diff options
| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-03-24 19:37:28 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-03-24 19:37:28 +0000 |
| commit | c6d3a5eaa0739cf78fef8427ca21c69dc1c99369 (patch) | |
| tree | 9a726e4a21f81564c2d3772320c2e4644302b153 | |
| parent | df931524ae52f74000edda2782e123c9b3459c10 (diff) | |
[X86][Broadwell] Merge xmm/ymm instructions instregex entries to reduce regex matches to reduce compile time
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328434 91177308-0d34-0410-b5e6-96231b3b80d8
| -rwxr-xr-x | lib/Target/X86/X86SchedBroadwell.td | 1608 |
1 files changed, 489 insertions, 1119 deletions
diff --git a/lib/Target/X86/X86SchedBroadwell.td b/lib/Target/X86/X86SchedBroadwell.td index 69799a59e00..b575d9848f6 100755 --- a/lib/Target/X86/X86SchedBroadwell.td +++ b/lib/Target/X86/X86SchedBroadwell.td @@ -22,7 +22,7 @@ def BroadwellModel : SchedMachineModel { // Based on the LSD (loop-stream detector) queue size and benchmarking data. let LoopMicroOpBufferSize = 50; - // This flag is set to allow the scheduler to assign a default model to + // This flag is set to allow the scheduler to assign a default model to // unrecognized opcodes. let CompleteModel = 0; } @@ -306,42 +306,20 @@ def: InstRW<[BWWriteResGroup1], (instregex "MMX_MOVD64from64rr", "MMX_PSRLQrr", "MMX_PSRLWri", "MMX_PSRLWrr", - "MOVPDI2DIrr", - "MOVPQIto64rr", - "PSLLDri", - "PSLLQri", - "PSLLWri", - "PSRADri", - "PSRAWri", - "PSRLDri", - "PSRLQri", - "PSRLWri", - "VMOVPDI2DIrr", - "VMOVPQIto64rr", - "VPSLLDYri", - "VPSLLDri", - "VPSLLQYri", - "VPSLLQri", - "VPSLLVQYrr", - "VPSLLVQrr", - "VPSLLWYri", - "VPSLLWri", - "VPSRADYri", - "VPSRADri", - "VPSRAWYri", - "VPSRAWri", - "VPSRLDYri", - "VPSRLDri", - "VPSRLQYri", - "VPSRLQri", - "VPSRLVQYrr", - "VPSRLVQrr", - "VPSRLWYri", - "VPSRLWri", - "VTESTPDYrr", - "VTESTPDrr", - "VTESTPSYrr", - "VTESTPSrr")>; + "(V?)MOVPDI2DIrr", + "(V?)MOVPQIto64rr", + "(V?)PSLLD(Y?)ri", + "(V?)PSLLQ(Y?)ri", + "VPSLLVQ(Y?)rr", + "(V?)PSLLW(Y?)ri", + "(V?)PSRAD(Y?)ri", + "(V?)PSRAW(Y?)ri", + "(V?)PSRLD(Y?)ri", + "(V?)PSRLQ(Y?)ri", + "VPSRLVQ(Y?)rr", + "(V?)PSRLW(Y?)ri", + "VTESTPD(Y?)rr", + "VTESTPS(Y?)rr")>; def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> { let Latency = 1; @@ -358,12 +336,7 @@ def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[BWWriteResGroup3], (instregex "ANDNPDrr", - "ANDNPSrr", - "ANDPDrr", - "ANDPSrr", - "INSERTPSrr", - "MMX_MOVD64rr", +def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr", "MMX_MOVD64to64rr", "MMX_MOVQ2DQrr", "MMX_PALIGNRrri", @@ -375,173 +348,73 @@ def: InstRW<[BWWriteResGroup3], (instregex "ANDNPDrr", "MMX_PUNPCKLBWirr", "MMX_PUNPCKLDQirr", "MMX_PUNPCKLWDirr", - "MOV64toPQIrr", - "MOVAPDrr", - "MOVAPSrr", - "MOVDDUPrr", - "MOVDI2PDIrr", - "MOVHLPSrr", - "MOVLHPSrr", - "MOVSDrr", - "MOVSHDUPrr", - "MOVSLDUPrr", - "MOVSSrr", - "MOVUPDrr", - "MOVUPSrr", - "ORPDrr", - "ORPSrr", - "PACKSSDWrr", - "PACKSSWBrr", - "PACKUSDWrr", - "PACKUSWBrr", - "PALIGNRrri", - "PBLENDWrri", - "PMOVSXBDrr", - "PMOVSXBQrr", - "PMOVSXBWrr", - "PMOVSXDQrr", - "PMOVSXWDrr", - "PMOVSXWQrr", - "PMOVZXBDrr", - "PMOVZXBQrr", - "PMOVZXBWrr", - "PMOVZXDQrr", - "PMOVZXWDrr", - "PMOVZXWQrr", - "PSHUFBrr", - "PSHUFDri", - "PSHUFHWri", - "PSHUFLWri", - "PSLLDQri", - "PSRLDQri", - "PUNPCKHBWrr", - "PUNPCKHDQrr", - "PUNPCKHQDQrr", - "PUNPCKHWDrr", - "PUNPCKLBWrr", - "PUNPCKLDQrr", - "PUNPCKLQDQrr", - "PUNPCKLWDrr", - "SHUFPDrri", - "SHUFPSrri", - "UNPCKHPDrr", - "UNPCKHPSrr", - "UNPCKLPDrr", - "UNPCKLPSrr", - "VANDNPDYrr", - "VANDNPDrr", - "VANDNPSYrr", - "VANDNPSrr", - "VANDPDYrr", - "VANDPDrr", - "VANDPSYrr", - "VANDPSrr", + "(V?)ANDNPD(Y?)rr", + "(V?)ANDNPS(Y?)rr", + "(V?)ANDPD(Y?)rr", + "(V?)ANDPS(Y?)rr", "VBROADCASTSSrr", - "VINSERTPSrr", - "VMOV64toPQIrr", - "VMOVAPDYrr", - "VMOVAPDrr", - "VMOVAPSYrr", - "VMOVAPSrr", - "VMOVDDUPYrr", - "VMOVDDUPrr", - "VMOVDI2PDIrr", - "VMOVHLPSrr", - "VMOVLHPSrr", - "VMOVSDrr", - "VMOVSHDUPYrr", - "VMOVSHDUPrr", - "VMOVSLDUPYrr", - "VMOVSLDUPrr", - "VMOVSSrr", - "VMOVUPDYrr", - "VMOVUPDrr", - "VMOVUPSYrr", - "VMOVUPSrr", - "VORPDYrr", - "VORPDrr", - "VORPSYrr", - "VORPSrr", - "VPACKSSDWYrr", - "VPACKSSDWrr", - "VPACKSSWBYrr", - "VPACKSSWBrr", - "VPACKUSDWYrr", - "VPACKUSDWrr", - "VPACKUSWBYrr", - "VPACKUSWBrr", - "VPALIGNRYrri", - "VPALIGNRrri", - "VPBLENDWYrri", - "VPBLENDWrri", + "(V?)INSERTPSrr", + "(V?)MOV64toPQIrr", + "(V?)MOVAPD(Y?)rr", + "(V?)MOVAPS(Y?)rr", + "(V?)MOVDDUP(Y?)rr", + "(V?)MOVDI2PDIrr", + "(V?)MOVHLPSrr", + "(V?)MOVLHPSrr", + "(V?)MOVSDrr", + "(V?)MOVSHDUP(Y?)rr", + "(V?)MOVSLDUP(Y?)rr", + "(V?)MOVSSrr", + "(V?)MOVUPD(Y?)rr", + "(V?)MOVUPS(Y?)rr", + "(V?)ORPD(Y?)rr", + "(V?)ORPS(Y?)rr", + "(V?)PACKSSDW(Y?)rr", + "(V?)PACKSSWB(Y?)rr", + "(V?)PACKUSDW(Y?)rr", + "(V?)PACKUSWB(Y?)rr", + "(V?)PALIGNR(Y?)rri", + "(V?)PBLENDW(Y?)rri", "VPBROADCASTDrr", "VPBROADCASTQrr", - "VPERMILPDYri", - "VPERMILPDYrr", - "VPERMILPDri", - "VPERMILPDrr", - "VPERMILPSYri", - "VPERMILPSYrr", - "VPERMILPSri", - "VPERMILPSrr", - "VPMOVSXBDrr", - "VPMOVSXBQrr", - "VPMOVSXBWrr", - "VPMOVSXDQrr", - "VPMOVSXWDrr", - "VPMOVSXWQrr", - "VPMOVZXBDrr", - "VPMOVZXBQrr", - "VPMOVZXBWrr", - "VPMOVZXDQrr", - "VPMOVZXWDrr", - "VPMOVZXWQrr", - "VPSHUFBYrr", - "VPSHUFBrr", - "VPSHUFDYri", - "VPSHUFDri", - "VPSHUFHWYri", - "VPSHUFHWri", - "VPSHUFLWYri", - "VPSHUFLWri", - "VPSLLDQYri", - "VPSLLDQri", - "VPSRLDQYri", - "VPSRLDQri", - "VPUNPCKHBWYrr", - "VPUNPCKHBWrr", - "VPUNPCKHDQYrr", - "VPUNPCKHDQrr", - "VPUNPCKHQDQYrr", - "VPUNPCKHQDQrr", - "VPUNPCKHWDYrr", - "VPUNPCKHWDrr", - "VPUNPCKLBWYrr", - "VPUNPCKLBWrr", - "VPUNPCKLDQYrr", - "VPUNPCKLDQrr", - "VPUNPCKLQDQYrr", - "VPUNPCKLQDQrr", - "VPUNPCKLWDYrr", - "VPUNPCKLWDrr", - "VSHUFPDYrri", - "VSHUFPDrri", - "VSHUFPSYrri", - "VSHUFPSrri", - "VUNPCKHPDYrr", - "VUNPCKHPDrr", - "VUNPCKHPSYrr", - "VUNPCKHPSrr", - "VUNPCKLPDYrr", - "VUNPCKLPDrr", - "VUNPCKLPSYrr", - "VUNPCKLPSrr", - "VXORPDYrr", - "VXORPDrr", - "VXORPSYrr", - "VXORPSrr", - "XORPDrr", - "XORPSrr")>; + "VPERMILPD(Y?)ri", + "VPERMILPD(Y?)rr", + "VPERMILPS(Y?)ri", + "VPERMILPS(Y?)rr", + "(V?)PMOVSXBDrr", + "(V?)PMOVSXBQrr", + "(V?)PMOVSXBWrr", + "(V?)PMOVSXDQrr", + "(V?)PMOVSXWDrr", + "(V?)PMOVSXWQrr", + "(V?)PMOVZXBDrr", + "(V?)PMOVZXBQrr", + "(V?)PMOVZXBWrr", + "(V?)PMOVZXDQrr", + "(V?)PMOVZXWDrr", + "(V?)PMOVZXWQrr", + "(V?)PSHUFB(Y?)rr", + "(V?)PSHUFD(Y?)ri", + "(V?)PSHUFHW(Y?)ri", + "(V?)PSHUFLW(Y?)ri", + "(V?)PSLLDQ(Y?)ri", + "(V?)PSRLDQ(Y?)ri", + "(V?)PUNPCKHBW(Y?)rr", + "(V?)PUNPCKHDQ(Y?)rr", + "(V?)PUNPCKHQDQ(Y?)rr", + "(V?)PUNPCKHWD(Y?)rr", + "(V?)PUNPCKLBW(Y?)rr", + "(V?)PUNPCKLDQ(Y?)rr", + "(V?)PUNPCKLQDQ(Y?)rr", + "(V?)PUNPCKLWD(Y?)rr", + "(V?)SHUFPD(Y?)rri", + "(V?)SHUFPS(Y?)rri", + "(V?)UNPCKHPD(Y?)rr", + "(V?)UNPCKHPS(Y?)rr", + "(V?)UNPCKLPD(Y?)rr", + "(V?)UNPCKLPS(Y?)rr", + "(V?)XORPD(Y?)rr", + "(V?)XORPS(Y?)rr")>; def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> { let Latency = 1; @@ -643,175 +516,71 @@ def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr", "MMX_PSUBUSBirr", "MMX_PSUBUSWirr", "MMX_PSUBWirr", - "PABSBrr", - "PABSDrr", - "PABSWrr", - "PADDBrr", - "PADDDrr", - "PADDQrr", - "PADDSBrr", - "PADDSWrr", - "PADDUSBrr", - "PADDUSWrr", - "PADDWrr", - "PAVGBrr", - "PAVGWrr", - "PCMPEQBrr", - "PCMPEQDrr", - "PCMPEQQrr", - "PCMPEQWrr", - "PCMPGTBrr", - "PCMPGTDrr", - "PCMPGTWrr", - "PMAXSBrr", - "PMAXSDrr", - "PMAXSWrr", - "PMAXUBrr", - "PMAXUDrr", - "PMAXUWrr", - "PMINSBrr", - "PMINSDrr", - "PMINSWrr", - "PMINUBrr", - "PMINUDrr", - "PMINUWrr", - "PSIGNBrr", - "PSIGNDrr", - "PSIGNWrr", - "PSUBBrr", - "PSUBDrr", - "PSUBQrr", - "PSUBSBrr", - "PSUBSWrr", - "PSUBUSBrr", - "PSUBUSWrr", - "PSUBWrr", - "VPABSBYrr", - "VPABSBrr", - "VPABSDYrr", - "VPABSDrr", - "VPABSWYrr", - "VPABSWrr", - "VPADDBYrr", - "VPADDBrr", - "VPADDDYrr", - "VPADDDrr", - "VPADDQYrr", - "VPADDQrr", - "VPADDSBYrr", - "VPADDSBrr", - "VPADDSWYrr", - "VPADDSWrr", - "VPADDUSBYrr", - "VPADDUSBrr", - "VPADDUSWYrr", - "VPADDUSWrr", - "VPADDWYrr", - "VPADDWrr", - "VPAVGBYrr", - "VPAVGBrr", - "VPAVGWYrr", - "VPAVGWrr", - "VPCMPEQBYrr", - "VPCMPEQBrr", - "VPCMPEQDYrr", - "VPCMPEQDrr", - "VPCMPEQQYrr", - "VPCMPEQQrr", - "VPCMPEQWYrr", - "VPCMPEQWrr", - "VPCMPGTBYrr", - "VPCMPGTBrr", - "VPCMPGTDYrr", - "VPCMPGTDrr", - "VPCMPGTWYrr", - "VPCMPGTWrr", - "VPMAXSBYrr", - "VPMAXSBrr", - "VPMAXSDYrr", - "VPMAXSDrr", - "VPMAXSWYrr", - "VPMAXSWrr", - "VPMAXUBYrr", - "VPMAXUBrr", - "VPMAXUDYrr", - "VPMAXUDrr", - "VPMAXUWYrr", - "VPMAXUWrr", - "VPMINSBYrr", - "VPMINSBrr", - "VPMINSDYrr", - "VPMINSDrr", - "VPMINSWYrr", - "VPMINSWrr", - "VPMINUBYrr", - "VPMINUBrr", - "VPMINUDYrr", - "VPMINUDrr", - "VPMINUWYrr", - "VPMINUWrr", - "VPSIGNBYrr", - "VPSIGNBrr", - "VPSIGNDYrr", - "VPSIGNDrr", - "VPSIGNWYrr", - "VPSIGNWrr", - "VPSUBBYrr", - "VPSUBBrr", - "VPSUBDYrr", - "VPSUBDrr", - "VPSUBQYrr", - "VPSUBQrr", - "VPSUBSBYrr", - "VPSUBSBrr", - "VPSUBSWYrr", - "VPSUBSWrr", - "VPSUBUSBYrr", - "VPSUBUSBrr", - "VPSUBUSWYrr", - "VPSUBUSWrr", - "VPSUBWYrr", - "VPSUBWrr")>; + "(V?)PABSB(Y?)rr", + "(V?)PABSD(Y?)rr", + "(V?)PABSW(Y?)rr", + "(V?)PADDB(Y?)rr", + "(V?)PADDD(Y?)rr", + "(V?)PADDQ(Y?)rr", + "(V?)PADDSB(Y?)rr", + "(V?)PADDSW(Y?)rr", + "(V?)PADDUSB(Y?)rr", + "(V?)PADDUSW(Y?)rr", + "(V?)PADDW(Y?)rr", + "(V?)PAVGB(Y?)rr", + "(V?)PAVGW(Y?)rr", + "(V?)PCMPEQB(Y?)rr", + "(V?)PCMPEQD(Y?)rr", + "(V?)PCMPEQQ(Y?)rr", + "(V?)PCMPEQW(Y?)rr", + "(V?)PCMPGTB(Y?)rr", + "(V?)PCMPGTD(Y?)rr", + "(V?)PCMPGTW(Y?)rr", + "(V?)PMAXSB(Y?)rr", + "(V?)PMAXSD(Y?)rr", + "(V?)PMAXSW(Y?)rr", + "(V?)PMAXUB(Y?)rr", + "(V?)PMAXUD(Y?)rr", + "(V?)PMAXUW(Y?)rr", + "(V?)PMINSB(Y?)rr", + "(V?)PMINSD(Y?)rr", + "(V?)PMINSW(Y?)rr", + "(V?)PMINUB(Y?)rr", + "(V?)PMINUD(Y?)rr", + "(V?)PMINUW(Y?)rr", + "(V?)PSIGNB(Y?)rr", + "(V?)PSIGND(Y?)rr", + "(V?)PSIGNW(Y?)rr", + "(V?)PSUBB(Y?)rr", + "(V?)PSUBD(Y?)rr", + "(V?)PSUBQ(Y?)rr", + "(V?)PSUBSB(Y?)rr", + "(V?)PSUBSW(Y?)rr", + "(V?)PSUBUSB(Y?)rr", + "(V?)PSUBUSW(Y?)rr", + "(V?)PSUBW(Y?)rr")>; def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> { let Latency = 1; let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[BWWriteResGroup8], (instregex "BLENDPDrri", - "BLENDPSrri", - "MMX_MOVQ64rr", +def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVQ64rr", "MMX_PANDNirr", "MMX_PANDirr", "MMX_PORirr", "MMX_PXORirr", - "MOVDQArr", - "MOVDQUrr", - "MOVPQI2QIrr", - "PANDNrr", - "PANDrr", - "PORrr", - "PXORrr", - "VBLENDPDYrri", - "VBLENDPDrri", - "VBLENDPSYrri", - "VBLENDPSrri", - "VMOVDQAYrr", - "VMOVDQArr", - "VMOVDQUYrr", - "VMOVDQUrr", - "VMOVPQI2QIrr", + "(V?)BLENDPD(Y?)rri", + "(V?)BLENDPS(Y?)rri", + "(V?)MOVDQA(Y?)rr", + "(V?)MOVDQU(Y?)rr", + "(V?)MOVPQI2QIrr", "VMOVZPQILo2PQIrr", - "VPANDNYrr", - "VPANDNrr", - "VPANDYrr", - "VPANDrr", - "VPBLENDDYrri", - "VPBLENDDrri", - "VPORYrr", - "VPORrr", - "VPXORYrr", - "VPXORrr")>; + "(V?)PANDN(Y?)rr", + "(V?)PAND(Y?)rr", + "VPBLENDD(Y?)rri", + "(V?)POR(Y?)rr", + "(V?)PXOR(Y?)rr")>; def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> { let Latency = 1; @@ -879,58 +648,31 @@ def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm", "MOV(16|32|64)mr", "MOV8mi", "MOV8mr", - "MOVAPDmr", - "MOVAPSmr", - "MOVDQAmr", - "MOVDQUmr", - "MOVHPDmr", - "MOVHPSmr", - "MOVLPDmr", - "MOVLPSmr", - "MOVNTDQmr", "MOVNTI_64mr", "MOVNTImr", - "MOVNTPDmr", - "MOVNTPSmr", - "MOVPDI2DImr", - "MOVPQI2QImr", - "MOVPQIto64mr", - "MOVSDmr", - "MOVSSmr", - "MOVUPDmr", - "MOVUPSmr", "ST_FP32m", "ST_FP64m", "ST_FP80m", "VEXTRACTF128mr", "VEXTRACTI128mr", - "VMOVAPDYmr", - "VMOVAPDmr", - "VMOVAPSYmr", - "VMOVAPSmr", - "VMOVDQAYmr", - "VMOVDQAmr", - "VMOVDQUYmr", - "VMOVDQUmr", - "VMOVHPDmr", - "VMOVHPSmr", - "VMOVLPDmr", - "VMOVLPSmr", - "VMOVNTDQYmr", - "VMOVNTDQmr", - "VMOVNTPDYmr", - "VMOVNTPDmr", - "VMOVNTPSYmr", - "VMOVNTPSmr", - "VMOVPDI2DImr", - "VMOVPQI2QImr", - "VMOVPQIto64mr", - "VMOVSDmr", - "VMOVSSmr", - "VMOVUPDYmr", - "VMOVUPDmr", - "VMOVUPSYmr", - "VMOVUPSmr")>; + "(V?)MOVAPD(Y?)mr", + "(V?)MOVAPS(Y?)mr", + "(V?)MOVDQA(Y?)mr", + "(V?)MOVDQU(Y?)mr", + "(V?)MOVHPDmr", + "(V?)MOVHPSmr", + "(V?)MOVLPDmr", + "(V?)MOVLPSmr", + "(V?)MOVNTDQ(V?)mr", + "(V?)MOVNTPD(V?)mr", + "(V?)MOVNTPS(V?)mr", + "(V?)MOVPDI2DImr", + "(V?)MOVPQI2QImr", + "(V?)MOVPQIto64mr", + "(V?)MOVSDmr", + "(V?)MOVSSmr", + "(V?)MOVUPD(Y?)mr", + "(V?)MOVUPS(Y?)mr")>; def BWWriteResGroup11 : SchedWriteRes<[BWPort5]> { let Latency = 2; @@ -941,20 +683,13 @@ def: InstRW<[BWWriteResGroup11], (instregex "BLENDVPDrr0", "BLENDVPSrr0", "MMX_PINSRWrr", "PBLENDVBrr0", - "PINSRBrr", - "PINSRDrr", - "PINSRQrr", - "PINSRWrr", - "VBLENDVPDYrr", - "VBLENDVPDrr", - "VBLENDVPSYrr", - "VBLENDVPSrr", - "VPBLENDVBYrr", - "VPBLENDVBrr", - "VPINSRBrr", - "VPINSRDrr", - "VPINSRQrr", - "VPINSRWrr")>; + "VBLENDVPD(Y?)rr", + "VBLENDVPS(Y?)rr", + "VPBLENDVB(Y?)rr", + "(V?)PINSRBrr", + "(V?)PINSRDrr", + "(V?)PINSRQrr", + "(V?)PINSRWrr")>; def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> { let Latency = 2; @@ -988,41 +723,24 @@ def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[BWWriteResGroup15], (instregex "CVTPS2PDrr", - "CVTSS2SDrr", - "EXTRACTPSrr", - "MMX_PEXTRWrr", - "PEXTRBrr", - "PEXTRDrr", - "PEXTRQrr", - "PEXTRWrr", - "PSLLDrr", - "PSLLQrr", - "PSLLWrr", - "PSRADrr", - "PSRAWrr", - "PSRLDrr", - "PSRLQrr", - "PSRLWrr", - "PTESTrr", - "VCVTPH2PSYrr", - "VCVTPH2PSrr", - "VCVTPS2PDrr", - "VCVTSS2SDrr", - "VEXTRACTPSrr", - "VPEXTRBrr", - "VPEXTRDrr", - "VPEXTRQrr", - "VPEXTRWrr", - "VPSLLDrr", - "VPSLLQrr", - "VPSLLWrr", - "VPSRADrr", - "VPSRAWrr", - "VPSRLDrr", - "VPSRLQrr", - "VPSRLWrr", - "VPTESTrr")>; +def: InstRW<[BWWriteResGroup15], (instregex "MMX_PEXTRWrr", + "VCVTPH2PS(Y?)rr", + "(V?)CVTPS2PDrr", + "(V?)CVTSS2SDrr", + "(V?)EXTRACTPSrr", + "(V?)PEXTRBrr", + "(V?)PEXTRDrr", + "(V?)PEXTRQrr", + "(V?)PEXTRWrr", + "(V?)PSLLDrr", + "(V?)PSLLQrr", + "(V?)PSLLWrr", + "(V?)PSRADrr", + "(V?)PSRAWrr", + "(V?)PSRLDrr", + "(V?)PSRLQrr", + "(V?)PSRLWrr", + "(V?)PTESTrr")>; def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> { let Latency = 2; @@ -1072,18 +790,12 @@ def BWWriteResGroup21 : SchedWriteRes<[BWPort4,BWPort5,BWPort237]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[BWWriteResGroup21], (instregex "EXTRACTPSmr", - "PEXTRBmr", - "PEXTRDmr", - "PEXTRQmr", - "PEXTRWmr", - "STMXCSR", - "VEXTRACTPSmr", - "VPEXTRBmr", - "VPEXTRDmr", - "VPEXTRQmr", - "VPEXTRWmr", - "VSTMXCSR")>; +def: InstRW<[BWWriteResGroup21], (instregex "(V?)EXTRACTPSmr", + "(V?)PEXTRBmr", + "(V?)PEXTRDmr", + "(V?)PEXTRQmr", + "(V?)PEXTRWmr", + "(V?)STMXCSR")>; def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> { let Latency = 2; @@ -1124,15 +836,9 @@ def BWWriteResGroup26 : SchedWriteRes<[BWPort0]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[BWWriteResGroup26], (instregex "MOVMSKPDrr", - "MOVMSKPSrr", - "PMOVMSKBrr", - "VMOVMSKPDYrr", - "VMOVMSKPDrr", - "VMOVMSKPSYrr", - "VMOVMSKPSrr", - "VPMOVMSKBYrr", - "VPMOVMSKBrr")>; +def: InstRW<[BWWriteResGroup26], (instregex "(V?)MOVMSKPD(Y?)rr", + "(V?)MOVMSKPS(Y?)rr", + "(V?)PMOVMSKB(Y?)rr")>; def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> { let Latency = 3; @@ -1141,98 +847,54 @@ def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> { } def: InstRW<[BWWriteResGroup27], (instrs IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>; def: InstRW<[BWWriteResGroup27], (instrs IMUL8r, MUL8r)>; -def: InstRW<[BWWriteResGroup27], (instregex "ADDPDrr", - "ADDPSrr", - "ADDSDrr", - "ADDSSrr", - "ADDSUBPDrr", - "ADDSUBPSrr", - "ADD_FPrST0", +def: InstRW<[BWWriteResGroup27], (instregex "ADD_FPrST0", "ADD_FST0r", "ADD_FrST0", "BSF(16|32|64)rr", "BSR(16|32|64)rr", - "CMPPDrri", - "CMPPSrri", - "CMPSDrr", - "CMPSSrr", - "COMISDrr", - "COMISSrr", - "CVTDQ2PSrr", - "CVTPS2DQrr", - "CVTTPS2DQrr", "LZCNT(16|32|64)rr", - "MAX(C?)PDrr", - "MAX(C?)PSrr", - "MAX(C?)SDrr", - "MAX(C?)SSrr", - "MIN(C?)PDrr", - "MIN(C?)PSrr", - "MIN(C?)SDrr", - "MIN(C?)SSrr", "MMX_CVTPI2PSirr", "PDEP(32|64)rr", "PEXT(32|64)rr", "POPCNT(16|32|64)rr", "SHLD(16|32|64)rri8", "SHRD(16|32|64)rri8", - "SUBPDrr", - "SUBPSrr", "SUBR_FPrST0", "SUBR_FST0r", "SUBR_FrST0", - "SUBSDrr", - "SUBSSrr", "SUB_FPrST0", "SUB_FST0r", "SUB_FrST0", "TZCNT(16|32|64)rr", - "UCOMISDrr", - "UCOMISSrr", - "VADDPDYrr", - "VADDPDrr", - "VADDPSYrr", - "VADDPSrr", - "VADDSDrr", - "VADDSSrr", - "VADDSUBPDYrr", - "VADDSUBPDrr", - "VADDSUBPSYrr", - "VADDSUBPSrr", - "VCMPPDYrri", - "VCMPPDrri", - "VCMPPSYrri", - "VCMPPSrri", - "VCMPSDrr", - "VCMPSSrr", - "VCOMISDrr", - "VCOMISSrr", - "VCVTDQ2PSYrr", - "VCVTDQ2PSrr", - "VCVTPS2DQYrr", - "VCVTPS2DQrr", - "VCVTTPS2DQYrr", - "VCVTTPS2DQrr", - "VMAX(C?)PDYrr", - "VMAX(C?)PDrr", - "VMAX(C?)PSYrr", - "VMAX(C?)PSrr", - "VMAX(C?)SDrr", - "VMAX(C?)SSrr", - "VMIN(C?)PDYrr", - "VMIN(C?)PDrr", - "VMIN(C?)PSYrr", - "VMIN(C?)PSrr", - "VMIN(C?)SDrr", - "VMIN(C?)SSrr", - "VSUBPDYrr", - "VSUBPDrr", - "VSUBPSYrr", - "VSUBPSrr", - "VSUBSDrr", - "VSUBSSrr", - "VUCOMISDrr", - "VUCOMISSrr")>; + "(V?)ADDPD(Y?)rr", + "(V?)ADDPS(Y?)rr", + "(V?)ADDSDrr", + "(V?)ADDSSrr", + "(V?)ADDSUBPD(Y?)rr", + "(V?)ADDSUBPS(Y?)rr", + "(V?)CMPPD(Y?)rri", + "(V?)CMPPS(Y?)rri", + "(V?)CMPSDrr", + "(V?)CMPSSrr", + "(V?)COMISDrr", + "(V?)COMISSrr", + "(V?)CVTDQ2PS(Y?)rr", + "(V?)CVTPS2DQ(Y?)rr", + "(V?)CVTTPS2DQ(Y?)rr", + "(V?)MAX(C?)PD(Y?)rr", + "(V?)MAX(C?)PS(Y?)rr", + "(V?)MAX(C?)SDrr", + "(V?)MAX(C?)SSrr", + "(V?)MIN(C?)PD(Y?)rr", + "(V?)MIN(C?)PS(Y?)rr", + "(V?)MIN(C?)SDrr", + "(V?)MIN(C?)SSrr", + "(V?)SUBPD(Y?)rr", + "(V?)SUBPS(Y?)rr", + "(V?)SUBSDrr", + "(V?)SUBSSrr", + "(V?)UCOMISDrr", + "(V?)UCOMISSrr")>; def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> { let Latency = 3; @@ -1252,12 +914,10 @@ def: InstRW<[BWWriteResGroup28], (instregex "VBROADCASTSDYrr", "VEXTRACTI128rr", "VINSERTF128rr", "VINSERTI128rr", - "VPBROADCASTBYrr", - "VPBROADCASTBrr", + "VPBROADCASTB(Y?)rr", "VPBROADCASTDYrr", "VPBROADCASTQYrr", - "VPBROADCASTWYrr", - "VPBROADCASTWrr", + "VPBROADCASTW(Y?)rr", "VPERM2F128rr", "VPERM2I128rr", "VPERMDYrr", @@ -1282,16 +942,10 @@ def BWWriteResGroup29 : SchedWriteRes<[BWPort01]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[BWWriteResGroup29], (instregex "MULPDrr", - "MULPSrr", - "MULSDrr", - "MULSSrr", - "VMULPDYrr", - "VMULPDrr", - "VMULPSYrr", - "VMULPSrr", - "VMULSDrr", - "VMULSSrr")>; +def: InstRW<[BWWriteResGroup29], (instregex "(V?)MULPD(Y?)rr", + "(V?)MULPS(Y?)rr", + "(V?)MULSDrr", + "(V?)MULSSrr")>; def BWWriteResGroup30 : SchedWriteRes<[BWPort0156]> { let Latency = 3; @@ -1306,12 +960,9 @@ def BWWriteResGroup31 : SchedWriteRes<[BWPort0,BWPort5]> { let NumMicroOps = 3; let ResourceCycles = [2,1]; } -def: InstRW<[BWWriteResGroup31], (instregex "VPSLLVDYrr", - "VPSLLVDrr", - "VPSRAVDYrr", - "VPSRAVDrr", - "VPSRLVDYrr", - "VPSRLVDrr")>; +def: InstRW<[BWWriteResGroup31], (instregex "VPSLLVD(Y?)rr", + "VPSRAVD(Y?)rr", + "VPSRLVD(Y?)rr")>; def BWWriteResGroup32 : SchedWriteRes<[BWPort5,BWPort15]> { let Latency = 3; @@ -1324,24 +975,12 @@ def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDDrr", "MMX_PHSUBDrr", "MMX_PHSUBSWrr", "MMX_PHSUBWrr", - "PHADDDrr", - "PHADDSWrr", - "PHADDWrr", - "PHSUBDrr", - "PHSUBSWrr", - "PHSUBWrr", - "VPHADDDYrr", - "VPHADDDrr", - "VPHADDSWYrr", - "VPHADDSWrr", - "VPHADDWYrr", - "VPHADDWrr", - "VPHSUBDYrr", - "VPHSUBDrr", - "VPHSUBSWYrr", - "VPHSUBSWrr", - "VPHSUBWYrr", - "VPHSUBWrr")>; + "(V?)PHADDD(Y?)rr", + "(V?)PHADDSW(Y?)rr", + "(V?)PHADDW(Y?)rr", + "(V?)PHSUBD(Y?)rr", + "(V?)PHSUBSW(Y?)rr", + "(V?)PHSUBW(Y?)rr")>; def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> { let Latency = 3; @@ -1400,22 +1039,14 @@ def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[BWWriteResGroup39], (instregex "CVTSD2SI64rr", - "CVTSD2SIrr", - "CVTSS2SI64rr", - "CVTSS2SIrr", - "CVTTSD2SI64rr", - "CVTTSD2SIrr", - "CVTTSS2SI64rr", - "CVTTSS2SIrr", - "VCVTSD2SI64rr", - "VCVTSD2SIrr", - "VCVTSS2SI64rr", - "VCVTSS2SIrr", - "VCVTTSD2SI64rr", - "VCVTTSD2SIrr", - "VCVTTSS2SI64rr", - "VCVTTSS2SIrr")>; +def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVTSD2SI64rr", + "(V?)CVTSD2SIrr", + "(V?)CVTSS2SI64rr", + "(V?)CVTSS2SIrr", + "(V?)CVTTSD2SI64rr", + "(V?)CVTTSD2SIrr", + "(V?)CVTTSS2SI64rr", + "(V?)CVTTSS2SIrr")>; def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> { let Latency = 4; @@ -1446,28 +1077,20 @@ def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> { let ResourceCycles = [1,1]; } def: InstRW<[BWWriteResGroup42], (instrs IMUL64r, MUL64r, MULX64rr)>; -def: InstRW<[BWWriteResGroup42], (instregex "CVTDQ2PDrr", - "CVTPD2DQrr", - "CVTPD2PSrr", - "CVTSD2SSrr", - "CVTSI642SDrr", - "CVTSI2SDrr", - "CVTSI2SSrr", - "CVTTPD2DQrr", - "MMX_CVTPD2PIirr", +def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPD2PIirr", "MMX_CVTPI2PDirr", "MMX_CVTPS2PIirr", "MMX_CVTTPD2PIirr", "MMX_CVTTPS2PIirr", - "VCVTDQ2PDrr", - "VCVTPD2DQrr", - "VCVTPD2PSrr", + "(V?)CVTDQ2PDrr", + "(V?)CVTPD2DQrr", + "(V?)CVTPD2PSrr", "VCVTPS2PHrr", - "VCVTSD2SSrr", - "VCVTSI642SDrr", - "VCVTSI2SDrr", - "VCVTSI2SSrr", - "VCVTTPD2DQrr")>; + "(V?)CVTSD2SSrr", + "(V?)CVTSI642SDrr", + "(V?)CVTSI2SDrr", + "(V?)CVTSI2SSrr", + "(V?)CVTTPD2DQrr")>; def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { let Latency = 4; @@ -1495,8 +1118,7 @@ def: InstRW<[BWWriteResGroup44], (instregex "ISTT_FP16m", "IST_FP16m", "IST_FP32m", "IST_FP64m", - "VCVTPS2PHYmr", - "VCVTPS2PHmr")>; + "VCVTPS2PH(Y?)mr")>; def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> { let Latency = 4; @@ -1528,46 +1150,21 @@ def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr", "MUL_FPrST0", "MUL_FST0r", "MUL_FrST0", - "PCMPGTQrr", - "PHMINPOSUWrr", - "PMADDUBSWrr", - "PMADDWDrr", - "PMULDQrr", - "PMULHRSWrr", - "PMULHUWrr", - "PMULHWrr", - "PMULLWrr", - "PMULUDQrr", - "PSADBWrr", - "RCPPSr", - "RCPSSr", - "RSQRTPSr", - "RSQRTSSr", - "VPCMPGTQYrr", - "VPCMPGTQrr", - "VPHMINPOSUWrr", - "VPMADDUBSWYrr", - "VPMADDUBSWrr", - "VPMADDWDYrr", - "VPMADDWDrr", - "VPMULDQYrr", - "VPMULDQrr", - "VPMULHRSWYrr", - "VPMULHRSWrr", - "VPMULHUWYrr", - "VPMULHUWrr", - "VPMULHWYrr", - "VPMULHWrr", - "VPMULLWYrr", - "VPMULLWrr", - "VPMULUDQYrr", - "VPMULUDQrr", - "VPSADBWYrr", - "VPSADBWrr", - "VRCPPSr", - "VRCPSSr", - "VRSQRTPSr", - "VRSQRTSSr")>; + "(V?)PCMPGTQ(Y?)rr", + "(V?)PHMINPOSUWrr", + "(V?)PMADDUBSW(Y?)rr", + "(V?)PMADDWD(Y?)rr", + "(V?)PMULDQ(Y?)rr", + "(V?)PMULHRSW(Y?)rr", + "(V?)PMULHUW(Y?)rr", + "(V?)PMULHW(Y?)rr", + "(V?)PMULLW(Y?)rr", + "(V?)PMULUDQ(Y?)rr", + "(V?)PSADBW(Y?)rr", + "(V?)RCPPSr", + "(V?)RCPSSr", + "(V?)RSQRTPSr", + "(V?)RSQRTSSr")>; def BWWriteResGroup48 : SchedWriteRes<[BWPort01]> { let Latency = 5; @@ -1583,30 +1180,13 @@ def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[BWWriteResGroup49], (instregex "LDDQUrm", - "MMX_MOVD64rm", +def: InstRW<[BWWriteResGroup49], (instregex "MMX_MOVD64rm", "MMX_MOVD64to64rm", "MMX_MOVQ64rm", "MOV(16|32|64)rm", - "MOV64toPQIrm", - "MOV8rm", - "MOVAPDrm", - "MOVAPSrm", - "MOVDDUPrm", - "MOVDI2PDIrm", - "MOVDQArm", - "MOVDQUrm", - "MOVNTDQArm", - "MOVQI2PQIrm", - "MOVSDrm", - "MOVSHDUPrm", - "MOVSLDUPrm", - "MOVSSrm", "MOVSX(16|32|64)rm16", "MOVSX(16|32|64)rm32", "MOVSX(16|32|64)rm8", - "MOVUPDrm", - "MOVUPSrm", "MOVZX(16|32|64)rm16", "MOVZX(16|32|64)rm8", "PREFETCHNTA", @@ -1614,22 +1194,22 @@ def: InstRW<[BWWriteResGroup49], (instregex "LDDQUrm", "PREFETCHT1", "PREFETCHT2", "VBROADCASTSSrm", - "VLDDQUrm", - "VMOV64toPQIrm", - "VMOVAPDrm", - "VMOVAPSrm", - "VMOVDDUPrm", - "VMOVDI2PDIrm", - "VMOVDQArm", - "VMOVDQUrm", - "VMOVNTDQArm", - "VMOVQI2PQIrm", - "VMOVSDrm", - "VMOVSHDUPrm", - "VMOVSLDUPrm", - "VMOVSSrm", - "VMOVUPDrm", - "VMOVUPSrm", + "(V?)LDDQUrm", + "(V?)MOV64toPQIrm", + "(V?)MOVAPDrm", + "(V?)MOVAPSrm", + "(V?)MOVDDUPrm", + "(V?)MOVDI2PDIrm", + "(V?)MOVDQArm", + "(V?)MOVDQUrm", + "(V?)MOVNTDQArm", + "(V?)MOVQI2PQIrm", + "(V?)MOVSDrm", + "(V?)MOVSHDUPrm", + "(V?)MOVSLDUPrm", + "(V?)MOVSSrm", + "(V?)MOVUPDrm", + "(V?)MOVUPSrm", "VPBROADCASTDrm", "VPBROADCASTQrm")>; @@ -1638,20 +1218,11 @@ def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> { let NumMicroOps = 3; let ResourceCycles = [1,2]; } -def: InstRW<[BWWriteResGroup50], (instregex "CVTSI642SSrr", - "HADDPDrr", - "HADDPSrr", - "HSUBPDrr", - "HSUBPSrr", - "VCVTSI642SSrr", - "VHADDPDYrr", - "VHADDPDrr", - "VHADDPSYrr", - "VHADDPSrr", - "VHSUBPDYrr", - "VHSUBPDrr", - "VHSUBPSYrr", - "VHSUBPSrr")>; +def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr", + "(V?)HADDPD(Y?)rr", + "(V?)HADDPS(Y?)rr", + "(V?)HSUBPD(Y?)rr", + "(V?)HSUBPS(Y?)rr")>; def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> { let Latency = 5; @@ -1672,14 +1243,10 @@ def BWWriteResGroup53 : SchedWriteRes<[BWPort0,BWPort4,BWPort237,BWPort15]> { let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } -def: InstRW<[BWWriteResGroup53], (instregex "VMASKMOVPDYmr", - "VMASKMOVPDmr", - "VMASKMOVPSYmr", - "VMASKMOVPSmr", - "VPMASKMOVDYmr", - "VPMASKMOVDmr", - "VPMASKMOVQYmr", - "VPMASKMOVQmr")>; +def: InstRW<[BWWriteResGroup53], (instregex "VMASKMOVPD(Y?)mr", + "VMASKMOVPS(Y?)mr", + "VPMASKMOVD(Y?)mr", + "VPMASKMOVQ(Y?)mr")>; def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> { let Latency = 5; @@ -1734,25 +1301,17 @@ def: InstRW<[BWWriteResGroup58], (instregex "LD_F32m", "VMOVUPSYrm", "VPBROADCASTDYrm", "VPBROADCASTQYrm", - "ROUNDPDr", - "ROUNDPSr", - "ROUNDSDr", - "ROUNDSSr", - "VROUNDPDr", - "VROUNDPSr", - "VROUNDSDr", - "VROUNDSSr", - "VROUNDPDYr", - "VROUNDPSYr")>; + "(V?)ROUNDPD(Y?)r", + "(V?)ROUNDPS(Y?)r", + "(V?)ROUNDSDr", + "(V?)ROUNDSSr")>; def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> { let Latency = 6; let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[BWWriteResGroup59], (instregex "CVTPS2PDrm", - "CVTSS2SDrm", - "MMX_PSLLDrm", +def: InstRW<[BWWriteResGroup59], (instregex "MMX_PSLLDrm", "MMX_PSLLQrm", "MMX_PSLLWrm", "MMX_PSRADrm", @@ -1760,10 +1319,9 @@ def: InstRW<[BWWriteResGroup59], (instregex "CVTPS2PDrm", "MMX_PSRLDrm", "MMX_PSRLQrm", "MMX_PSRLWrm", - "VCVTPH2PSYrm", - "VCVTPH2PSrm", - "VCVTPS2PDrm", - "VCVTSS2SDrm", + "VCVTPH2PS(Y?)rm", + "(V?)CVTPS2PDrm", + "(V?)CVTSS2SDrm", "VPSLLVQrm", "VPSRLVQrm", "VTESTPDrm", @@ -1785,12 +1343,7 @@ def BWWriteResGroup61 : SchedWriteRes<[BWPort5,BWPort23]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[BWWriteResGroup61], (instregex "ANDNPDrm", - "ANDNPSrm", - "ANDPDrm", - "ANDPSrm", - "INSERTPSrm", - "MMX_PALIGNRrmi", +def: InstRW<[BWWriteResGroup61], (instregex "MMX_PALIGNRrmi", "MMX_PINSRWrm", "MMX_PSHUFBrm", "MMX_PSHUFWmi", @@ -1800,111 +1353,63 @@ def: InstRW<[BWWriteResGroup61], (instregex "ANDNPDrm", "MMX_PUNPCKLBWirm", "MMX_PUNPCKLDQirm", "MMX_PUNPCKLWDirm", - "MOVHPDrm", - "MOVHPSrm", - "MOVLPDrm", - "MOVLPSrm", - "ORPDrm", - "ORPSrm", - "PACKSSDWrm", - "PACKSSWBrm", - "PACKUSDWrm", - "PACKUSWBrm", - "PALIGNRrmi", - "PBLENDWrmi", - "PINSRBrm", - "PINSRDrm", - "PINSRQrm", - "PINSRWrm", - "PMOVSXBDrm", - "PMOVSXBQrm", - "PMOVSXBWrm", - "PMOVSXDQrm", - "PMOVSXWDrm", - "PMOVSXWQrm", - "PMOVZXBDrm", - "PMOVZXBQrm", - "PMOVZXBWrm", - "PMOVZXDQrm", - "PMOVZXWDrm", - "PMOVZXWQrm", - "PSHUFBrm", - "PSHUFDmi", - "PSHUFHWmi", - "PSHUFLWmi", - "PUNPCKHBWrm", - "PUNPCKHDQrm", - "PUNPCKHQDQrm", - "PUNPCKHWDrm", - "PUNPCKLBWrm", - "PUNPCKLDQrm", - "PUNPCKLQDQrm", - "PUNPCKLWDrm", - "SHUFPDrmi", - "SHUFPSrmi", - "UNPCKHPDrm", - "UNPCKHPSrm", - "UNPCKLPDrm", - "UNPCKLPSrm", - "VANDNPDrm", - "VANDNPSrm", - "VANDPDrm", - "VANDPSrm", - "VINSERTPSrm", - "VMOVHPDrm", - "VMOVHPSrm", - "VMOVLPDrm", - "VMOVLPSrm", - "VORPDrm", - "VORPSrm", - "VPACKSSDWrm", - "VPACKSSWBrm", - "VPACKUSDWrm", - "VPACKUSWBrm", - "VPALIGNRrmi", - "VPBLENDWrmi", + "(V?)ANDNPDrm", + "(V?)ANDNPSrm", + "(V?)ANDPDrm", + "(V?)ANDPSrm", + "(V?)INSERTPSrm", + "(V?)MOVHPDrm", + "(V?)MOVHPSrm", + "(V?)MOVLPDrm", + "(V?)MOVLPSrm", + "(V?)ORPDrm", + "(V?)ORPSrm", + "(V?)PACKSSDWrm", + "(V?)PACKSSWBrm", + "(V?)PACKUSDWrm", + "(V?)PACKUSWBrm", + "(V?)PALIGNRrmi", + "(V?)PBLENDWrmi", "VPERMILPDmi", "VPERMILPDrm", "VPERMILPSmi", "VPERMILPSrm", - "VPINSRBrm", - "VPINSRDrm", - "VPINSRQrm", - "VPINSRWrm", - "VPMOVSXBDrm", - "VPMOVSXBQrm", - "VPMOVSXBWrm", - "VPMOVSXDQrm", - "VPMOVSXWDrm", - "VPMOVSXWQrm", - "VPMOVZXBDrm", - "VPMOVZXBQrm", - "VPMOVZXBWrm", - "VPMOVZXDQrm", - "VPMOVZXWDrm", - "VPMOVZXWQrm", - "VPSHUFBrm", - "VPSHUFDmi", - "VPSHUFHWmi", - "VPSHUFLWmi", - "VPUNPCKHBWrm", - "VPUNPCKHDQrm", - "VPUNPCKHQDQrm", - "VPUNPCKHWDrm", - "VPUNPCKLBWrm", - "VPUNPCKLDQrm", - "VPUNPCKLQDQrm", - "VPUNPCKLWDrm", - "VSHUFPDrmi", - "VSHUFPSrmi", - "VUNPCKHPDrm", - "VUNPCKHPSrm", - "VUNPCKLPDrm", - "VUNPCKLPSrm", - "VXORPDrm", - "VXORPSrm", - "XORPDrm", - "XORPSrm")>; + "(V?)PINSRBrm", + "(V?)PINSRDrm", + "(V?)PINSRQrm", + "(V?)PINSRWrm", + "(V?)PMOVSXBDrm", + "(V?)PMOVSXBQrm", + "(V?)PMOVSXBWrm", + "(V?)PMOVSXDQrm", + "(V?)PMOVSXWDrm", + "(V?)PMOVSXWQrm", + "(V?)PMOVZXBDrm", + "(V?)PMOVZXBQrm", + "(V?)PMOVZXBWrm", + "(V?)PMOVZXDQrm", + "(V?)PMOVZXWDrm", + "(V?)PMOVZXWQrm", + "(V?)PSHUFBrm", + "(V?)PSHUFDmi", + "(V?)PSHUFHWmi", + "(V?)PSHUFLWmi", + "(V?)PUNPCKHBWrm", + "(V?)PUNPCKHDQrm", + "(V?)PUNPCKHQDQrm", + "(V?)PUNPCKHWDrm", + "(V?)PUNPCKLBWrm", + "(V?)PUNPCKLDQrm", + "(V?)PUNPCKLQDQrm", + "(V?)PUNPCKLWDrm", + "(V?)SHUFPDrmi", + "(V?)SHUFPSrmi", + "(V?)UNPCKHPDrm", + "(V?)UNPCKHPSrm", + "(V?)UNPCKLPDrm", + "(V?)UNPCKLPSrm", + "(V?)XORPDrm", + "(V?)XORPSrm")>; def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> { let Latency = 6; @@ -1975,117 +1480,68 @@ def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm", "MMX_PSUBUSWirm", "MMX_PSUBWirm", "MOVBE(16|32|64)rm", - "PABSBrm", - "PABSDrm", - "PABSWrm", - "PADDBrm", - "PADDDrm", - "PADDQrm", - "PADDSBrm", - "PADDSWrm", - "PADDUSBrm", - "PADDUSWrm", - "PADDWrm", - "PAVGBrm", - "PAVGWrm", - "PCMPEQBrm", - "PCMPEQDrm", - "PCMPEQQrm", - "PCMPEQWrm", - "PCMPGTBrm", - "PCMPGTDrm", - "PCMPGTWrm", - "PMAXSBrm", - "PMAXSDrm", - "PMAXSWrm", - "PMAXUBrm", - "PMAXUDrm", - "PMAXUWrm", - "PMINSBrm", - "PMINSDrm", - "PMINSWrm", - "PMINUBrm", - "PMINUDrm", - "PMINUWrm", - "PSIGNBrm", - "PSIGNDrm", - "PSIGNWrm", - "PSUBBrm", - "PSUBDrm", - "PSUBQrm", - "PSUBSBrm", - "PSUBSWrm", - "PSUBUSBrm", - "PSUBUSWrm", - "PSUBWrm", - "VPABSBrm", - "VPABSDrm", - "VPABSWrm", - "VPADDBrm", - "VPADDDrm", - "VPADDQrm", - "VPADDSBrm", - "VPADDSWrm", - "VPADDUSBrm", - "VPADDUSWrm", - "VPADDWrm", - "VPAVGBrm", - "VPAVGWrm", - "VPCMPEQBrm", - "VPCMPEQDrm", - "VPCMPEQQrm", - "VPCMPEQWrm", - "VPCMPGTBrm", - "VPCMPGTDrm", - "VPCMPGTWrm", - "VPMAXSBrm", - "VPMAXSDrm", - "VPMAXSWrm", - "VPMAXUBrm", - "VPMAXUDrm", - "VPMAXUWrm", - "VPMINSBrm", - "VPMINSDrm", - "VPMINSWrm", - "VPMINUBrm", - "VPMINUDrm", - "VPMINUWrm", - "VPSIGNBrm", - "VPSIGNDrm", - "VPSIGNWrm", - "VPSUBBrm", - "VPSUBDrm", - "VPSUBQrm", - "VPSUBSBrm", - "VPSUBSWrm", - "VPSUBUSBrm", - "VPSUBUSWrm", - "VPSUBWrm")>; + "(V?)PABSBrm", + "(V?)PABSDrm", + "(V?)PABSWrm", + "(V?)PADDBrm", + "(V?)PADDDrm", + "(V?)PADDQrm", + "(V?)PADDSBrm", + "(V?)PADDSWrm", + "(V?)PADDUSBrm", + "(V?)PADDUSWrm", + "(V?)PADDWrm", + "(V?)PAVGBrm", + "(V?)PAVGWrm", + "(V?)PCMPEQBrm", + "(V?)PCMPEQDrm", + "(V?)PCMPEQQrm", + "(V?)PCMPEQWrm", + "(V?)PCMPGTBrm", + "(V?)PCMPGTDrm", + "(V?)PCMPGTWrm", + "(V?)PMAXSBrm", + "(V?)PMAXSDrm", + "(V?)PMAXSWrm", + "(V?)PMAXUBrm", + "(V?)PMAXUDrm", + "(V?)PMAXUWrm", + "(V?)PMINSBrm", + "(V?)PMINSDrm", + "(V?)PMINSWrm", + "(V?)PMINUBrm", + "(V?)PMINUDrm", + "(V?)PMINUWrm", + "(V?)PSIGNBrm", + "(V?)PSIGNDrm", + "(V?)PSIGNWrm", + "(V?)PSUBBrm", + "(V?)PSUBDrm", + "(V?)PSUBQrm", + "(V?)PSUBSBrm", + "(V?)PSUBSWrm", + "(V?)PSUBUSBrm", + "(V?)PSUBUSWrm", + "(V?)PSUBWrm")>; def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> { let Latency = 6; let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[BWWriteResGroup65], (instregex "BLENDPDrmi", - "BLENDPSrmi", - "MMX_PANDNirm", +def: InstRW<[BWWriteResGroup65], (instregex "MMX_PANDNirm", "MMX_PANDirm", "MMX_PORirm", "MMX_PXORirm", - "PANDNrm", - "PANDrm", - "PORrm", - "PXORrm", - "VBLENDPDrmi", - "VBLENDPSrmi", + "(V?)BLENDPDrmi", + "(V?)BLENDPSrmi", "VINSERTF128rm", "VINSERTI128rm", - "VPANDNrm", - "VPANDrm", + "(V?)PANDNrm", + "(V?)PANDrm", "VPBLENDDrmi", - "VPORrm", - "VPXORrm")>; + "(V?)PORrm", + "(V?)PXORrm")>; def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> { let Latency = 6; @@ -2301,9 +1757,7 @@ def BWWriteResGroup78 : SchedWriteRes<[BWPort0,BWPort5]> { let NumMicroOps = 3; let ResourceCycles = [1,2]; } -def: InstRW<[BWWriteResGroup78], (instregex "MPSADBWrri", - "VMPSADBWYrri", - "VMPSADBWrri")>; +def: InstRW<[BWWriteResGroup78], (instregex "(V?)MPSADBW(Y?)rri")>; def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> { let Latency = 7; @@ -2434,79 +1888,50 @@ def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> { } def: InstRW<[BWWriteResGroup91], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi8, IMUL64rmi32)>; def: InstRW<[BWWriteResGroup91], (instrs IMUL8m, MUL8m)>; -def: InstRW<[BWWriteResGroup91], (instregex "ADDPDrm", - "ADDPSrm", - "ADDSDrm", - "ADDSSrm", - "ADDSUBPDrm", - "ADDSUBPSrm", - "BSF(16|32|64)rm", +def: InstRW<[BWWriteResGroup91], (instregex "BSF(16|32|64)rm", "BSR(16|32|64)rm", - "CMPPDrmi", - "CMPPSrmi", - "CMPSDrm", - "CMPSSrm", - "COMISDrm", - "COMISSrm", - "CVTDQ2PSrm", - "CVTPS2DQrm", - "CVTTPS2DQrm", "LZCNT(16|32|64)rm", - "MAX(C?)PDrm", - "MAX(C?)PSrm", - "MAX(C?)SDrm", - "MAX(C?)SSrm", - "MIN(C?)PDrm", - "MIN(C?)PSrm", - "MIN(C?)SDrm", - "MIN(C?)SSrm", "MMX_CVTPI2PSirm", "MMX_CVTPS2PIirm", "MMX_CVTTPS2PIirm", "PDEP(32|64)rm", "PEXT(32|64)rm", "POPCNT(16|32|64)rm", - "SUBPDrm", - "SUBPSrm", - "SUBSDrm", - "SUBSSrm", "TZCNT(16|32|64)rm", - "UCOMISDrm", - "UCOMISSrm", - "VADDPDrm", - "VADDPSrm", - "VADDSDrm", - "VADDSSrm", - "VADDSUBPDrm", - "VADDSUBPSrm", - "VCMPPDrmi", - "VCMPPSrmi", - "VCMPSDrm", - "VCMPSSrm", - "VCOMISDrm", - "VCOMISSrm", - "VCVTDQ2PSrm", - "VCVTPS2DQrm", - "VCVTTPS2DQrm", - "VMAX(C?)PDrm", - "VMAX(C?)PSrm", - "VMAX(C?)SDrm", - "VMAX(C?)SSrm", - "VMIN(C?)PDrm", - "VMIN(C?)PSrm", - "VMIN(C?)SDrm", - "VMIN(C?)SSrm", - "VSUBPDrm", - "VSUBPSrm", - "VSUBSDrm", - "VSUBSSrm", - "VUCOMISDrm", - "VUCOMISSrm")>; + "(V?)ADDPDrm", + "(V?)ADDPSrm", + "(V?)ADDSDrm", + "(V?)ADDSSrm", + "(V?)ADDSUBPDrm", + "(V?)ADDSUBPSrm", + "(V?)CMPPDrmi", + "(V?)CMPPSrmi", + "(V?)CMPSDrm", + "(V?)CMPSSrm", + "(V?)COMISDrm", + "(V?)COMISSrm", + "(V?)CVTDQ2PSrm", + "(V?)CVTPS2DQrm", + "(V?)CVTTPS2DQrm", + "(V?)MAX(C?)PDrm", + "(V?)MAX(C?)PSrm", + "(V?)MAX(C?)SDrm", + "(V?)MAX(C?)SSrm", + "(V?)MIN(C?)PDrm", + "(V?)MIN(C?)PSrm", + "(V?)MIN(C?)SDrm", + "(V?)MIN(C?)SSrm", + "(V?)SUBPDrm", + "(V?)SUBPSrm", + "(V?)SUBSDrm", + "(V?)SUBSSrm", + "(V?)UCOMISDrm", + "(V?)UCOMISSrm")>; def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> { let Latency = 8; let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; + let ResourceCycles = [1,1,1]; } def: InstRW<[BWWriteResGroup91_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>; @@ -2534,14 +1959,10 @@ def BWWriteResGroup93 : SchedWriteRes<[BWPort01,BWPort23]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[BWWriteResGroup93], (instregex "MULPDrm", - "MULPSrm", - "MULSDrm", - "MULSSrm", - "VMULPDrm", - "VMULPSrm", - "VMULSDrm", - "VMULSSrm")>; +def: InstRW<[BWWriteResGroup93], (instregex "(V?)MULPDrm", + "(V?)MULPSrm", + "(V?)MULSDrm", + "(V?)MULSSrm")>; def BWWriteResGroup94 : SchedWriteRes<[BWPort5,BWPort23]> { let Latency = 8; @@ -2576,18 +1997,12 @@ def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDDrm", "MMX_PHSUBDrm", "MMX_PHSUBSWrm", "MMX_PHSUBWrm", - "PHADDDrm", - "PHADDSWrm", - "PHADDWrm", - "PHSUBDrm", - "PHSUBSWrm", - "PHSUBWrm", - "VPHADDDrm", - "VPHADDSWrm", - "VPHADDWrm", - "VPHSUBDrm", - "VPHSUBSWrm", - "VPHSUBWrm")>; + "(V?)PHADDDrm", + "(V?)PHADDSWrm", + "(V?)PHADDWrm", + "(V?)PHSUBDrm", + "(V?)PHSUBSWrm", + "(V?)PHSUBWrm")>; def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> { let Latency = 8; @@ -2688,29 +2103,21 @@ def BWWriteResGroup104 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[BWWriteResGroup104], (instregex "DPPDrri", - "VDPPDrri")>; +def: InstRW<[BWWriteResGroup104], (instregex "(V?)DPPDrri")>; def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> { let Latency = 9; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[BWWriteResGroup105], (instregex "CVTSD2SI64rm", - "CVTSD2SIrm", - "CVTSS2SI64rm", - "CVTSS2SIrm", - "CVTTSD2SI64rm", - "CVTTSD2SIrm", - "CVTTSS2SIrm", - "VCVTSD2SI64rm", - "VCVTSD2SIrm", - "VCVTSS2SI64rm", - "VCVTSS2SIrm", - "VCVTTSD2SI64rm", - "VCVTTSD2SIrm", +def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSD2SI64rm", + "(V?)CVTSD2SIrm", + "(V?)CVTSS2SI64rm", + "(V?)CVTSS2SIrm", + "(V?)CVTTSD2SI64rm", + "(V?)CVTTSD2SIrm", "VCVTTSS2SI64rm", - "VCVTTSS2SIrm")>; + "(V?)CVTTSS2SIrm")>; def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> { let Latency = 9; @@ -2725,26 +2132,22 @@ def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> { let ResourceCycles = [1,1,1]; } def: InstRW<[BWWriteResGroup107], (instrs IMUL64m, MUL64m, MULX64rm)>; -def: InstRW<[BWWriteResGroup107], (instregex "CVTDQ2PDrm", - "CVTPD2DQrm", +def: InstRW<[BWWriteResGroup107], (instregex "CVTPD2DQrm", "CVTPD2PSrm", - "CVTSD2SSrm", "CVTTPD2DQrm", "MMX_CVTPD2PIirm", "MMX_CVTPI2PDirm", "MMX_CVTTPD2PIirm", - "VCVTDQ2PDrm", - "VCVTSD2SSrm")>; + "(V?)CVTDQ2PDrm", + "(V?)CVTSD2SSrm")>; def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> { let Latency = 9; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTBYrm", - "VPBROADCASTBrm", - "VPBROADCASTWYrm", - "VPBROADCASTWrm")>; +def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm", + "VPBROADCASTW(Y?)rm")>; def BWWriteResGroup109 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> { let Latency = 9; @@ -2795,9 +2198,7 @@ def BWWriteResGroup114 : SchedWriteRes<[BWPort0]> { let NumMicroOps = 2; let ResourceCycles = [2]; } -def: InstRW<[BWWriteResGroup114], (instregex "PMULLDrr", - "VPMULLDYrr", - "VPMULLDrr")>; +def: InstRW<[BWWriteResGroup114], (instregex "(V?)PMULLD(Y?)rr")>; def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> { let Latency = 10; @@ -2812,36 +2213,21 @@ def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDUBSWrm", "MMX_PMULLWirm", "MMX_PMULUDQirm", "MMX_PSADBWirm", - "PCMPGTQrm", - "PHMINPOSUWrm", - "PMADDUBSWrm", - "PMADDWDrm", - "PMULDQrm", - "PMULHRSWrm", - "PMULHUWrm", - "PMULHWrm", - "PMULLWrm", - "PMULUDQrm", - "PSADBWrm", - "RCPPSm", - "RCPSSm", - "RSQRTPSm", - "RSQRTSSm", - "VPCMPGTQrm", - "VPHMINPOSUWrm", - "VPMADDUBSWrm", - "VPMADDWDrm", - "VPMULDQrm", - "VPMULHRSWrm", - "VPMULHUWrm", - "VPMULHWrm", - "VPMULLWrm", - "VPMULUDQrm", - "VPSADBWrm", - "VRCPPSm", - "VRCPSSm", - "VRSQRTPSm", - "VRSQRTSSm")>; + "(V?)PCMPGTQrm", + "(V?)PHMINPOSUWrm", + "(V?)PMADDUBSWrm", + "(V?)PMADDWDrm", + "(V?)PMULDQrm", + "(V?)PMULHRSWrm", + "(V?)PMULHUWrm", + "(V?)PMULHWrm", + "(V?)PMULLWrm", + "(V?)PMULUDQrm", + "(V?)PSADBWrm", + "(V?)RCPPSm", + "(V?)RCPSSm", + "(V?)RSQRTPSm", + "(V?)RSQRTSSm")>; def BWWriteResGroup116 : SchedWriteRes<[BWPort01,BWPort23]> { let Latency = 10; @@ -2874,14 +2260,10 @@ def BWWriteResGroup119 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> { let NumMicroOps = 4; let ResourceCycles = [1,2,1]; } -def: InstRW<[BWWriteResGroup119], (instregex "HADDPDrm", - "HADDPSrm", - "HSUBPDrm", - "HSUBPSrm", - "VHADDPDrm", - "VHADDPSrm", - "VHSUBPDrm", - "VHSUBPSrm")>; +def: InstRW<[BWWriteResGroup119], (instregex "(V?)HADDPDrm", + "(V?)HADDPSrm", + "(V?)HSUBPDrm", + "(V?)HSUBPSrm")>; def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> { let Latency = 10; @@ -2902,10 +2284,8 @@ def BWWriteResGroup122 : SchedWriteRes<[BWPort0]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[BWWriteResGroup122], (instregex "DIVPSrr", - "DIVSSrr", - "VDIVPSrr", - "VDIVSSrr")>; +def: InstRW<[BWWriteResGroup122], (instregex "(V?)DIVPSrr", + "(V?)DIVSSrr")>; def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> { let Latency = 11; @@ -2946,14 +2326,10 @@ def BWWriteResGroup127 : SchedWriteRes<[BWPort1,BWPort23]> { let NumMicroOps = 3; let ResourceCycles = [2,1]; } -def: InstRW<[BWWriteResGroup127], (instregex "ROUNDPDm", - "ROUNDPSm", - "ROUNDSDm", - "ROUNDSSm", - "VROUNDPDm", - "VROUNDPSm", - "VROUNDSDm", - "VROUNDSSm")>; +def: InstRW<[BWWriteResGroup127], (instregex "(V?)ROUNDPDm", + "(V?)ROUNDPSm", + "(V?)ROUNDSDm", + "(V?)ROUNDSSm")>; def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> { let Latency = 11; @@ -3044,10 +2420,8 @@ def BWWriteResGroup139 : SchedWriteRes<[BWPort0]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[BWWriteResGroup139], (instregex "DIVPDrr", - "DIVSDrr", - "VDIVPDrr", - "VDIVSDrr", +def: InstRW<[BWWriteResGroup139], (instregex "(V?)DIVPDrr", + "(V?)DIVSDrr", "VSQRTPSr", "VSQRTSSr")>; @@ -3064,9 +2438,7 @@ def BWWriteResGroup142 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> { let NumMicroOps = 4; let ResourceCycles = [2,1,1]; } -def: InstRW<[BWWriteResGroup142], (instregex "DPPSrri", - "VDPPSYrri", - "VDPPSrri")>; +def: InstRW<[BWWriteResGroup142], (instregex "(V?)DPPS(Y?)rri")>; def BWWriteResGroup143 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> { let Latency = 14; @@ -3191,10 +2563,8 @@ def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[BWWriteResGroup161], (instregex "DIVPDrm", - "DIVSDrm", - "VDIVPDrm", - "VDIVSDrm", +def: InstRW<[BWWriteResGroup161], (instregex "(V?)DIVPDrm", + "(V?)DIVSDrm", "VSQRTPSm", "VSQRTSSm")>; @@ -3377,7 +2747,7 @@ def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>; def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> { let Latency = 26; let NumMicroOps = 14; - let ResourceCycles = [1,4,8,1]; + let ResourceCycles = [1,4,8,1]; } def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>; |