diff options
author | Diana Picus <diana.picus@linaro.org> | 2019-01-16 11:56:47 +0100 |
---|---|---|
committer | Diana Picus <diana.picus@linaro.org> | 2019-01-16 11:56:47 +0100 |
commit | 184150cc5fb59f124cf9dea215ee7750fc9aa6d6 (patch) | |
tree | ffc950d6603498befccee2916d8b9f6362b658e8 | |
parent | 77f2009352556e0e7840ccddf0e874aac590b123 (diff) |
Fix capitalization. NFClinaro-local/diana.picus/varargs
-rw-r--r-- | lib/Target/ARM/ARMCallLowering.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMCallLowering.cpp b/lib/Target/ARM/ARMCallLowering.cpp index a64544c20d1..aba0863e02b 100644 --- a/lib/Target/ARM/ARMCallLowering.cpp +++ b/lib/Target/ARM/ARMCallLowering.cpp @@ -540,19 +540,19 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, // Create the call instruction so we can add the implicit uses of arg // registers, but don't insert it yet. - bool isDirect = !Callee.isReg(); - auto CallOpcode = getCallOpcode(STI, isDirect); + bool IsDirect = !Callee.isReg(); + auto CallOpcode = getCallOpcode(STI, IsDirect); auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode); - bool isThumb = STI.isThumb(); - if (isThumb) + bool IsThumb = STI.isThumb(); + if (IsThumb) MIB.add(predOps(ARMCC::AL)); MIB.add(Callee); - if (!isDirect) { + if (!IsDirect) { auto CalleeReg = Callee.getReg(); if (CalleeReg && !TRI->isPhysicalRegister(CalleeReg)) { - unsigned CalleeIdx = isThumb ? 2 : 0; + unsigned CalleeIdx = IsThumb ? 2 : 0; MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass( MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(), *MIB.getInstr(), MIB->getDesc(), Callee, CalleeIdx)); |