diff options
author | Sam Parker <sam.parker@arm.com> | 2019-01-21 11:01:05 +0000 |
---|---|---|
committer | Sam Parker <sam.parker@arm.com> | 2019-01-21 11:01:05 +0000 |
commit | e33706e16e8f884773da963313d1cd6fc44c4b62 (patch) | |
tree | fc1b722a549ef0f3c278ca61db0f98871936e332 | |
parent | 19fdbae0bcc021ae9976d0b29e1fcbb193c2fe38 (diff) |
[AArch64] Use LL for 64-bit intrinsic arguments
The ACLE states that 64-bit crc32, wsr, rsr and rbit operands are
uint64_t so we should have the clang builtin match this description
- which is what we already do for AArch32.
Differential Revision: https://reviews.llvm.org/D56852
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@351740 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | include/clang/Basic/BuiltinsAArch64.def | 10 | ||||
-rw-r--r-- | test/CodeGen/arm64-crc32.c | 19 | ||||
-rw-r--r-- | test/CodeGen/builtins-arm64.c | 6 |
3 files changed, 20 insertions, 15 deletions
diff --git a/include/clang/Basic/BuiltinsAArch64.def b/include/clang/Basic/BuiltinsAArch64.def index ee1d973def..fb7b65aa4d 100644 --- a/include/clang/Basic/BuiltinsAArch64.def +++ b/include/clang/Basic/BuiltinsAArch64.def @@ -32,7 +32,7 @@ BUILTIN(__builtin_arm_clrex, "v", "") // Bit manipulation BUILTIN(__builtin_arm_rbit, "UiUi", "nc") -BUILTIN(__builtin_arm_rbit64, "LUiLUi", "nc") +BUILTIN(__builtin_arm_rbit64, "LLUiLLUi", "nc") // HINT BUILTIN(__builtin_arm_nop, "v", "") @@ -49,8 +49,8 @@ BUILTIN(__builtin_arm_crc32h, "UiUiUs", "nc") BUILTIN(__builtin_arm_crc32ch, "UiUiUs", "nc") BUILTIN(__builtin_arm_crc32w, "UiUiUi", "nc") BUILTIN(__builtin_arm_crc32cw, "UiUiUi", "nc") -BUILTIN(__builtin_arm_crc32d, "UiUiLUi", "nc") -BUILTIN(__builtin_arm_crc32cd, "UiUiLUi", "nc") +BUILTIN(__builtin_arm_crc32d, "UiUiLLUi", "nc") +BUILTIN(__builtin_arm_crc32cd, "UiUiLLUi", "nc") // Memory barrier BUILTIN(__builtin_arm_dmb, "vUi", "nc") @@ -62,10 +62,10 @@ BUILTIN(__builtin_arm_prefetch, "vvC*UiUiUiUi", "nc") // System Registers BUILTIN(__builtin_arm_rsr, "UicC*", "nc") -BUILTIN(__builtin_arm_rsr64, "LUicC*", "nc") +BUILTIN(__builtin_arm_rsr64, "LLUicC*", "nc") BUILTIN(__builtin_arm_rsrp, "v*cC*", "nc") BUILTIN(__builtin_arm_wsr, "vcC*Ui", "nc") -BUILTIN(__builtin_arm_wsr64, "vcC*LUi", "nc") +BUILTIN(__builtin_arm_wsr64, "vcC*LLUi", "nc") BUILTIN(__builtin_arm_wsrp, "vcC*vC*", "nc") // MSVC diff --git a/test/CodeGen/arm64-crc32.c b/test/CodeGen/arm64-crc32.c index 2d913fb123..26d69a23b6 100644 --- a/test/CodeGen/arm64-crc32.c +++ b/test/CodeGen/arm64-crc32.c @@ -1,54 +1,57 @@ // REQUIRES: aarch64-registered-target // RUN: %clang_cc1 -triple arm64-none-linux-gnu \ // RUN: -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-windows \ +// RUN: -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +#include <stdint.h> -int crc32b(int a, char b) +uint32_t crc32b(uint32_t a, uint8_t b) { return __builtin_arm_crc32b(a,b); // CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32 // CHECK: call i32 @llvm.aarch64.crc32b(i32 %a, i32 [[T0]]) } -int crc32cb(int a, char b) +uint32_t crc32cb(uint32_t a, uint8_t b) { return __builtin_arm_crc32cb(a,b); // CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32 // CHECK: call i32 @llvm.aarch64.crc32cb(i32 %a, i32 [[T0]]) } -int crc32h(int a, short b) +uint32_t crc32h(uint32_t a, uint16_t b) { return __builtin_arm_crc32h(a,b); // CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32 // CHECK: call i32 @llvm.aarch64.crc32h(i32 %a, i32 [[T0]]) } -int crc32ch(int a, short b) +uint32_t crc32ch(uint32_t a, uint16_t b) { return __builtin_arm_crc32ch(a,b); // CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32 // CHECK: call i32 @llvm.aarch64.crc32ch(i32 %a, i32 [[T0]]) } -int crc32w(int a, int b) +uint32_t crc32w(uint32_t a, uint32_t b) { return __builtin_arm_crc32w(a,b); // CHECK: call i32 @llvm.aarch64.crc32w(i32 %a, i32 %b) } -int crc32cw(int a, int b) +uint32_t crc32cw(uint32_t a, uint32_t b) { return __builtin_arm_crc32cw(a,b); // CHECK: call i32 @llvm.aarch64.crc32cw(i32 %a, i32 %b) } -int crc32d(int a, long b) +uint32_t crc32d(uint32_t a, uint64_t b) { return __builtin_arm_crc32d(a,b); // CHECK: call i32 @llvm.aarch64.crc32x(i32 %a, i64 %b) } -int crc32cd(int a, long b) +uint32_t crc32cd(uint32_t a, uint64_t b) { return __builtin_arm_crc32cd(a,b); // CHECK: call i32 @llvm.aarch64.crc32cx(i32 %a, i64 %b) diff --git a/test/CodeGen/builtins-arm64.c b/test/CodeGen/builtins-arm64.c index 7027a6e220..63673cc386 100644 --- a/test/CodeGen/builtins-arm64.c +++ b/test/CodeGen/builtins-arm64.c @@ -1,4 +1,6 @@ // RUN: %clang_cc1 -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-windows -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +#include <stdint.h> void f0(void *a, void *b) { __clear_cache(a,b); @@ -55,7 +57,7 @@ unsigned rsr() { return __builtin_arm_rsr("1:2:3:4:5"); } -unsigned long rsr64() { +uint64_t rsr64() { // CHECK: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) return __builtin_arm_rsr64("1:2:3:4:5"); } @@ -72,7 +74,7 @@ void wsr(unsigned v) { __builtin_arm_wsr("1:2:3:4:5", v); } -void wsr64(unsigned long v) { +void wsr64(uint64_t v) { // CHECK: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %v) __builtin_arm_wsr64("1:2:3:4:5", v); } |