Re-generate docs/ClangCommandLineReference.rst

$ bin/clang-tblgen -gen-opt-docs -I../cfe.src/include
    -I../cfe.src/include/clang/Driver -I../llvm.src/include
    ../cfe.src/include/clang/Driver/ClangOptionDocs.td -o
    ../cfe.src/docs/ClangCommandLineReference.rst


git-svn-id: https://llvm.org/svn/llvm-project/cfe/branches/release_80@353395 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 131 insertions, 61 deletions

diff --git a/docs/ClangCommandLineReference.rst b/docs/ClangCommandLineReference.rst
index e852c3e387..3dafac54a0 100644
--- a/docs/ClangCommandLineReference.rst
+++ b/docs/ClangCommandLineReference.rst
@@ -198,6 +198,10 @@ Filename (or -) to write dependency output to
 
 Emit Clang AST files for source inputs
 
+.. option:: -enable-trivial-auto-var-init-zero-knowing-it-will-be-removed-from-clang<arg>
+
+Trivial automatic variable initialization to zero is only here for benchmarks, it'll eventually be removed, and I'm OK with that because I'm only using it to benchmark
+
 .. option:: -exported\_symbols\_list <arg>
 
 .. option:: -faligned-new=<arg>
@@ -210,10 +214,6 @@ Use approximate transcendental functions
 
 Flush denormal floating point values to zero in CUDA device mode.
 
-.. option:: -fcuda-rdc, -fno-cuda-rdc
-
-Generate relocatable device code, also known as separate compilation mode.
-
 .. option:: -fcuda-short-ptr, -fno-cuda-short-ptr
 
 Use 32-bit pointers for accessing const/local/shared address spaces.
@@ -222,6 +222,10 @@ Use 32-bit pointers for accessing const/local/shared address spaces.
 
 Reserve register r19 (Hexagon only)
 
+.. option:: -fgpu-rdc, -fcuda-rdc, -fno-gpu-rdc
+
+Generate relocatable device code, also known as separate compilation mode.
+
 .. option:: -fheinous-gnu-extensions
 
 .. option:: -flat\_namespace
@@ -254,6 +258,10 @@ Use the gcc toolchain at the given directory
 
 Generate CodeView debug information
 
+.. option:: -gcodeview-ghash, -gno-codeview-ghash
+
+Emit type record hashes in a .debug$H section
+
 .. option:: -headerpad\_max\_install\_names<arg>
 
 .. option:: -help, --help
@@ -288,6 +296,10 @@ Make the next included directory (-I or -F) an indexer header map
 
 .. option:: -mbig-endian, -EB
 
+.. option:: -mbranch-protection=<arg>
+
+Enforce targets of indirect branches and function returns
+
 .. option:: --migrate
 
 Run the migrator
@@ -792,15 +804,7 @@ Don't use blacklist file for sanitizers
 
 .. option:: -fparse-all-comments
 
-.. option:: -frecord-command-line, -frecord-gcc-switches, -fno-record-command-line, -fno-record-gcc-switches
-
-Generate a section named ".GCC.command.line" containing the clang driver
-command-line. After linking, the section may contain multiple command lines,
-which will be individually terminated by null bytes. Separate arguments within
-a command line are combined with spaces; spaces and backslashes within an
-argument are escaped with backslashes. This format differs from the format of
-the equivalent section produced by GCC with the -frecord-gcc-switches flag.
-This option is currently only supported on ELF targets.
+.. option:: -frecord-command-line, -fno-record-command-line, -frecord-gcc-switches
 
 .. option:: -fsanitize-address-field-padding=<arg>
 
@@ -810,20 +814,18 @@ Level of field padding for AddressSanitizer
 
 Enable linker dead stripping of globals in AddressSanitizer
 
-.. option:: -fsanitize-address-use-odr-indicator, -fno-sanitize-address-use-odr-indicator
-
-Enable ODR indicator globals to avoid false ODR violation reports in partially sanitized programs at the cost of an increase in binary size
-
 .. option:: -fsanitize-address-poison-custom-array-cookie, -fno-sanitize-address-poison-custom-array-cookie
 
-Enable "poisoning" array cookies when allocating arrays with a custom operator new\[\] in Address Sanitizer, preventing accesses to the cookies from user code. An array cookie is a small implementation-defined header added to certain array allocations to record metadata such as the length of the array. Accesses to array cookies from user code are technically allowed by the standard but are more likely to be the result of an out-of-bounds array access.
-
-An operator new\[\] is "custom" if it is not one of the allocation functions provided by the C++ standard library. Array cookies from non-custom allocation functions are always poisoned.
+Enable poisoning array cookies when using custom operator new\[\] in AddressSanitizer
 
 .. option:: -fsanitize-address-use-after-scope, -fno-sanitize-address-use-after-scope
 
 Enable use-after-scope detection in AddressSanitizer
 
+.. option:: -fsanitize-address-use-odr-indicator, -fno-sanitize-address-use-odr-indicator
+
+Enable ODR indicator globals to avoid false ODR violation reports in partially sanitized programs at the cost of an increase in binary size
+
 .. option:: -fsanitize-blacklist=<arg>
 
 Path to blacklist file for sanitizers
@@ -840,6 +842,10 @@ Generalize pointers in CFI indirect call type signature checks
 
 Specify the type of coverage instrumentation for Sanitizers
 
+.. option:: -fsanitize-hwaddress-abi=<arg>
+
+Select the HWAddressSanitizer ABI to target (interceptor or platform, default interceptor)
+
 .. option:: -fsanitize-link-c++-runtime
 
 .. option:: -fsanitize-memory-track-origins, -fno-sanitize-memory-track-origins
@@ -1072,6 +1078,10 @@ Set directory to include search path with prefix
 
 Add directory to SYSTEM include search path, absolute paths are relative to -isysroot
 
+.. option:: --libomptarget-nvptx-path=<arg>
+
+Path to libomptarget-nvptx libraries
+
 .. option:: --ptxas-path=<arg>
 
 Path to ptxas (used for compiling CUDA code)
@@ -1283,6 +1293,8 @@ Enable C++ static destructor registration (the default)
 
 Instrument control-flow architecture protection. Options: return, branch, full, none.
 
+.. option:: -fcf-runtime-abi=<arg>
+
 .. option:: -fchar8\_t, -fno-char8\_t
 
 Enable C++ builtin type char8\_t
@@ -1343,6 +1355,10 @@ Emit macro debug information
 
 remap file source paths in debug info
 
+.. option:: -fdebug-ranges-base-address, -fno-debug-ranges-base-address
+
+Use DWARF base address selection entries in debug\_ranges
+
 .. option:: -fdebug-types-section, -fno-debug-types-section
 
 Place debug types in their own section (ELF Only)
@@ -1651,6 +1667,8 @@ Synthesize retain and release calls for Objective-C pointers
 
 Use EH-safe code when synthesizing retains and releases in -fobjc-arc
 
+.. option:: -fobjc-convert-messages-to-runtime-calls, -fno-objc-convert-messages-to-runtime-calls
+
 .. option:: -fobjc-exceptions, -fno-objc-exceptions
 
 Enable Objective-C exceptions
@@ -1737,6 +1755,14 @@ Load the named plugin (dynamic shared object)
 
 .. option:: -fprofile-dir=<arg>
 
+.. option:: -fprofile-exclude-files=<arg>
+
+Instrument only functions from files where names don't match all the regexes separated by a semi-colon
+
+.. option:: -fprofile-filter-files=<arg>
+
+Instrument only functions from files where names match any regex separated by a semi-colon
+
 .. option:: -fprofile-generate, -fno-profile-generate
 
 Generate instrumented code to collect execution counts into default.profraw (overridden by LLVM\_PROFILE\_FILE env var)
@@ -1765,6 +1791,10 @@ Generate instrumented code to collect execution counts into <file> (overridden b
 
 Use instrumentation data for profile-guided optimization
 
+.. option:: -fprofile-remapping-file=<file>, -fprofile-remapping-file <arg>
+
+Use the remappings described in <file> to match the profile data against names in the program
+
 .. option:: -fprofile-sample-accurate, -fauto-profile-accurate, -fno-profile-sample-accurate
 
 Specifies that the sample profile is accurate. If the sample
@@ -1876,19 +1906,23 @@ Enable the superword-level parallelism vectorization passes
 
 Provide minimal debug info in the object/executable to facilitate online symbolication/stack traces in the absence of .dwo/.dwp files when using Split DWARF
 
+.. option:: -fsplit-lto-unit, -fno-split-lto-unit
+
+Enables splitting of the LTO unit.
+
 .. option:: -fsplit-stack
 
 .. option:: -fstack-protector, -fno-stack-protector
 
-Enable stack protectors for functions potentially vulnerable to stack smashing
+Enable stack protectors for some functions vulnerable to stack smashing. This uses a loose heuristic which considers functions vulnerable if they contain a char (or 8bit integer) array or constant sized calls to alloca, which are of greater size than ssp-buffer-size (default: 8 bytes). All variable sized calls to alloca are considered vulnerable
 
 .. option:: -fstack-protector-all
 
-Force the usage of stack protectors for all functions
+Enable stack protectors for all functions
 
 .. option:: -fstack-protector-strong
 
-Use a strong heuristic to apply stack protectors to functions
+Enable stack protectors for some functions vulnerable to stack smashing. Compared to -fstack-protector, this uses a stronger heuristic that includes functions containing arrays of any size (and any type), as well as any calls to alloca or the taking of an address from a local variable
 
 .. option:: -fstack-size-section, -fno-stack-size-section
 
@@ -1962,6 +1996,10 @@ Specify the function to be called on overflow
 
 Process trigraph sequences
 
+.. option:: -ftrivial-auto-var-init=<arg>
+
+Initialize trivial automatic stack variables: uninitialized (default) \| pattern
+
 .. option:: -funique-section-names, -fno-unique-section-names
 
 Use unique names for text and data sections (ELF Only)
@@ -2000,6 +2038,10 @@ Enable the loop vectorization passes
 
 .. option:: -fverbose-asm, -fno-verbose-asm
 
+.. option:: -fvisibility-global-new-delete-hidden
+
+Give global C++ operator new and delete declarations hidden visibility
+
 .. option:: -fvisibility-inlines-hidden
 
 Give inline C++ member functions hidden visibility by default
@@ -2162,7 +2204,7 @@ Link stack frames through backchain on System Z
 
 .. option:: -mconsole<arg>
 
-.. option:: -mcpu=<arg>, -mv5 (equivalent to -mcpu=hexagonv5), -mv55 (equivalent to -mcpu=hexagonv55), -mv60 (equivalent to -mcpu=hexagonv60), -mv62 (equivalent to -mcpu=hexagonv62), -mv65 (equivalent to -mcpu=hexagonv65)
+.. option:: -mcpu=<arg>, -mv5 (equivalent to -mcpu=hexagonv5), -mv55 (equivalent to -mcpu=hexagonv55), -mv60 (equivalent to -mcpu=hexagonv60), -mv62 (equivalent to -mcpu=hexagonv62), -mv65 (equivalent to -mcpu=hexagonv65), -mv66 (equivalent to -mcpu=hexagonv66)
 
 .. option:: -mcrc, -mno-crc
 
@@ -2196,6 +2238,8 @@ Enable merging of globals
 
 .. option:: -mhwdiv=<arg>, --mhwdiv <arg>, --mhwdiv=<arg>
 
+.. option:: -mhwmult=<arg>
+
 .. option:: -miamcu, -mno-iamcu
 
 Use Intel MCU ABI
@@ -2272,6 +2316,8 @@ Select return address signing scope
 
 Use software floating point
 
+.. option:: -mspeculative-load-hardening, -mno-speculative-load-hardening
+
 .. option:: -mstack-alignment=<arg>
 
 Set the stack alignment
@@ -2296,6 +2342,10 @@ The thread model to use, e.g. posix, single (posix by default)
 
 .. option:: -mthumb, -mno-thumb
 
+.. option:: -mtls-direct-seg-refs, -mno-tls-direct-seg-refs
+
+Enable direct TLS access through segment registers (default)
+
 .. option:: -mtune=<arg>
 
 .. option:: -mtvos-version-min=<arg>, -mappletvos-version-min=<arg>
@@ -2314,41 +2364,33 @@ The thread model to use, e.g. posix, single (posix by default)
 
 AARCH64
 -------
-.. option:: -ffixed-x1
-
-Reserve the x1 register (AArch64 only)
-
-.. option:: -ffixed-x2
-
-Reserve the x2 register (AArch64 only)
-
-.. option:: -ffixed-x3
+.. option:: -fcall-saved-x10
 
-Reserve the x3 register (AArch64 only)
+Make the x10 register call-saved (AArch64 only)
 
-.. option:: -ffixed-x4
+.. option:: -fcall-saved-x11
 
-Reserve the x4 register (AArch64 only)
+Make the x11 register call-saved (AArch64 only)
 
-.. option:: -ffixed-x5
+.. option:: -fcall-saved-x12
 
-Reserve the x5 register (AArch64 only)
+Make the x12 register call-saved (AArch64 only)
 
-.. option:: -ffixed-x6
+.. option:: -fcall-saved-x13
 
-Reserve the x6 register (AArch64 only)
+Make the x13 register call-saved (AArch64 only)
 
-.. option:: -ffixed-x7
+.. option:: -fcall-saved-x14
 
-Reserve the x7 register (AArch64 only)
+Make the x14 register call-saved (AArch64 only)
 
-.. option:: -ffixed-x18
+.. option:: -fcall-saved-x15
 
-Reserve the x18 register (AArch64 only)
+Make the x15 register call-saved (AArch64 only)
 
-.. option:: -ffixed-x20
+.. option:: -fcall-saved-x18
 
-Reserve the x20 register (AArch64 only)
+Make the x18 register call-saved (AArch64 only)
 
 .. option:: -fcall-saved-x8
 
@@ -2358,33 +2400,41 @@ Make the x8 register call-saved (AArch64 only)
 
 Make the x9 register call-saved (AArch64 only)
 
-.. option:: -fcall-saved-x10
+.. option:: -ffixed-x1
 
-Make the x10 register call-saved (AArch64 only)
+Reserve the 1 register (AArch64 only)
 
-.. option:: -fcall-saved-x11
+.. option:: -ffixed-x18
 
-Make the x11 register call-saved (AArch64 only)
+Reserve the 18 register (AArch64 only)
 
-.. option:: -fcall-saved-x12
+.. option:: -ffixed-x2
 
-Make the x12 register call-saved (AArch64 only)
+Reserve the 2 register (AArch64 only)
 
-.. option:: -fcall-saved-x13
+.. option:: -ffixed-x20
 
-Make the x13 register call-saved (AArch64 only)
+Reserve the 20 register (AArch64 only)
 
-.. option:: -fcall-saved-x14
+.. option:: -ffixed-x3
 
-Make the x14 register call-saved (AArch64 only)
+Reserve the 3 register (AArch64 only)
 
-.. option:: -fcall-saved-x15
+.. option:: -ffixed-x4
 
-Make the x15 register call-saved (AArch64 only)
+Reserve the 4 register (AArch64 only)
 
-.. option:: -fcall-saved-x18
+.. option:: -ffixed-x5
 
-Make the x18 register call-saved (AArch64 only)
+Reserve the 5 register (AArch64 only)
+
+.. option:: -ffixed-x6
+
+Reserve the 6 register (AArch64 only)
+
+.. option:: -ffixed-x7
+
+Reserve the 7 register (AArch64 only)
 
 .. option:: -mfix-cortex-a53-835769, -mno-fix-cortex-a53-835769
 
@@ -2396,6 +2446,14 @@ Generate code which only uses the general purpose registers (AArch64 only)
 
 AMDGPU
 ------
+.. option:: -mcode-object-v3, -mno-code-object-v3
+
+Enable code object v3 (AMDGPU only)
+
+.. option:: -msram-ecc, -mno-sram-ecc
+
+Enable SRAM ECC (AMDGPU only)
+
 .. option:: -mxnack, -mno-xnack
 
 Enable XNACK (AMDGPU only)
@@ -2594,6 +2652,8 @@ WebAssembly
 
 .. option:: -msimd128, -mno-simd128
 
+.. option:: -munimplemented-simd128, -mno-unimplemented-simd128
+
 X86
 ---
 .. option:: -m3dnow, -mno-3dnow
@@ -2811,6 +2871,10 @@ ___________
 
 .. option:: -ggdb3
 
+.. option:: -gline-directives-only
+
+Emit debug line info directives only
+
 .. option:: -gline-tables-only, -g1, -gmlt
 
 Emit debug line number tables only
@@ -2841,10 +2905,16 @@ Embed source text in DWARF debug sections
 
 .. option:: -gpubnames, -gno-pubnames
 
-.. option:: -grecord-command-line, -grecord-gcc-switches, -gno-record-command-line, -gno-record-gcc-switches
+.. option:: -grecord-command-line, -gno-record-command-line, -grecord-gcc-switches
 
 .. option:: -gsplit-dwarf
 
+.. program:: clang1
+.. option:: -gsplit-dwarf=<arg>
+.. program:: clang
+
+Set DWARF fission mode to either 'split' or 'single'
+
 .. option:: -gstrict-dwarf, -gno-strict-dwarf
 
 .. option:: -gz