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-rw-r--r--gcc/config/alpha/alpha.md130
1 files changed, 101 insertions, 29 deletions
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 4e213f812e9..97838a5083a 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -337,8 +337,8 @@
"! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
&& INTVAL (operands[2]) % 4 == 0"
[(set (match_dup 3) (match_dup 4))
- (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
- (match_dup 5))
+ (set (match_dup 0) (sign_extend:DI (plus:SI (ashift:SI (match_dup 3)
+ (match_dup 5))
(match_dup 1))))]
{
HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
@@ -348,7 +348,7 @@
val /= 2, mult = 8;
operands[4] = GEN_INT (val);
- operands[5] = GEN_INT (mult);
+ operands[5] = GEN_INT (exact_log2 (mult));
})
(define_split
@@ -519,38 +519,71 @@
(define_insn "*sadd<modesuffix>"
[(set (match_operand:I48MODE 0 "register_operand" "=r,r")
(plus:I48MODE
- (mult:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r,r")
- (match_operand:I48MODE 2 "const48_operand" "I,I"))
+ (ashift:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r,r")
+ (match_operand:I48MODE 2 "const23_operand" "I,I"))
(match_operand:I48MODE 3 "sext_add_operand" "rI,O")))]
""
"@
- s%2add<modesuffix> %1,%3,%0
- s%2sub<modesuffix> %1,%n3,%0")
+ s%P2add<modesuffix> %1,%3,%0
+ s%P2sub<modesuffix> %1,%n3,%0")
+
+(define_insn_and_split "*saddsi_1"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (plus:SI
+ (subreg:SI
+ (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
+ (match_operand:DI 2 "const23_operand" "I,I")) 0)
+ (match_operand:SI 3 "sext_add_operand" "rI,O")))]
+ ""
+ "#"
+ ""
+ [(set (match_dup 0)
+ (plus:SI (ashift:SI (match_dup 1) (match_dup 2))
+ (match_dup 3)))]
+ "operands[1] = gen_lowpart (SImode, operands[1]);")
(define_insn "*saddl_se"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(sign_extend:DI
- (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
- (match_operand:SI 2 "const48_operand" "I,I"))
- (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
+ (plus:SI
+ (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
+ (match_operand:SI 2 "const23_operand" "I,I"))
+ (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
""
"@
- s%2addl %1,%3,%0
- s%2subl %1,%n3,%0")
+ s%P2addl %1,%3,%0
+ s%P2subl %1,%n3,%0")
+
+(define_insn_and_split "*saddl_se_1"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (sign_extend:DI
+ (plus:SI
+ (subreg:SI
+ (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
+ (match_operand:DI 2 "const23_operand" "I,I")) 0)
+ (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
+ ""
+ "#"
+ ""
+ [(set (match_dup 0)
+ (sign_extend:DI
+ (plus:SI (ashift:SI (match_dup 1) (match_dup 2))
+ (match_dup 3))))]
+ "operands[1] = gen_lowpart (SImode, operands[1]);")
(define_split
[(set (match_operand:DI 0 "register_operand")
(sign_extend:DI
- (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
+ (plus:SI (ashift:SI (match_operator:SI 1 "comparison_operator"
[(match_operand 2)
(match_operand 3)])
- (match_operand:SI 4 "const48_operand"))
+ (match_operand:SI 4 "const23_operand"))
(match_operand:SI 5 "sext_add_operand"))))
(clobber (match_operand:DI 6 "reg_not_elim_operand"))]
""
[(set (match_dup 6) (match_dup 7))
(set (match_dup 0)
- (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
+ (sign_extend:DI (plus:SI (ashift:SI (match_dup 8) (match_dup 4))
(match_dup 5))))]
{
operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
@@ -621,20 +654,53 @@
(define_insn "*ssub<modesuffix>"
[(set (match_operand:I48MODE 0 "register_operand" "=r")
(minus:I48MODE
- (mult:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r")
- (match_operand:I48MODE 2 "const48_operand" "I"))
+ (ashift:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r")
+ (match_operand:I48MODE 2 "const23_operand" "I"))
(match_operand:I48MODE 3 "reg_or_8bit_operand" "rI")))]
""
- "s%2sub<modesuffix> %1,%3,%0")
+ "s%P2sub<modesuffix> %1,%3,%0")
+
+(define_insn_and_split "*ssubsi_1"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (minus:SI
+ (subreg:SI
+ (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
+ (match_operand:DI 2 "const23_operand" "I")) 0)
+ (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
+ ""
+ "#"
+ ""
+ [(set (match_dup 0)
+ (minus:SI (ashift:SI (match_dup 1) (match_dup 2))
+ (match_dup 3)))]
+ "operands[1] = gen_lowpart (SImode, operands[1]);")
(define_insn "*ssubl_se"
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI
- (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
- (match_operand:SI 2 "const48_operand" "I"))
- (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
+ (minus:SI
+ (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
+ (match_operand:SI 2 "const23_operand" "I"))
+ (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
+ ""
+ "s%P2subl %1,%3,%0")
+
+(define_insn_and_split "*ssubl_se_1"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (sign_extend:DI
+ (minus:SI
+ (subreg:SI
+ (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
+ (match_operand:DI 2 "const23_operand" "I")) 0)
+ (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
""
- "s%2subl %1,%3,%0")
+ "#"
+ ""
+ [(set (match_dup 0)
+ (sign_extend:DI
+ (minus:SI (ashift:SI (match_dup 1) (match_dup 2))
+ (match_dup 3))))]
+ "operands[1] = gen_lowpart (SImode, operands[1]);")
(define_insn "subv<mode>3"
[(set (match_operand:I48MODE 0 "register_operand" "=r")
@@ -1200,7 +1266,7 @@
(subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
(match_operand:DI 2 "const_int_operand" "P"))
0)))]
- "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
+ "IN_RANGE (INTVAL (operands[2]), 1, 3)"
{
if (operands[2] == const1_rtx)
return "addl %r1,%r1,%0";
@@ -3139,9 +3205,10 @@
[(set (match_dup 5)
(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
(set (match_dup 0)
- (plus:DI (mult:DI (match_dup 5) (match_dup 3))
+ (plus:DI (ashift:DI (match_dup 5) (match_dup 3))
(match_dup 4)))]
{
+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
if (can_create_pseudo_p ())
operands[5] = gen_reg_rtx (DImode);
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
@@ -3164,9 +3231,10 @@
[(set (match_dup 5)
(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
(set (match_dup 0)
- (plus:SI (mult:SI (match_dup 6) (match_dup 3))
+ (plus:SI (ashift:SI (match_dup 6) (match_dup 3))
(match_dup 4)))]
{
+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
if (can_create_pseudo_p ())
operands[5] = gen_reg_rtx (DImode);
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
@@ -3192,9 +3260,10 @@
[(set (match_dup 5)
(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
(set (match_dup 0)
- (sign_extend:DI (plus:SI (mult:SI (match_dup 6) (match_dup 3))
+ (sign_extend:DI (plus:SI (ashift:SI (match_dup 6) (match_dup 3))
(match_dup 4))))]
{
+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
if (can_create_pseudo_p ())
operands[5] = gen_reg_rtx (DImode);
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
@@ -3219,9 +3288,10 @@
[(set (match_dup 5)
(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
(set (match_dup 0)
- (minus:DI (mult:DI (match_dup 5) (match_dup 3))
+ (minus:DI (ashift:DI (match_dup 5) (match_dup 3))
(match_dup 4)))]
{
+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
if (can_create_pseudo_p ())
operands[5] = gen_reg_rtx (DImode);
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
@@ -3244,9 +3314,10 @@
[(set (match_dup 5)
(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
(set (match_dup 0)
- (minus:SI (mult:SI (match_dup 6) (match_dup 3))
+ (minus:SI (ashift:SI (match_dup 6) (match_dup 3))
(match_dup 4)))]
{
+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
if (can_create_pseudo_p ())
operands[5] = gen_reg_rtx (DImode);
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
@@ -3272,9 +3343,10 @@
[(set (match_dup 5)
(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
(set (match_dup 0)
- (sign_extend:DI (minus:SI (mult:SI (match_dup 6) (match_dup 3))
+ (sign_extend:DI (minus:SI (ashift:SI (match_dup 6) (match_dup 3))
(match_dup 4))))]
{
+ operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3])));
if (can_create_pseudo_p ())
operands[5] = gen_reg_rtx (DImode);
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-23 23:15:31 +0000