diff options
| author | Yvan Roux <yvan.roux@linaro.org> | 2017-09-12 15:39:18 +0200 |
|---|---|---|
| committer | Yvan Roux <yvan.roux@linaro.org> | 2017-09-13 14:17:43 +0000 |
| commit | e91ce32c9641f2e3605f946d5d161af0de00da33 (patch) | |
| tree | 5f5b9410a945e06fd70edcb3c70b23e75bc867e2 | |
| parent | 3e9df2c0e1c9fb9883e91bd0b7c84c25fed0daa7 (diff) | |
gcc/
Backport from trunk r250631.
2017-07-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64.md
(define_split for and<mode>3nr_compare): Move
non aarch64_logical_operand to a register.
(define_split for and_<SHIFT:optab><mode>3nr_compare0): Move non
register immediate operand to a register.
* config/aarch64/predicates.md (aarch64_mov_imm_operand): New.
gcc/testsuite/
Backport from trunk r250631.
2017-07-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/tst_imm_split_1.c: New Test.
Change-Id: I73eb5a81dc9587fcaf9e909594f3a3754e6cd4a6
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 36 | ||||
| -rw-r--r-- | gcc/config/aarch64/predicates.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c | 18 |
3 files changed, 58 insertions, 0 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 6bdbf650d92..12f29ada904 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3824,6 +3824,22 @@ [(set_attr "type" "logics_reg,logics_imm")] ) +(define_split + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (and:GPI (match_operand:GPI 0 "register_operand") + (match_operand:GPI 1 "aarch64_mov_imm_operand")) + (const_int 0))) + (clobber (match_operand:SI 2 "register_operand"))] + "" + [(set (match_dup 2) (match_dup 1)) + (set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (and:GPI (match_dup 0) + (match_dup 2)) + (const_int 0)))] +) + (define_insn "*and<mode>3nr_compare0_zextract" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ @@ -3859,6 +3875,26 @@ [(set_attr "type" "logics_shift_imm")] ) +(define_split + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (and:GPI (SHIFT:GPI + (match_operand:GPI 0 "register_operand") + (match_operand:QI 1 "aarch64_shift_imm_<mode>")) + (match_operand:GPI 2 "aarch64_mov_imm_operand")) + (const_int 0))) + (clobber (match_operand:SI 3 "register_operand"))] + "" + [(set (match_dup 3) (match_dup 2)) + (set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (and:GPI (SHIFT:GPI + (match_dup 0) + (match_dup 1)) + (match_dup 3)) + (const_int 0)))] +) + ;; ------------------------------------------------------------------- ;; Shifts ;; ------------------------------------------------------------------- diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index cd7ded98663..4bd8f45562c 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -110,6 +110,10 @@ (ior (match_operand 0 "register_operand") (match_operand 0 "aarch64_logical_immediate"))) +(define_predicate "aarch64_mov_imm_operand" + (and (match_code "const_int") + (match_test "aarch64_move_imm (INTVAL (op), mode)"))) + (define_predicate "aarch64_logical_and_immediate" (and (match_code "const_int") (match_test "aarch64_and_bitmask_imm (INTVAL (op), mode)"))) diff --git a/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c b/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c new file mode 100644 index 00000000000..33a2c0f45af --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int +f (unsigned char *p) +{ + return p[0] == 50 || p[0] == 52; +} + +int +g (unsigned char *p) +{ + return (p[0] >> 4 & 0xfd) == 0; +} + +/* { dg-final { scan-assembler-not "and\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+.*" } } */ +/* { dg-final { scan-assembler "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+" } } */ +/* { dg-final { scan-assembler "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+, lsr 4" } } */ |