diff options
| author | Yvan Roux <yvan.roux@linaro.org> | 2017-03-03 15:32:58 +0100 |
|---|---|---|
| committer | Yvan Roux <yvan.roux@linaro.org> | 2017-03-14 09:08:11 +0000 |
| commit | b66b46e0487236d617d4cb7b0bb7decffe78ced6 (patch) | |
| tree | 71cd0a09aa34fd38e45db17a40b73dfc9d37a4e4 | |
| parent | 734c8955b843da4f7ae52997db34291f653b6381 (diff) | |
gcc/
Backport from trunk r243428.
2016-12-08 Naveen H.S <Naveen.Hurugalawadi@cavium.com>
* config/aarch64/aarch64.c (aarch64_load_symref_appropriately):
Handle SYMBOL_SMALL_TLSGD for ILP32.
* config/aarch64/aarch64.md : tlsgd_small modified into
tlsgd_small_<mode> to support SImode and DImode.
*tlsgd_small modified into *tlsgd_small_<mode> to support SImode and
DImode.
gcc/testsuite/
Backport from trunk r243428.
2016-12-08 Naveen H.S <Naveen.Hurugalawadi@cavium.com>
* gcc.target/aarch64/pr78382.c : New Testcase.
Change-Id: Ie0bf9fc133bc8f4e696622ffefb1fffb165b48e6
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 8 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 8 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/pr78382.c | 10 |
3 files changed, 20 insertions, 6 deletions
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 4dc905b9221..8434707ea15 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1379,10 +1379,14 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm, case SYMBOL_SMALL_TLSGD: { rtx_insn *insns; - rtx result = gen_rtx_REG (Pmode, R0_REGNUM); + machine_mode mode = GET_MODE (dest); + rtx result = gen_rtx_REG (mode, R0_REGNUM); start_sequence (); - aarch64_emit_call_insn (gen_tlsgd_small (result, imm)); + if (TARGET_ILP32) + aarch64_emit_call_insn (gen_tlsgd_small_si (result, imm)); + else + aarch64_emit_call_insn (gen_tlsgd_small_di (result, imm)); insns = get_insns (); end_sequence (); diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 6fc797920e6..957725758d1 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -5112,20 +5112,20 @@ ;; The TLS ABI specifically requires that the compiler does not schedule ;; instructions in the TLS stubs, in order to enable linker relaxation. ;; Therefore we treat the stubs as an atomic sequence. -(define_expand "tlsgd_small" +(define_expand "tlsgd_small_<mode>" [(parallel [(set (match_operand 0 "register_operand" "") (call (mem:DI (match_dup 2)) (const_int 1))) - (unspec:DI [(match_operand:DI 1 "aarch64_valid_symref" "")] UNSPEC_GOTSMALLTLS) + (unspec:DI [(match_operand:PTR 1 "aarch64_valid_symref" "")] UNSPEC_GOTSMALLTLS) (clobber (reg:DI LR_REGNUM))])] "" { operands[2] = aarch64_tls_get_addr (); }) -(define_insn "*tlsgd_small" +(define_insn "*tlsgd_small_<mode>" [(set (match_operand 0 "register_operand" "") (call (mem:DI (match_operand:DI 2 "" "")) (const_int 1))) - (unspec:DI [(match_operand:DI 1 "aarch64_valid_symref" "S")] UNSPEC_GOTSMALLTLS) + (unspec:DI [(match_operand:PTR 1 "aarch64_valid_symref" "S")] UNSPEC_GOTSMALLTLS) (clobber (reg:DI LR_REGNUM)) ] "" diff --git a/gcc/testsuite/gcc.target/aarch64/pr78382.c b/gcc/testsuite/gcc.target/aarch64/pr78382.c new file mode 100644 index 00000000000..febe7bc8d0a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr78382.c @@ -0,0 +1,10 @@ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-mtls-dialect=trad -fpic" } */ + +__thread int abc; +void +foo () +{ + int *p; + p = &abc; +} |