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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright 2016-2020 HabanaLabs, Ltd.
* All Rights Reserved.
*
*/
/************************************
** This is an auto-generated file **
** DO NOT EDIT BELOW **
************************************/
#ifndef ASIC_REG_PDMA0_CORE_CTX_REGS_H_
#define ASIC_REG_PDMA0_CORE_CTX_REGS_H_
/*
*****************************************
* PDMA0_CORE_CTX
* (Prototype: DMA_CORE_CTX)
*****************************************
*/
#define mmPDMA0_CORE_CTX_RATE_LIM_TKN 0x4C8B860
#define mmPDMA0_CORE_CTX_PWRLP 0x4C8B864
#define mmPDMA0_CORE_CTX_TE_NUMROWS 0x4C8B868
#define mmPDMA0_CORE_CTX_IDX 0x4C8B86C
#define mmPDMA0_CORE_CTX_IDX_INC 0x4C8B870
#define mmPDMA0_CORE_CTX_CTRL 0x4C8B874
#define mmPDMA0_CORE_CTX_SRC_TSIZE_0 0x4C8B878
#define mmPDMA0_CORE_CTX_SRC_TSIZE_1 0x4C8B87C
#define mmPDMA0_CORE_CTX_SRC_STRIDE_1 0x4C8B880
#define mmPDMA0_CORE_CTX_SRC_TSIZE_2 0x4C8B884
#define mmPDMA0_CORE_CTX_SRC_STRIDE_2 0x4C8B888
#define mmPDMA0_CORE_CTX_SRC_TSIZE_3 0x4C8B88C
#define mmPDMA0_CORE_CTX_SRC_STRIDE_3 0x4C8B890
#define mmPDMA0_CORE_CTX_SRC_TSIZE_4 0x4C8B894
#define mmPDMA0_CORE_CTX_SRC_STRIDE_4 0x4C8B898
#define mmPDMA0_CORE_CTX_DST_TSIZE_1 0x4C8B89C
#define mmPDMA0_CORE_CTX_DST_STRIDE_1 0x4C8B8A0
#define mmPDMA0_CORE_CTX_DST_TSIZE_2 0x4C8B8A4
#define mmPDMA0_CORE_CTX_DST_STRIDE_2 0x4C8B8A8
#define mmPDMA0_CORE_CTX_DST_TSIZE_3 0x4C8B8AC
#define mmPDMA0_CORE_CTX_DST_STRIDE_3 0x4C8B8B0
#define mmPDMA0_CORE_CTX_DST_TSIZE_4 0x4C8B8B4
#define mmPDMA0_CORE_CTX_DST_STRIDE_4 0x4C8B8B8
#define mmPDMA0_CORE_CTX_WR_COMP_ADDR_HI 0x4C8B8BC
#define mmPDMA0_CORE_CTX_WR_COMP_ADDR_LO 0x4C8B8C0
#define mmPDMA0_CORE_CTX_WR_COMP_WDATA 0x4C8B8C4
#define mmPDMA0_CORE_CTX_SRC_OFFSET_LO 0x4C8B8C8
#define mmPDMA0_CORE_CTX_SRC_OFFSET_HI 0x4C8B8CC
#define mmPDMA0_CORE_CTX_DST_OFFSET_LO 0x4C8B8D0
#define mmPDMA0_CORE_CTX_DST_OFFSET_HI 0x4C8B8D4
#define mmPDMA0_CORE_CTX_SRC_BASE_LO 0x4C8B8D8
#define mmPDMA0_CORE_CTX_SRC_BASE_HI 0x4C8B8DC
#define mmPDMA0_CORE_CTX_DST_BASE_LO 0x4C8B8E0
#define mmPDMA0_CORE_CTX_DST_BASE_HI 0x4C8B8E4
#define mmPDMA0_CORE_CTX_DST_TSIZE_0 0x4C8B8E8
#define mmPDMA0_CORE_CTX_COMMIT 0x4C8B8EC
#endif /* ASIC_REG_PDMA0_CORE_CTX_REGS_H_ */
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