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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright 2016-2020 HabanaLabs, Ltd.
* All Rights Reserved.
*
*/
/************************************
** This is an auto-generated file **
** DO NOT EDIT BELOW **
************************************/
#ifndef ASIC_REG_DCORE0_TPC0_CFG_KERNEL_REGS_H_
#define ASIC_REG_DCORE0_TPC0_CFG_KERNEL_REGS_H_
/*
*****************************************
* DCORE0_TPC0_CFG_KERNEL
* (Prototype: TPC_NON_TENSOR_DESCRIPTOR)
*****************************************
*/
#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0x400B508
#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0x400B50C
#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_0 0x400B510
#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_0 0x400B514
#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_1 0x400B518
#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_1 0x400B51C
#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_2 0x400B520
#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_2 0x400B524
#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_3 0x400B528
#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_3 0x400B52C
#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_4 0x400B530
#define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_4 0x400B534
#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_CONFIG 0x400B538
#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_ID 0x400B53C
#define mmDCORE0_TPC0_CFG_KERNEL_POWER_LOOP 0x400B540
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_0 0x400B544
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_1 0x400B548
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_2 0x400B54C
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_3 0x400B550
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_4 0x400B554
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_5 0x400B558
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_6 0x400B55C
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_7 0x400B560
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_8 0x400B564
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_9 0x400B568
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_10 0x400B56C
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_11 0x400B570
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_12 0x400B574
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_13 0x400B578
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_14 0x400B57C
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_15 0x400B580
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_16 0x400B584
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_17 0x400B588
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_18 0x400B58C
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_19 0x400B590
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_20 0x400B594
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_21 0x400B598
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_22 0x400B59C
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_23 0x400B5A0
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_24 0x400B5A4
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_25 0x400B5A8
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_26 0x400B5AC
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_27 0x400B5B0
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_28 0x400B5B4
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_29 0x400B5B8
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_30 0x400B5BC
#define mmDCORE0_TPC0_CFG_KERNEL_SRF_31 0x400B5C0
#define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_ID_INC 0x400B5C4
#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_0 0x400B5C8
#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_1 0x400B5CC
#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_2 0x400B5D0
#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_3 0x400B5D4
#define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_4 0x400B5D8
#endif /* ASIC_REG_DCORE0_TPC0_CFG_KERNEL_REGS_H_ */
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