diff options
author | Vishal Bhoj <vishal.bhoj@linaro.org> | 2014-06-02 11:20:28 +0530 |
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committer | Vishal Bhoj <vishal.bhoj@linaro.org> | 2014-06-02 11:20:28 +0530 |
commit | d0fc6571e7c769847836aad3071a3b21a820eae5 (patch) | |
tree | 2c3f69540a367929200c47bf024ecc5ae2a17dbb | |
parent | 3fa3bdcfdcb724087762c9dcf6b48e2525bbd6ff (diff) | |
parent | 90b51c33f362926e17d4c07dcef1ce822abaa89f (diff) |
Merge remote-tracking branch 'origin/master'
429 files changed, 19112 insertions, 9259 deletions
@@ -8,7 +8,7 @@ VERSION = 2014 PATCHLEVEL = 07 SUBLEVEL = -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc2 NAME = # *DOCUMENTATION* @@ -699,6 +699,7 @@ PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name` endif PLATFORM_LIBS += $(PLATFORM_LIBGCC) export PLATFORM_LIBS +export PLATFORM_LIBGCC # Special flags for CPP when processing the linker script. # Pass the version down so we can handle backwards compatibility @@ -752,6 +753,9 @@ ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb u-boot-dtb.bin +ifeq ($(CONFIG_SPL_FRAMEWORK),y) +ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img +endif ALL-$(CONFIG_OF_HOSTFILE) += u-boot.dtb ifneq ($(CONFIG_SPL_TARGET),) ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%) @@ -854,6 +858,11 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE $(call if_changed,mkimage) +MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img) + +u-boot-dtb.img: u-boot-dtb.bin FORCE + $(call if_changed,mkimage) + u-boot.sha1: u-boot.bin tools/ubsha1 u-boot.bin @@ -893,7 +902,7 @@ MKIMAGEFLAGS_u-boot-spl.ais = -s -n $(if $(CONFIG_AIS_CONFIG_FILE), \ spl/u-boot-spl.ais: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) -OBJCOPYFLAGS_u-boot.ais = -I binary -O binary --pad-to=$(CONFIG_SPL_MAX_SIZE) +OBJCOPYFLAGS_u-boot.ais = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) u-boot.ais: spl/u-boot-spl.ais u-boot.img FORCE $(call if_changed,pad_cat) @@ -928,6 +937,13 @@ OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE $(call if_changed,pad_cat) +ifneq ($(CONFIG_SUNXI),) +OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \ + --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff +u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE + $(call if_changed,pad_cat) +endif + ifneq ($(CONFIG_TEGRA),) OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE) u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot.bin FORCE @@ -1154,6 +1170,9 @@ spl/u-boot-spl.bin: spl/u-boot-spl spl/u-boot-spl: tools prepare $(Q)$(MAKE) obj=spl -f $(srctree)/spl/Makefile all +spl/sunxi-spl.bin: spl/u-boot-spl + @: + tpl/u-boot-tpl.bin: tools prepare $(Q)$(MAKE) obj=tpl -f $(srctree)/spl/Makefile all CONFIG_TPL_BUILD=y @@ -1534,6 +1534,16 @@ The following options need to be configured: CONFIG_SH_MMCIF_CLK Define the clock frequency for MMCIF + CONFIG_GENERIC_MMC + Enable the generic MMC driver + + CONFIG_SUPPORT_EMMC_BOOT + Enable some additional features of the eMMC boot partitions. + + CONFIG_SUPPORT_EMMC_RPMB + Enable the commands for reading, writing and programming the + key for the Replay Protection Memory Block partition in eMMC. + - USB Device Firmware Update (DFU) class support: CONFIG_DFU_FUNCTION This enables the USB portion of the DFU USB class @@ -1579,6 +1589,28 @@ The following options need to be configured: entering dfuMANIFEST state. Host waits this timeout, before sending again an USB request to the device. +- USB Device Android Fastboot support: + CONFIG_CMD_FASTBOOT + This enables the command "fastboot" which enables the Android + fastboot mode for the platform's USB device. Fastboot is a USB + protocol for downloading images, flashing and device control + used on Android devices. + See doc/README.android-fastboot for more information. + + CONFIG_ANDROID_BOOT_IMAGE + This enables support for booting images which use the Android + image format header. + + CONFIG_USB_FASTBOOT_BUF_ADDR + The fastboot protocol requires a large memory buffer for + downloads. Define this to the starting RAM address to use for + downloaded images. + + CONFIG_USB_FASTBOOT_BUF_SIZE + The fastboot protocol requires a large memory buffer for + downloads. This buffer should be as large as possible for a + platform. Define this to the size available RAM for fastboot. + - Journaling Flash filesystem support: CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE, CONFIG_JFFS2_NAND_DEV @@ -2550,6 +2582,19 @@ CBFS (Coreboot Filesystem) support Specify the number of FPGA devices to support. + CONFIG_CMD_FPGA_LOADMK + + Enable support for fpga loadmk command + + CONFIG_CMD_FPGA_LOADP + + Enable support for fpga loadp command - load partial bitstream + + CONFIG_CMD_FPGA_LOADBP + + Enable support for fpga loadbp command - load partial bitstream + (Xilinx only) + CONFIG_SYS_FPGA_PROG_FEEDBACK Enable printing of hash marks during FPGA configuration. diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 3e2358e13..1cfcca9fa 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -15,48 +15,7 @@ #include <asm-offsets.h> #include <config.h> #include <version.h> -.globl _start -_start: b reset -#ifdef CONFIG_SPL_BUILD - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang -_hang: - .word do_hang - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 /* now 16*4=64 */ -#else - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#endif /* CONFIG_SPL_BUILD */ -.global _end_vect -_end_vect: - - .balignl 16,0xdeadbeef /* ************************************************************************* * @@ -70,26 +29,7 @@ _end_vect: ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -152,195 +92,3 @@ cpu_init_crit: mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack - ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_bad_stack_swi - sub r13, r13, #4 @ space on current stack for scratch reg. - str r0, [r13] @ save R0's value. - ldr r0, IRQ_STACK_START_IN @ get data regions start - str lr, [r0] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r0, #4] @ save spsr in position 1 of saved stack - ldr lr, [r0] @ restore lr - ldr r0, [r13] @ restore r0 - add r13, r13, #4 @ pop stack entry - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm -#endif /* CONFIG_SPL_BUILD */ - -/* - * exception handlers - */ -#ifdef CONFIG_SPL_BUILD - .align 5 -do_hang: - bl hang /* hang and never return */ -#else /* !CONFIG_SPL_BUILD */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - .align 5 -.global arm1136_cache_flush -arm1136_cache_flush: -#if !defined(CONFIG_SYS_ICACHE_OFF) - mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache -#endif -#if !defined(CONFIG_SYS_DCACHE_OFF) - mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache -#endif - mov pc, lr @ back to caller -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index ce620115d..0704bdde2 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -25,48 +25,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - -.globl _start -_start: b reset -#ifndef CONFIG_SPL_BUILD - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq -_pad: - .word 0x12345678 /* now 16*4=64 */ -#else - . = _start + 64 -#endif - -.global _end_vect -_end_vect: - .balignl 16,0xdeadbeef -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from memory! @@ -77,14 +35,7 @@ _end_vect: ************************************************************************* */ -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -182,150 +133,3 @@ skip_tcmdisable: c_runtime_cpu_setup: mov pc, lr - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - */ - - .macro bad_save_user_regs - /* carve out a frame on current user stack */ - sub sp, sp, #S_FRAME_SIZE - /* Save user registers (now in svc mode) r0-r12 */ - stmia sp, {r0 - r12} - - ldr r2, IRQ_STACK_START_IN - /* get values for "aborted" pc and cpsr (into parm regs) */ - ldmia r2, {r2 - r3} - /* grab pointer to old stack */ - add r0, sp, #S_FRAME_SIZE - - add r5, sp, #S_SP - mov r1, lr - /* save sp_SVC, lr_SVC, pc, cpsr */ - stmia r5, {r0 - r3} - /* save current stack into r0 (param register) */ - mov r0, sp - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - /* save caller lr in position 0 of saved stack */ - str lr, [r13] - /* get the spsr */ - mrs lr, spsr - /* save spsr in position 1 of saved stack */ - str lr, [r13, #4] - - /* prepare SVC-Mode */ - mov r13, #MODE_SVC - @ msr spsr_c, r13 - /* switch modes, make sure moves will execute */ - msr spsr, r13 - /* capture return pc */ - mov lr, pc - /* jump to next instruction & switch modes. */ - movs pc, lr - .endm - - .macro get_bad_stack_swi - /* space on current stack for scratch reg. */ - sub r13, r13, #4 - /* save R0's value. */ - str r0, [r13] - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - /* save caller lr in position 0 of saved stack */ - str lr, [r0] - /* get the spsr */ - mrs lr, spsr - /* save spsr in position 1 of saved stack */ - str lr, [r0, #4] - /* restore lr */ - ldr lr, [r0] - /* restore r0 */ - ldr r0, [r13] - /* pop stack entry */ - add r13, r13, #4 - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 1a3484269..01c85be64 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -15,48 +15,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -#ifdef CONFIG_SPL_BUILD -_undefined_instruction: .word _undefined_instruction -_software_interrupt: .word _software_interrupt -_prefetch_abort: .word _prefetch_abort -_data_abort: .word _data_abort -_not_used: .word _not_used -_irq: .word _irq -_fiq: .word _fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#else -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#endif /* CONFIG_SPL_BUILD */ - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from RAM! @@ -67,26 +25,7 @@ _pad: .word 0x12345678 /* now 16*4=64 */ ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -139,169 +78,3 @@ cpu_init_crit: mov pc, lr #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - msr spsr_c, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 168f525ec..c6f3b029a 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -82,7 +82,7 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ }, /* - * T30: 1.4 GHz + * T30: 600 MHz * * Register Field Bits Width * ------------------------------ @@ -92,10 +92,10 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { * PLLX_MISC cpcon 11: 8 4 */ { - { .n = 862, .m = 8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ - { .n = 583, .m = 8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */ - { .n = 700, .m = 6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ - { .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ + { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ + { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ + { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ }, /* * T114: 700 MHz diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c index a80648389..9003902e3 100644 --- a/arch/arm/cpu/arm720t/tegra30/cpu.c +++ b/arch/arm/cpu/arm720t/tegra30/cpu.c @@ -41,10 +41,18 @@ void tegra_i2c_ll_write_data(uint data, uint config) writel(config, ®->cnfg); } +#define TPS62366A_I2C_ADDR 0xC0 +#define TPS62366A_SET1_REG 0x01 +#define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG) + +#define TPS62361B_I2C_ADDR 0xC0 +#define TPS62361B_SET3_REG 0x03 +#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG) + #define TPS65911_I2C_ADDR 0x5A #define TPS65911_VDDCTRL_OP_REG 0x28 #define TPS65911_VDDCTRL_SR_REG 0x27 -#define TPS65911_VDDCTRL_OP_DATA (0x2300 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) #define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) #define I2C_SEND_2_BYTES 0x0A02 @@ -58,9 +66,20 @@ static void enable_cpu_power_rail(void) reg |= CPUPWRREQ_OE; writel(reg, &pmc->pmc_cntrl); + /* Set VDD_CORE to 1.200V. */ +#ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 + tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2); + tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES); +#endif +#ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3 + tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2); + tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES); +#endif + udelay(1000); + /* * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. - * First set VDD to 1.4V, then enable the VDD regulator. + * First set VDD to 1.0125V, then enable the VDD regulator. */ tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2); tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES); diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds index 96994043e..623a63520 100644 --- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds +++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds @@ -16,7 +16,8 @@ SECTIONS .text : { *(.__image_copy_start) - arch/arm/cpu/arm920t/start.o (.text*) + *(.vectors) + arch/arm/cpu/arm920t/start.o (.text*) /* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */ . = 0x1000; LONG(0x53555243) diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 7bf094aec..07404502c 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -15,36 +15,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b start_code - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * * Startup Code (called from the ARM reset exception vector) * * do important init only if we don't start from memory! @@ -55,28 +25,9 @@ _fiq: .word fiq ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de + .globl reset -/* - * the actual start code - */ - -start_code: +reset: /* * set the cpu to SVC32 mode */ @@ -196,166 +147,3 @@ cpu_init_crit: mov lr, ip mov pc, lr #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r3} @ get pc, cpsr - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r7, sp, #S_PC - stmdb r7, {sp, lr}^ @ Calling SP, LR - str lr, [r7, #0] @ Save calling PC - mrs r6, spsr - str r6, [r7, #4] @ Save CPSR - str r0, [r7, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - /* return & move spsr_svc into cpsr */ - subs pc, lr, #4 - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c index 7d7725c4b..0e6c0da1b 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -165,3 +165,20 @@ void at91_macb_hw_init(void) #endif } #endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI +void at91_mci_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI0 CLK */ + at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI0 CDA */ + at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI0 DA0 */ + at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* MCI0 DA1 */ + at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI0 DA2 */ + at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI0 DA3 */ + + /* Enable clock */ + writel(1 << ATMEL_ID_MCI0, &pmc->pcer); +} +#endif diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index d4711c070..093750626 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -13,7 +13,6 @@ #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/kirkwood.h> -#include <hush.h> #define BUFLEN 16 diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index 34a0fcb46..9b6043653 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -27,70 +27,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: - b reset - b undefined_instruction - b software_interrupt - b prefetch_abort - b data_abort - b not_used - b irq - b fiq - -/* - * Vector table, located at address 0x20. - * This table allows the code running AFTER SPL, the U-Boot, to install it's - * interrupt handlers here. The problem is that the U-Boot is loaded into RAM, - * including it's interrupt vectoring table and the table at 0x0 is still the - * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table - * is still used. - */ -_vt_reset: - .word _reset -_vt_undefined_instruction: - .word _hang -_vt_software_interrupt: - .word _hang -_vt_prefetch_abort: - .word _hang -_vt_data_abort: - .word _hang -_vt_not_used: - .word _reset -_vt_irq: - .word _hang -_vt_fiq: - .word _hang - -reset: - ldr pc, _vt_reset -undefined_instruction: - ldr pc, _vt_undefined_instruction -software_interrupt: - ldr pc, _vt_software_interrupt -prefetch_abort: - ldr pc, _vt_prefetch_abort -data_abort: - ldr pc, _vt_data_abort -not_used: - ldr pc, _vt_not_used -irq: - ldr pc, _vt_irq -fiq: - ldr pc, _vt_fiq - - .balignl 16,0xdeadbeef - -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from memory! @@ -101,28 +37,8 @@ fiq: ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ - -_reset: + .globl reset +reset: /* * If the CPU is configured in "Wait JTAG connection mode", the stack * pointer is not configured and is zero. This will cause crash when @@ -179,7 +95,3 @@ _reset: mov r0, #0 bx lr - -_hang: -1: - bl 1b /* hang and never return */ diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index b55c5f094..f88db3b1f 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -15,7 +15,6 @@ #include <asm/io.h> #include <u-boot/md5.h> #include <asm/arch/cpu.h> -#include <hush.h> #define BUFLEN 16 diff --git a/arch/arm/cpu/arm926ejs/spear/start.S b/arch/arm/cpu/arm926ejs/spear/start.S index 7dbd5dbf9..290ac2e56 100644 --- a/arch/arm/cpu/arm926ejs/spear/start.S +++ b/arch/arm/cpu/arm926ejs/spear/start.S @@ -17,29 +17,6 @@ #include <config.h> -.globl _start -_start: - b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: -_software_interrupt: -_prefetch_abort: -_data_abort: -_not_used: -_irq: -_fiq: - .word infinite_loop - -infinite_loop: - b infinite_loop - /* ************************************************************************* * @@ -53,9 +30,7 @@ infinite_loop: ************************************************************************* */ -/* - * the actual reset code - */ + .globl reset reset: /* diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds index b6d0f65b6..c7ee19912 100644 --- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds @@ -21,6 +21,7 @@ SECTIONS . = ALIGN(4); .text : { + *(.vectors) arch/arm/cpu/arm926ejs/spear/start.o (.text*) *(.text*) } diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 071732705..8eb249475 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -23,75 +23,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG -.globl _start -_start: -.globl _NOR_BOOT_CFG -_NOR_BOOT_CFG: - .word CONFIG_SYS_DV_NOR_BOOT_CFG - b reset -#else -.globl _start -_start: - b reset -#endif -#ifdef CONFIG_SPL_BUILD -/* No exception handlers in preloader */ - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - -_hang: - .word do_hang -/* pad to 64 byte boundary */ - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 -#else - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq - -#endif /* CONFIG_SPL_BUILD */ - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from memory! @@ -102,26 +33,7 @@ _fiq: ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -198,175 +110,3 @@ flush_dcache: mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - @ carve out a frame on current user stack - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - ldr r2, IRQ_STACK_START_IN - @ get values for "aborted" pc and cpsr (into parm regs) - ldmia r2, {r2 - r3} - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm -#endif /* CONFIG_SPL_BUILD */ - -/* - * exception handlers - */ -#ifdef CONFIG_SPL_BUILD - .align 5 -do_hang: -1: - bl 1b /* hang and never return */ -#else /* !CONFIG_SPL_BUILD */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm946es/cpu.c b/arch/arm/cpu/arm946es/cpu.c index 0c8d92d73..e20e5a89a 100644 --- a/arch/arm/cpu/arm946es/cpu.c +++ b/arch/arm/cpu/arm946es/cpu.c @@ -16,6 +16,7 @@ #include <common.h> #include <command.h> #include <asm/system.h> +#include <asm/io.h> static void cache_flush(void); @@ -51,3 +52,15 @@ static void cache_flush (void) asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i)); } + +#ifndef CONFIG_INTEGRATOR + +__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused))) +{ + writew(0x0, 0xfffece10); + writew(0x8, 0xfffece10); + for (;;) + ; +} + +#endif /* #ifdef CONFIG_INTEGRATOR */ diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 7d5014583..41123716a 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -22,45 +22,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: - b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq - - .balignl 16,0xdeadbeef - -_vectors_end: - -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from memory! @@ -71,26 +32,7 @@ _vectors_end: ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -157,189 +99,3 @@ cpu_init_crit: mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ #endif -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - @ carve out a frame on current user stack - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, IRQ_STACK_START_IN - @ get values for "aborted" pc and cpsr (into parm regs) - ldmia r2, {r2 - r3} - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - -# ifdef CONFIG_INTEGRATOR - - /* Satisfied by general board level routine */ - -#else - - .align 5 -.globl reset_cpu -reset_cpu: - - ldr r1, rstctl1 /* get clkm1 reset ctl */ - mov r3, #0x0 - strh r3, [r1] /* clear it */ - mov r3, #0x8 - strh r3, [r1] /* force dsp+arm reset */ -_loop_forever: - b _loop_forever - -rstctl1: - .word 0xfffece10 - -#endif /* #ifdef CONFIG_INTEGRATOR */ diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index 7404ea734..c0c07b6a1 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -21,42 +21,6 @@ /* ************************************************************************* * - * Jump vector table - * - ************************************************************************* - */ - -.globl _start -_start: - b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq - - .balignl 16,0xdeadbeef - -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from memory! @@ -67,26 +31,7 @@ _fiq: ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -132,174 +77,3 @@ cpu_init_crit: */ mov pc, lr /* back to my caller */ #endif -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - @ carve out a frame on current user stack - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, IRQ_STACK_START_IN - @ get values for "aborted" pc and cpsr (into parm regs) - ldmia r2, {r2 - r3} - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -.globl undefined_instruction -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -.globl software_interrupt -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -.globl prefetch_abort -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -.globl data_abort -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -.globl not_used -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - .align 5 -.globl irq -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -.globl fiq -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -.globl irq -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -.globl fiq -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index ab869b1ee..232118d7f 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,7 +12,7 @@ obj-y += cache_v7.o obj-y += cpu.o obj-y += syslib.o -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),) ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index 5566310d9..aae3f096b 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -14,7 +14,6 @@ endif obj-$(CONFIG_TI816X) += clock_ti816x.o obj-y += sys_info.o -obj-y += mem.o obj-y += ddr.o obj-y += emif4.o obj-y += board.o diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c deleted file mode 100644 index 56c9e7dbc..000000000 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Author : - * Mansoor Ahamed <mansoor.ahamed@ti.com> - * - * Initial Code from: - * Manikandan Pillai <mani.pillai@ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/cpu.h> -#include <asm/arch/mem.h> -#include <asm/arch/sys_proto.h> -#include <command.h> - -struct gpmc *gpmc_cfg; - - -void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, - u32 size) -{ - writel(0, &cs->config7); - sdelay(1000); - /* Delay for settling */ - writel(gpmc_config[0], &cs->config1); - writel(gpmc_config[1], &cs->config2); - writel(gpmc_config[2], &cs->config3); - writel(gpmc_config[3], &cs->config4); - writel(gpmc_config[4], &cs->config5); - writel(gpmc_config[5], &cs->config6); - /* Enable the config */ - writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | - (1 << 6)), &cs->config7); - sdelay(2000); -} - -/***************************************************** - * gpmc_init(): init gpmc bus - * Init GPMC for x16, MuxMode (SDRAM in x32). - * This code can only be executed from SRAM or SDRAM. - *****************************************************/ -void gpmc_init(void) -{ - /* putting a blanket check on GPMC based on ZeBu for now */ - gpmc_cfg = (struct gpmc *)GPMC_BASE; -#if defined(CONFIG_NOR) -/* configure GPMC for NOR */ - const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, - STNOR_GPMC_CONFIG2, - STNOR_GPMC_CONFIG3, - STNOR_GPMC_CONFIG4, - STNOR_GPMC_CONFIG5, - STNOR_GPMC_CONFIG6, - STNOR_GPMC_CONFIG7 - }; - u32 size = GPMC_SIZE_16M; - u32 base = CONFIG_SYS_FLASH_BASE; -#elif defined(CONFIG_NAND) -/* configure GPMC for NAND */ - const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, - M_NAND_GPMC_CONFIG2, - M_NAND_GPMC_CONFIG3, - M_NAND_GPMC_CONFIG4, - M_NAND_GPMC_CONFIG5, - M_NAND_GPMC_CONFIG6, - 0 - }; - u32 size = GPMC_SIZE_256M; - u32 base = CONFIG_SYS_NAND_BASE; -#else - const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 }; - u32 size = 0; - u32 base = 0; -#endif - /* global settings */ - writel(0x00000008, &gpmc_cfg->sysconfig); - writel(0x00000000, &gpmc_cfg->irqstatus); - writel(0x00000000, &gpmc_cfg->irqenable); -#ifdef CONFIG_NOR - writel(0x00000200, &gpmc_cfg->config); -#else - writel(0x00000012, &gpmc_cfg->config); -#endif - /* - * Disable the GPMC0 config set by ROM code - */ - writel(0, &gpmc_cfg->cs[0].config7); - sdelay(1000); - /* enable chip-select specific configurations */ - enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); -} diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c index 50eb598ff..2ce682f6b 100644 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@ -79,12 +79,24 @@ u32 get_sysboot_value(void) } #ifdef CONFIG_DISPLAY_CPUINFO +static char *cpu_revs[] = { + "1.0", + "2.0", + "2.1"}; + + +static char *dev_types[] = { + "TST", + "EMU", + "HS", + "GP"}; + /** * Print CPU information */ int print_cpuinfo(void) { - char *cpu_s, *sec_s; + char *cpu_s, *sec_s, *rev_s; switch (get_cpu_type()) { case AM335X: @@ -94,28 +106,21 @@ int print_cpuinfo(void) cpu_s = "TI81XX"; break; default: - cpu_s = "Unknown cpu type"; + cpu_s = "Unknown CPU type"; break; } - switch (get_device_type()) { - case TST_DEVICE: - sec_s = "TST"; - break; - case EMU_DEVICE: - sec_s = "EMU"; - break; - case HS_DEVICE: - sec_s = "HS"; - break; - case GP_DEVICE: - sec_s = "GP"; - break; - default: + if (get_cpu_rev() < ARRAY_SIZE(cpu_revs)) + rev_s = cpu_revs[get_cpu_rev()]; + else + rev_s = "?"; + + if (get_device_type() < ARRAY_SIZE(dev_types)) + sec_s = dev_types[get_device_type()]; + else sec_s = "?"; - } - printf("%s-%s rev %d\n", cpu_s, sec_s, get_cpu_rev()); + printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s); return 0; } diff --git a/arch/arm/cpu/armv7/at91/config.mk b/arch/arm/cpu/armv7/at91/config.mk new file mode 100644 index 000000000..09eab7095 --- /dev/null +++ b/arch/arm/cpu/armv7/at91/config.mk @@ -0,0 +1,10 @@ +# +# Copyright (C) 2014, Andreas Bießmann <andreas.devel@googlemail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# +ifdef CONFIG_SPL_BUILD +ALL-y += boot.bin +else +ALL-y += u-boot.img +endif diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 9edb47502..ee7c2e5a4 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -13,30 +13,23 @@ static void exynos5_uart_config(int peripheral) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank; int i, start, count; switch (peripheral) { case PERIPH_ID_UART0: - bank = &gpio1->a0; - start = 0; + start = EXYNOS5_GPIO_A00; count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->d0; - start = 0; + start = EXYNOS5_GPIO_D00; count = 4; break; case PERIPH_ID_UART2: - bank = &gpio1->a1; - start = 0; + start = EXYNOS5_GPIO_A10; count = 4; break; case PERIPH_ID_UART3: - bank = &gpio1->a1; - start = 4; + start = EXYNOS5_GPIO_A14; count = 2; break; default: @@ -44,37 +37,30 @@ static void exynos5_uart_config(int peripheral) return; } for (i = start; i < start + count; i++) { - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); } } static void exynos5420_uart_config(int peripheral) { - struct exynos5420_gpio_part1 *gpio1 = - (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank; int i, start, count; switch (peripheral) { case PERIPH_ID_UART0: - bank = &gpio1->a0; - start = 0; + start = EXYNOS5420_GPIO_A00; count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->a0; - start = 4; + start = EXYNOS5420_GPIO_A04; count = 4; break; case PERIPH_ID_UART2: - bank = &gpio1->a1; - start = 0; + start = EXYNOS5420_GPIO_A10; count = 4; break; case PERIPH_ID_UART3: - bank = &gpio1->a1; - start = 4; + start = EXYNOS5420_GPIO_A14; count = 2; break; default: @@ -83,64 +69,59 @@ static void exynos5420_uart_config(int peripheral) } for (i = start; i < start + count; i++) { - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); } } static int exynos5_mmc_config(int peripheral, int flags) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank, *bank_ext; - int i, start = 0, gpio_func = 0; + int i, start, start_ext, gpio_func = 0; switch (peripheral) { case PERIPH_ID_SDMMC0: - bank = &gpio1->c0; - bank_ext = &gpio1->c1; - start = 0; - gpio_func = GPIO_FUNC(0x2); + start = EXYNOS5_GPIO_C00; + start_ext = EXYNOS5_GPIO_C10; + gpio_func = S5P_GPIO_FUNC(0x2); break; case PERIPH_ID_SDMMC1: - bank = &gpio1->c2; - bank_ext = NULL; + start = EXYNOS5_GPIO_C20; + start_ext = 0; break; case PERIPH_ID_SDMMC2: - bank = &gpio1->c3; - bank_ext = &gpio1->c4; - start = 3; - gpio_func = GPIO_FUNC(0x3); + start = EXYNOS5_GPIO_C30; + start_ext = EXYNOS5_GPIO_C43; + gpio_func = S5P_GPIO_FUNC(0x3); break; case PERIPH_ID_SDMMC3: - bank = &gpio1->c4; - bank_ext = NULL; + start = EXYNOS5_GPIO_C40; + start_ext = 0; break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; } - if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { debug("SDMMC device %d does not support 8bit mode", peripheral); return -1; } if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = start; i <= (start + 3); i++) { - s5p_gpio_cfg_pin(bank_ext, i, gpio_func); - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + for (i = start_ext; i <= (start_ext + 3); i++) { + gpio_cfg_pin(i, gpio_func); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } } - for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + for (i = start; i < (start + 2); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } - for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + for (i = (start + 3); i <= (start + 6); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } return 0; @@ -148,26 +129,20 @@ static int exynos5_mmc_config(int peripheral, int flags) static int exynos5420_mmc_config(int peripheral, int flags) { - struct exynos5420_gpio_part3 *gpio3 = - (struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3(); - struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL; - int i, start; + int i, start = 0, start_ext = 0; switch (peripheral) { case PERIPH_ID_SDMMC0: - bank = &gpio3->c0; - bank_ext = &gpio3->c3; - start = 0; + start = EXYNOS5420_GPIO_C00; + start_ext = EXYNOS5420_GPIO_C30; break; case PERIPH_ID_SDMMC1: - bank = &gpio3->c1; - bank_ext = &gpio3->d1; - start = 4; + start = EXYNOS5420_GPIO_C10; + start_ext = EXYNOS5420_GPIO_D14; break; case PERIPH_ID_SDMMC2: - bank = &gpio3->c2; - bank_ext = NULL; - start = 0; + start = EXYNOS5420_GPIO_C20; + start_ext = 0; break; default: start = 0; @@ -175,41 +150,41 @@ static int exynos5420_mmc_config(int peripheral, int flags) return -1; } - if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { debug("SDMMC device %d does not support 8bit mode", peripheral); return -1; } if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = start; i <= (start + 3); i++) { - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + for (i = start_ext; i <= (start_ext + 3); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } } - for (i = 0; i < 3; i++) { + for (i = start; i < (start + 3); i++) { /* * MMC0 is intended to be used for eMMC. The * card detect pin is used as a VDDEN signal to * power on the eMMC. The 5420 iROM makes * this same assumption. */ - if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) { - s5p_gpio_set_value(bank, i, 1); - s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT); + if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) { + gpio_set_value(i, 1); + gpio_cfg_pin(i, S5P_GPIO_OUTPUT); } else { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); } - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } - for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + for (i = (start + 3); i <= (start + 6); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } return 0; @@ -217,8 +192,6 @@ static int exynos5420_mmc_config(int peripheral, int flags) static void exynos5_sromc_config(int flags) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); int i; /* @@ -236,13 +209,13 @@ static void exynos5_sromc_config(int flags) * GPY1[2] SROM_WAIT(2) * GPY1[3] EBI_DATA_RDn(2) */ - s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK), - GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK), + S5P_GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2)); for (i = 0; i < 4; i++) - s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2)); /* * EBI: 8 Addrss Lines @@ -277,108 +250,101 @@ static void exynos5_sromc_config(int flags) * GPY6[7] EBI_DATA[15](2) */ for (i = 0; i < 8; i++) { - s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP); + gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2)); + gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP); - s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP); + gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2)); + gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP); - s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); + gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2)); + gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP); } } static void exynos5_i2c_config(int peripheral, int flags) { - - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - switch (peripheral) { case PERIPH_ID_I2C0: - s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C1: - s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C2: - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C3: - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C4: - s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C5: - s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C6: - s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4)); break; case PERIPH_ID_I2C7: - s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3)); break; } } static void exynos5420_i2c_config(int peripheral) { - struct exynos5420_gpio_part1 *gpio1 = - (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); - switch (peripheral) { case PERIPH_ID_I2C0: - s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C1: - s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C2: - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C3: - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C4: - s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C5: - s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C6: - s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4)); break; case PERIPH_ID_I2C7: - s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C8: - s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C9: - s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C10: - s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2)); break; } } @@ -386,19 +352,15 @@ static void exynos5420_i2c_config(int peripheral) static void exynos5_i2s_config(int peripheral) { int i; - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1(); - struct exynos5_gpio_part4 *gpio4 = - (struct exynos5_gpio_part4 *)samsung_get_base_gpio_part4(); switch (peripheral) { case PERIPH_ID_I2S0: for (i = 0; i < 5; i++) - s5p_gpio_cfg_pin(&gpio4->z, i, GPIO_FUNC(0x02)); + gpio_cfg_pin(EXYNOS5_GPIO_Z0 + i, S5P_GPIO_FUNC(0x02)); break; case PERIPH_ID_I2S1: for (i = 0; i < 5; i++) - s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02)); + gpio_cfg_pin(EXYNOS5_GPIO_B00 + i, S5P_GPIO_FUNC(0x02)); break; } } @@ -406,75 +368,57 @@ static void exynos5_i2s_config(int peripheral) void exynos5_spi_config(int peripheral) { int cfg = 0, pin = 0, i; - struct s5p_gpio_bank *bank = NULL; - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - struct exynos5_gpio_part2 *gpio2 = - (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2(); switch (peripheral) { case PERIPH_ID_SPI0: - bank = &gpio1->a2; - cfg = GPIO_FUNC(0x2); - pin = 0; + cfg = S5P_GPIO_FUNC(0x2); + pin = EXYNOS5_GPIO_A20; break; case PERIPH_ID_SPI1: - bank = &gpio1->a2; - cfg = GPIO_FUNC(0x2); - pin = 4; + cfg = S5P_GPIO_FUNC(0x2); + pin = EXYNOS5_GPIO_A24; break; case PERIPH_ID_SPI2: - bank = &gpio1->b1; - cfg = GPIO_FUNC(0x5); - pin = 1; + cfg = S5P_GPIO_FUNC(0x5); + pin = EXYNOS5_GPIO_B11; break; case PERIPH_ID_SPI3: - bank = &gpio2->f1; - cfg = GPIO_FUNC(0x2); - pin = 0; + cfg = S5P_GPIO_FUNC(0x2); + pin = EXYNOS5_GPIO_F10; break; case PERIPH_ID_SPI4: for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4)); } break; } if (peripheral != PERIPH_ID_SPI4) { for (i = pin; i < pin + 4; i++) - s5p_gpio_cfg_pin(bank, i, cfg); + gpio_cfg_pin(i, cfg); } } void exynos5420_spi_config(int peripheral) { int cfg, pin, i; - struct s5p_gpio_bank *bank = NULL; - struct exynos5420_gpio_part1 *gpio1 = - (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); - struct exynos5420_gpio_part4 *gpio4 = - (struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4(); switch (peripheral) { case PERIPH_ID_SPI0: - bank = &gpio1->a2; - cfg = GPIO_FUNC(0x2); - pin = 0; + pin = EXYNOS5420_GPIO_A20; + cfg = S5P_GPIO_FUNC(0x2); break; case PERIPH_ID_SPI1: - bank = &gpio1->a2; - cfg = GPIO_FUNC(0x2); - pin = 4; + pin = EXYNOS5420_GPIO_A24; + cfg = S5P_GPIO_FUNC(0x2); break; case PERIPH_ID_SPI2: - bank = &gpio1->b1; - cfg = GPIO_FUNC(0x5); - pin = 1; + pin = EXYNOS5420_GPIO_B11; + cfg = S5P_GPIO_FUNC(0x5); break; case PERIPH_ID_SPI3: - bank = &gpio4->f1; - cfg = GPIO_FUNC(0x2); - pin = 0; + pin = EXYNOS5420_GPIO_F10; + cfg = S5P_GPIO_FUNC(0x2); break; case PERIPH_ID_SPI4: cfg = 0; @@ -489,11 +433,13 @@ void exynos5420_spi_config(int peripheral) if (peripheral != PERIPH_ID_SPI4) { for (i = pin; i < pin + 4; i++) - s5p_gpio_cfg_pin(bank, i, cfg); + gpio_cfg_pin(i, cfg); } else { for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i, + S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i, + S5P_GPIO_FUNC(0x4)); } } } @@ -588,76 +534,70 @@ static int exynos5420_pinmux_config(int peripheral, int flags) static void exynos4_i2c_config(int peripheral, int flags) { - struct exynos4_gpio_part1 *gpio1 = - (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1(); - switch (peripheral) { case PERIPH_ID_I2C0: - s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D10, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D11, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C1: - s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D12, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D13, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C2: - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A07, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C3: - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A13, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C4: - s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B2, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B3, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C5: - s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B6, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B7, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C6: - s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS4_GPIO_C13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS4_GPIO_C14, S5P_GPIO_FUNC(0x4)); break; case PERIPH_ID_I2C7: - s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_D02, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_D03, S5P_GPIO_FUNC(0x3)); break; } } static int exynos4_mmc_config(int peripheral, int flags) { - struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - struct s5p_gpio_bank *bank, *bank_ext; - int i; + int i, start = 0, start_ext = 0; switch (peripheral) { case PERIPH_ID_SDMMC0: - bank = &gpio2->k0; - bank_ext = &gpio2->k1; + start = EXYNOS4_GPIO_K00; + start_ext = EXYNOS4_GPIO_K13; break; case PERIPH_ID_SDMMC2: - bank = &gpio2->k2; - bank_ext = &gpio2->k3; + start = EXYNOS4_GPIO_K20; + start_ext = EXYNOS4_GPIO_K33; break; default: return -1; } - for (i = 0; i < 7; i++) { - if (i == 2) + for (i = start; i < (start + 7); i++) { + if (i == (start + 2)) continue; - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = 3; i < 7; i++) { - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + for (i = start_ext; i < (start_ext + 4); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } } @@ -666,41 +606,138 @@ static int exynos4_mmc_config(int peripheral, int flags) static void exynos4_uart_config(int peripheral) { - struct exynos4_gpio_part1 *gpio1 = - (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank; int i, start, count; switch (peripheral) { case PERIPH_ID_UART0: - bank = &gpio1->a0; - start = 0; + start = EXYNOS4_GPIO_A00; count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->a0; - start = 4; + start = EXYNOS4_GPIO_A04; count = 4; break; case PERIPH_ID_UART2: - bank = &gpio1->a1; - start = 0; + start = EXYNOS4_GPIO_A10; count = 4; break; case PERIPH_ID_UART3: - bank = &gpio1->a1; - start = 4; + start = EXYNOS4_GPIO_A14; count = 2; break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return; } - for (i = start; i < start + count; i++) { - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + for (i = start; i < (start + count); i++) { + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + } +} + +static void exynos4x12_i2c_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_I2C0: + gpio_cfg_pin(EXYNOS4X12_GPIO_D10, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4X12_GPIO_D11, S5P_GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C1: + gpio_cfg_pin(EXYNOS4X12_GPIO_D12, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4X12_GPIO_D13, S5P_GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + gpio_cfg_pin(EXYNOS4X12_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_A07, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + gpio_cfg_pin(EXYNOS4X12_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_A13, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + gpio_cfg_pin(EXYNOS4X12_GPIO_B2, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_B3, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + gpio_cfg_pin(EXYNOS4X12_GPIO_B6, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_B7, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + gpio_cfg_pin(EXYNOS4X12_GPIO_C13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS4X12_GPIO_C14, S5P_GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + gpio_cfg_pin(EXYNOS4X12_GPIO_D02, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_D03, S5P_GPIO_FUNC(0x3)); + break; + } +} + +static int exynos4x12_mmc_config(int peripheral, int flags) +{ + int i, start = 0, start_ext = 0; + + switch (peripheral) { + case PERIPH_ID_SDMMC0: + start = EXYNOS4X12_GPIO_K00; + start_ext = EXYNOS4X12_GPIO_K13; + break; + case PERIPH_ID_SDMMC2: + start = EXYNOS4X12_GPIO_K20; + start_ext = EXYNOS4X12_GPIO_K33; + break; + default: + return -1; } + for (i = start; i < (start + 7); i++) { + if (i == (start + 2)) + continue; + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); + } + if (flags & PINMUX_FLAG_8BIT_MODE) { + for (i = start_ext; i < (start_ext + 4); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); + } + } + + return 0; } + +static void exynos4x12_uart_config(int peripheral) +{ + int i, start, count; + + switch (peripheral) { + case PERIPH_ID_UART0: + start = EXYNOS4X12_GPIO_A00; + count = 4; + break; + case PERIPH_ID_UART1: + start = EXYNOS4X12_GPIO_A04; + count = 4; + break; + case PERIPH_ID_UART2: + start = EXYNOS4X12_GPIO_A10; + count = 4; + break; + case PERIPH_ID_UART3: + start = EXYNOS4X12_GPIO_A14; + count = 2; + break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return; + } + for (i = start; i < (start + count); i++) { + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + } +} + static int exynos4_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -736,6 +773,41 @@ static int exynos4_pinmux_config(int peripheral, int flags) return 0; } +static int exynos4x12_pinmux_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + exynos4x12_uart_config(peripheral); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + exynos4x12_i2c_config(peripheral, flags); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC2: + return exynos4x12_mmc_config(peripheral, flags); + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC3: + case PERIPH_ID_SDMMC4: + debug("SDMMC device %d not implemented\n", peripheral); + return -1; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + return 0; +} + int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) { @@ -744,11 +816,14 @@ int exynos_pinmux_config(int peripheral, int flags) else if (proid_is_exynos5250()) return exynos5_pinmux_config(peripheral, flags); } else if (cpu_is_exynos4()) { - return exynos4_pinmux_config(peripheral, flags); - } else { - debug("pinmux functionality not supported\n"); + if (proid_is_exynos4412()) + return exynos4x12_pinmux_config(peripheral, flags); + else + return exynos4_pinmux_config(peripheral, flags); } + debug("pinmux functionality not supported\n"); + return -1; } @@ -787,7 +862,7 @@ int pinmux_decode_periph_id(const void *blob, int node) return exynos5_pinmux_decode_periph_id(blob, node); else if (cpu_is_exynos4()) return exynos4_pinmux_decode_periph_id(blob, node); - else - return PERIPH_ID_NONE; + + return PERIPH_ID_NONE; } #endif diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 59f5352b2..5f5132f66 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -27,8 +27,4 @@ obj-y += boot-common.o obj-y += lowlevel_init.o endif -ifndef CONFIG_SPL_BUILD -ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) obj-y += mem-common.o -endif -endif diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 429c4becf..71c0cc8f2 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1384,8 +1384,10 @@ void sdram_init(void) if (sdram_type == EMIF_SDRAM_TYPE_DDR3 && (!in_sdram && !warm_reset())) { - do_bug0039_workaround(EMIF1_BASE); - do_bug0039_workaround(EMIF2_BASE); + if (emif1_enabled) + do_bug0039_workaround(EMIF1_BASE); + if (emif2_enabled) + do_bug0039_workaround(EMIF2_BASE); } debug("<<sdram_init()\n"); diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 8ebc0ce25..ba97d9ec5 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -185,7 +185,7 @@ u32 omap_sdram_size(void) { u32 section, i, valid; u64 sdram_start = 0, sdram_end = 0, addr, - size, total_size = 0, trap_size = 0; + size, total_size = 0, trap_size = 0, trap_start = 0; for (i = 0; i < 4; i++) { section = __raw_readl(DMM_BASE + i*4); @@ -194,8 +194,8 @@ u32 omap_sdram_size(void) addr = section & EMIF_SYS_ADDR_MASK; /* See if the address is valid */ - if ((addr >= DRAM_ADDR_SPACE_START) && - (addr < DRAM_ADDR_SPACE_END)) { + if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) && + (addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) { size = ((section & EMIF_SYS_SIZE_MASK) >> EMIF_SYS_SIZE_SHIFT); size = 1 << size; @@ -208,12 +208,15 @@ u32 omap_sdram_size(void) sdram_end = addr + size; } else { trap_size = size; + trap_start = addr; } - } - } - total_size = (sdram_end - sdram_start) - (trap_size); + + if ((trap_start >= sdram_start) && (trap_start < sdram_end)) + total_size = (sdram_end - sdram_start) - (trap_size); + else + total_size = sdram_end - sdram_start; return total_size; } diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c index afc1bc185..944ef840a 100644 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ b/arch/arm/cpu/armv7/omap-common/mem-common.c @@ -2,31 +2,136 @@ * (C) Copyright 2010 * Texas Instruments, <www.ti.com> * - * Steve Sakoman <steve@sakoman.com> + * Author : + * Mansoor Ahamed <mansoor.ahamed@ti.com> + * + * Initial Code from: + * Manikandan Pillai <mani.pillai@ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> * * SPDX-License-Identifier: GPL-2.0+ */ +#include <common.h> +#include <asm/io.h> #include <asm/arch/cpu.h> +#include <asm/arch/mem.h> #include <asm/arch/sys_proto.h> +#include <command.h> +#include <linux/mtd/omap_gpmc.h> struct gpmc *gpmc_cfg; +#if defined(CONFIG_OMAP34XX) +/******************************************************** + * mem_ok() - test used to see if timings are correct + * for a part. Helps in guessing which part + * we are currently using. + *******************************************************/ +u32 mem_ok(u32 cs) +{ + u32 val1, val2, addr; + u32 pattern = 0x12345678; + + addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs); + + writel(0x0, addr + 0x400); /* clear pos A */ + writel(pattern, addr); /* pattern to pos B */ + writel(0x0, addr + 4); /* remove pattern off the bus */ + val1 = readl(addr + 0x400); /* get pos A value */ + val2 = readl(addr); /* get val2 */ + writel(0x0, addr + 0x400); /* clear pos A */ + + if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */ + return 0; + else + return 1; +} +#endif + +void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, + u32 size) +{ + writel(0, &cs->config7); + sdelay(1000); + /* Delay for settling */ + writel(gpmc_config[0], &cs->config1); + writel(gpmc_config[1], &cs->config2); + writel(gpmc_config[2], &cs->config3); + writel(gpmc_config[3], &cs->config4); + writel(gpmc_config[4], &cs->config5); + writel(gpmc_config[5], &cs->config6); + /* Enable the config */ + writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | + (1 << 6)), &cs->config7); + sdelay(2000); +} + /***************************************************** * gpmc_init(): init gpmc bus + * Init GPMC for x16, MuxMode (SDRAM in x32). * This code can only be executed from SRAM or SDRAM. *****************************************************/ void gpmc_init(void) { + /* putting a blanket check on GPMC based on ZeBu for now */ gpmc_cfg = (struct gpmc *)GPMC_BASE; - +#if defined(CONFIG_NOR) +/* configure GPMC for NOR */ + const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, + STNOR_GPMC_CONFIG2, + STNOR_GPMC_CONFIG3, + STNOR_GPMC_CONFIG4, + STNOR_GPMC_CONFIG5, + STNOR_GPMC_CONFIG6, + STNOR_GPMC_CONFIG7 + }; + u32 size = GPMC_SIZE_16M; + u32 base = CONFIG_SYS_FLASH_BASE; +#elif defined(CONFIG_NAND) +/* configure GPMC for NAND */ + const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, + M_NAND_GPMC_CONFIG2, + M_NAND_GPMC_CONFIG3, + M_NAND_GPMC_CONFIG4, + M_NAND_GPMC_CONFIG5, + M_NAND_GPMC_CONFIG6, + 0 + }; + u32 size = GPMC_SIZE_256M; + u32 base = CONFIG_SYS_NAND_BASE; +#elif defined(CONFIG_CMD_ONENAND) + const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1, + ONENAND_GPMC_CONFIG2, + ONENAND_GPMC_CONFIG3, + ONENAND_GPMC_CONFIG4, + ONENAND_GPMC_CONFIG5, + ONENAND_GPMC_CONFIG6, + 0 + }; + u32 base = PISMO1_ONEN_BASE; + u32 size = PISMO1_ONEN_SIZE; +#else + const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 }; + u32 size = 0; + u32 base = 0; +#endif /* global settings */ - writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */ - writel(0, &gpmc_cfg->timeout_control);/* timeout disable */ - + writel(0x00000008, &gpmc_cfg->sysconfig); + writel(0x00000000, &gpmc_cfg->irqstatus); + writel(0x00000000, &gpmc_cfg->irqenable); + writel(0x00000000, &gpmc_cfg->timeout_control); +#ifdef CONFIG_NOR + writel(0x00000200, &gpmc_cfg->config); +#else + writel(0x00000012, &gpmc_cfg->config); +#endif /* * Disable the GPMC0 config set by ROM code - * It conflicts with our MPDB (both at 0x08000000) */ writel(0, &gpmc_cfg->cs[0].config7); + sdelay(1000); + /* enable chip-select specific configurations */ + enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); } diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index 39ff2575b..cf8604635 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -9,7 +9,6 @@ obj-y := lowlevel_init.o obj-y += board.o obj-y += clock.o -obj-y += mem.o obj-y += sys_info.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index ad971327b..4baca11d7 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -372,6 +372,38 @@ struct vcores_data dra752_volts = { .iva.pmic = &tps659038, }; +struct vcores_data dra722_volts = { + .mpu.value = 1000, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = 0x23, + .mpu.pmic = &tps659038, + + .eve.value = 1000, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = 0x2f, + .eve.pmic = &tps659038, + + .gpu.value = 1000, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = 0x2f, + .gpu.pmic = &tps659038, + + .core.value = 1000, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = 0x27, + .core.pmic = &tps659038, + + .iva.value = 1000, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = 0x2f, + .iva.pmic = &tps659038, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -558,6 +590,13 @@ void hw_data_init(void) *ctrl = &dra7xx_ctrl; break; + case DRA722_ES1_0: + *prcm = &dra7xx_prcm; + *dplls_data = &dra7xx_dplls; + *omap_vcores = &dra722_volts; + *ctrl = &dra7xx_ctrl; + break; + default: printf("\n INVALID OMAP REVISION "); } @@ -580,6 +619,7 @@ void get_ioregs(const struct ctrl_ioregs **regs) break; case DRA752_ES1_0: case DRA752_ES1_1: + case DRA722_ES1_0: *regs = &ioregs_dra7xx_es1; break; diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 93feb1623..a8a474a88 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -336,6 +336,9 @@ void init_omap_revision(void) case DRA752_CONTROL_ID_CODE_ES1_1: *omap_si_rev = DRA752_ES1_1; break; + case DRA722_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = DRA722_ES1_0; + break; default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; } diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 7292161f3..ff08ef424 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -447,10 +447,10 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_wkup_control_spare_r = 0x4AE0C5B4, .control_wkup_control_spare_r_c0 = 0x4AE0C5B8, .control_srcomp_east_side_wkup = 0x4AE0C5BC, - .control_efuse_1 = 0x4AE0C5C0, - .control_efuse_2 = 0x4AE0C5C4, - .control_efuse_3 = 0x4AE0C5C8, - .control_efuse_4 = 0x4AE0C5CC, + .control_efuse_1 = 0x4AE0C5C8, + .control_efuse_2 = 0x4AE0C5CC, + .control_efuse_3 = 0x4AE0C5D0, + .control_efuse_4 = 0x4AE0C5D4, .control_efuse_13 = 0x4AE0C5F0, }; diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 16a91f911..e2ebab826 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -229,6 +229,17 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { .is_ma_present = 0x1 }; +/* + * DRA722 EVM EMIF1 CONFIGURATION + */ +const struct dmm_lisa_map_regs lisa_map_2G_x_2 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80600100, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) { switch (omap_revision()) { @@ -255,6 +266,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) break; } break; + case DRA722_ES1_0: default: *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; } @@ -275,8 +287,11 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs break; case DRA752_ES1_0: case DRA752_ES1_1: - default: *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2; + break; + case DRA722_ES1_0: + default: + *dmm_lisa_regs = &lisa_map_2G_x_2; } } @@ -463,6 +478,7 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, break; case DRA752_ES1_0: case DRA752_ES1_1: + case DRA722_ES1_0: if (emif_nr == 1) { *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1; *size = @@ -630,6 +646,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations) break; case DRA752_ES1_0: case DRA752_ES1_1: + case DRA722_ES1_0: bug_00339_regs_ptr = dra_bug_00339_regs; *iterations = sizeof(dra_bug_00339_regs)/ sizeof(dra_bug_00339_regs[0]); diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile index 22219990d..fad004ca6 100644 --- a/arch/arm/cpu/armv7/rmobile/Makefile +++ b/arch/arm/cpu/armv7/rmobile/Makefile @@ -11,7 +11,7 @@ obj-y += emac.o obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o obj-$(CONFIG_GLOBAL_TIMER) += timer.o obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o -obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-r8a7790.o pfc-r8a7790.o -obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-r8a7791.o pfc-r8a7791.o +obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o +obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c deleted file mode 100644 index 2de58ed27..000000000 --- a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c - * - * Copyright (C) 2013 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0 - */ -#include <common.h> -#include <asm/io.h> - -#define PRR 0xFF000044 - -u32 rmobile_get_cpu_type(void) -{ - u32 product; - - product = readl(PRR); - - return (u32)((product & 0x00007F00) >> 8); -} - -u32 rmobile_get_cpu_rev_integer(void) -{ - u32 product; - - product = readl(PRR); - - return (u32)((product & 0x000000F0) >> 4); -} diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c b/arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c index 7232e2377..42ee30fbe 100644 --- a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c +++ b/arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c @@ -1,8 +1,7 @@ /* - * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c - * This file is r8a7790 processor support. + * arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c * - * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013,2014 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0 */ @@ -18,5 +17,10 @@ u32 rmobile_get_cpu_type(void) u32 rmobile_get_cpu_rev_integer(void) { - return (readl(PRR) & 0x000000F0) >> 4; + return ((readl(PRR) & 0x000000F0) >> 4) + 1; +} + +u32 rmobile_get_cpu_rev_fraction(void) +{ + return readl(PRR) & 0x0000000F; } diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c index 83d5282e3..7a7c97d79 100644 --- a/arch/arm/cpu/armv7/rmobile/cpu_info.c +++ b/arch/arm/cpu/armv7/rmobile/cpu_info.c @@ -44,35 +44,30 @@ static u32 __rmobile_get_cpu_rev_fraction(void) u32 rmobile_get_cpu_rev_fraction(void) __attribute__((weak, alias("__rmobile_get_cpu_rev_fraction"))); +/* CPU infomation table */ +static const struct { + u16 cpu_type; + u8 cpu_name[10]; +} rmobile_cpuinfo[] = { + { 0x37, "SH73A0" }, + { 0x40, "R8A7740" }, + { 0x45, "R8A7790" }, + { 0x47, "R8A7791" }, + { 0x0, "CPU" }, +}; + int print_cpuinfo(void) { - switch (rmobile_get_cpu_type()) { - case 0x37: - printf("CPU: Renesas Electronics SH73A0 rev %d.%d\n", - rmobile_get_cpu_rev_integer(), - rmobile_get_cpu_rev_fraction()); - break; - case 0x40: - printf("CPU: Renesas Electronics R8A7740 rev %d.%d\n", - rmobile_get_cpu_rev_integer(), - rmobile_get_cpu_rev_fraction()); - break; - - case 0x45: - printf("CPU: Renesas Electronics R8A7790 rev %d\n", - rmobile_get_cpu_rev_integer()); - break; - - case 0x47: - printf("CPU: Renesas Electronics R8A7791 rev %d\n", - rmobile_get_cpu_rev_integer()); - break; - - default: - printf("CPU: Renesas Electronics CPU rev %d.%d\n", - rmobile_get_cpu_rev_integer(), - rmobile_get_cpu_rev_fraction()); - break; + int i = 0; + u32 cpu_type = rmobile_get_cpu_type(); + for (; i < ARRAY_SIZE(rmobile_cpuinfo); i++) { + if (rmobile_cpuinfo[i].cpu_type == cpu_type) { + printf("CPU: Renesas Electronics %s rev %d.%d\n", + rmobile_cpuinfo[i].cpu_name, + rmobile_get_cpu_rev_integer(), + rmobile_get_cpu_rev_fraction()); + break; + } } return 0; } diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S index e07cc8093..287f8d74a 100644 --- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S @@ -2,7 +2,7 @@ * arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S * This file is lager low level initialize. * - * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013, 2014 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0 */ @@ -36,16 +36,32 @@ do_cpu_waiting: .align 4 do_lowlevel_init: /* surpress wfe if ca15 */ - tst r4, #4 + tst r4, #4 mrceq p15, 0, r0, c1, c0, 1 /* actlr */ orreq r0, r0, #(1<<7) mcreq p15, 0, r0, c1, c0, 1 + /* and set l2 latency */ mrceq p15, 1, r0, c9, c0, 2 /* l2ctlr */ orreq r0, r0, #0x00000800 orreq r0, r0, #0x00000003 mcreq p15, 1, r0, c9, c0, 2 + mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */ + and r0, r0, #0xf00 + lsr r0, r0, #8 + tst r0, #1 /* only need for cluster 0 */ + bne _exit_init_l2_a15 + + mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */ + and r1, r0, #7 + cmp r1, #3 /* has already been set up */ + bicne r0, r0, #0xe7 + orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */ + orrne r0, r0, #0x20 /* L2CTLR[5] */ + mcrne p15, 1, r0, c9, c0, 2 + +_exit_init_l2_a15: ldr r3, =(CONFIG_SYS_INIT_SP_ADDR) sub sp, r3, #4 str lr, [sp] diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c index f49f990a0..46d6e60c1 100644 --- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c @@ -913,7 +913,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_SCIF3 [2] */ FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, /* SEL_IEB [2] */ - FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, /* SEL_MMC [1] */ FN_SEL_MMC_0, FN_SEL_MMC_1, /* SEL_SCIF5 [1] */ diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S index 1caaa2759..2f2e9fcc7 100644 --- a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S +++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S @@ -10,20 +10,7 @@ /* Save the parameter pass in by previous boot loader */ .global save_boot_params save_boot_params: - /* save the parameter here */ - - /* - * Setup stack for exception, which is located - * at the end of on-chip RAM. We don't expect exception prior to - * relocation and if that happens, we won't worry -- it will overide - * global data region as the code will goto reset. After relocation, - * this region won't be used by other part of program. - * Hence it is safe. - */ - ldr r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) - ldr r1, =IRQ_STACK_START_IN - str r0, [r1] - + /* no parameter to save */ bx lr diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 27be451a8..fedd7c8f7 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -19,46 +19,6 @@ #include <asm/system.h> #include <linux/linkage.h> -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq -#ifdef CONFIG_SPL_BUILD -_undefined_instruction: .word _undefined_instruction -_software_interrupt: .word _software_interrupt -_prefetch_abort: .word _prefetch_abort -_data_abort: .word _data_abort -_not_used: .word _not_used -_irq: .word _irq -_fiq: .word _fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#else -.globl _undefined_instruction -_undefined_instruction: .word undefined_instruction -.globl _software_interrupt -_software_interrupt: .word software_interrupt -.globl _prefetch_abort -_prefetch_abort: .word prefetch_abort -.globl _data_abort -_data_abort: .word data_abort -.globl _not_used -_not_used: .word not_used -.globl _irq -_irq: .word irq -.globl _fiq -_fiq: .word fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#endif /* CONFIG_SPL_BUILD */ - -.global _end_vect -_end_vect: - - .balignl 16,0xdeadbeef /************************************************************************* * * Startup Code (reset vector) @@ -70,26 +30,7 @@ _end_vect: * *************************************************************************/ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: bl save_boot_params @@ -250,195 +191,3 @@ ENTRY(cpu_init_crit) b lowlevel_init @ go setup pll,mux,memory ENDPROC(cpu_init_crit) #endif - -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current - @ user stack - stmia sp, {r0 - r12} @ Save user registers (now in - @ svc mode) r0-r12 - ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort - @ stack - ldmia r2, {r2 - r3} @ get values for "aborted" pc - @ and cpsr (into parm regs) - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 - @ (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! - @ a reserved stack spot would - @ be good. - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into - @ cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter - @ in banked mode) - - str lr, [r13] @ save caller lr in position 0 - @ of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of - @ saved stack - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure - @ moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & - @ switch modes. - .endm - - .macro get_bad_stack_swi - sub r13, r13, #4 @ space on current stack for - @ scratch reg. - str r0, [r13] @ save R0's value. - ldr r0, IRQ_STACK_START_IN @ get data regions start - @ spots for abort stack - str lr, [r0] @ save caller lr in position 0 - @ of saved stack - mrs lr, spsr @ get the spsr - str lr, [r0, #4] @ save spsr in position 1 of - @ saved stack - ldr lr, [r0] @ restore lr - ldr r0, [r13] @ restore r0 - add r13, r13, #4 @ pop stack entry - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effective fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif /* CONFIG_USE_IRQ */ -#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile new file mode 100644 index 000000000..a64bfa18e --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -0,0 +1,25 @@ +# +# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net> +# +# Based on some other Makefile +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y += timer.o +obj-y += board.o +obj-y += clock.o +obj-y += pinmux.o +obj-$(CONFIG_SUN7I) += clock_sun4i.o + +ifndef CONFIG_SPL_BUILD +obj-y += cpu_info.o +endif + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SUN7I) += dram.o +ifdef CONFIG_SPL_FEL +obj-y += start.o +endif +endif diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c new file mode 100644 index 000000000..49c94489e --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -0,0 +1,111 @@ +/* + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net> + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * Some init for sunxi platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <netdev.h> +#include <miiphy.h> +#include <serial.h> +#ifdef CONFIG_SPL_BUILD +#include <spl.h> +#endif +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/timer.h> + +#ifdef CONFIG_SPL_BUILD +/* Pointer to the global data structure for SPL */ +DECLARE_GLOBAL_DATA_PTR; + +/* The sunxi internal brom will try to loader external bootloader + * from mmc0, nand flash, mmc2. + * Unfortunately we can't check how SPL was loaded so assume + * it's always the first SD/MMC controller + */ +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +/* No confirmation data available in SPL yet. Hardcode bootmode */ +u32 spl_boot_mode(void) +{ + return MMCSD_MODE_RAW; +} +#endif + +int gpio_init(void) +{ + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX); + sunxi_gpio_set_pull(SUNXI_GPB(23), 1); + + return 0; +} + +void reset_cpu(ulong addr) +{ +} + +/* do some early init */ +void s_init(void) +{ +#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I) + /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ + asm volatile( + "mrc p15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #1 << 6\n" + "mcr p15, 0, r0, c1, c0, 1\n"); +#endif + + clock_init(); + timer_init(); + gpio_init(); + +#ifdef CONFIG_SPL_BUILD + gd = &gdata; + preloader_console_init(); + + sunxi_board_init(); +#endif +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif + +#ifdef CONFIG_CMD_NET +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +int cpu_eth_init(bd_t *bis) +{ + int rc; + +#ifdef CONFIG_SUNXI_GMAC + rc = sunxi_gmac_initialize(bis); + if (rc < 0) { + printf("sunxi: failed to initialize gmac\n"); + return rc; + } +#endif + + return 0; +} +#endif diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c new file mode 100644 index 000000000..47fb70ff7 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/clock.c @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sys_proto.h> + +int clock_init(void) +{ +#ifdef CONFIG_SPL_BUILD + clock_init_safe(); +#endif + clock_init_uart(); + + return 0; +} diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c new file mode 100644 index 000000000..5a7da3c6b --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -0,0 +1,188 @@ +/* + * sun4i, sun5i and sun7i specific clock code + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sys_proto.h> + +#ifdef CONFIG_SPL_BUILD +void clock_init_safe(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* Set safe defaults until PMU is configured */ + writel(AXI_DIV_1 << AXI_DIV_SHIFT | + AHB_DIV_2 << AHB_DIV_SHIFT | + APB0_DIV_1 << APB0_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); + writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); + sdelay(200); + writel(AXI_DIV_1 << AXI_DIV_SHIFT | + AHB_DIV_2 << AHB_DIV_SHIFT | + APB0_DIV_1 << APB0_DIV_SHIFT | + CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); +#ifdef CONFIG_SUN7I + writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0), + &ccm->ahb_gate0); +#endif + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); +} +#endif + +void clock_init_uart(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* uart clock source is apb1 */ + writel(APB1_CLK_SRC_OSC24M| + APB1_CLK_RATE_N_1| + APB1_CLK_RATE_M(1), + &ccm->apb1_clk_div_cfg); + + /* open the clock for uart */ + setbits_le32(&ccm->apb1_gate, + CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX-1)); +} + +int clock_twi_onoff(int port, int state) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (port > 2) + return -1; + + /* set the apb clock gate for twi */ + if (state) + setbits_le32(&ccm->apb1_gate, + CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port)); + else + clrbits_le32(&ccm->apb1_gate, + CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port)); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \ + 0 << CCM_PLL1_CFG_VCO_RST_SHIFT | \ + 8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \ + 0 << CCM_PLL1_CFG_PLL4_EXCH_SHIFT | \ + 16 << CCM_PLL1_CFG_BIAS_CUR_SHIFT | \ + (P)<< CCM_PLL1_CFG_DIVP_SHIFT | \ + 2 << CCM_PLL1_CFG_LCK_TMR_SHIFT | \ + (N)<< CCM_PLL1_CFG_FACTOR_N_SHIFT | \ + (K)<< CCM_PLL1_CFG_FACTOR_K_SHIFT | \ + 0 << CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT | \ + 0 << CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT | \ + (M)<< CCM_PLL1_CFG_FACTOR_M_SHIFT) + +static struct { + u32 pll1_cfg; + unsigned int freq; +} pll1_para[] = { + /* This array must be ordered by frequency. */ + { PLL1_CFG(16, 0, 0, 0), 384000000 }, + { PLL1_CFG(16, 1, 0, 0), 768000000 }, + { PLL1_CFG(20, 1, 0, 0), 960000000 }, + { PLL1_CFG(21, 1, 0, 0), 1008000000}, + { PLL1_CFG(22, 1, 0, 0), 1056000000}, + { PLL1_CFG(23, 1, 0, 0), 1104000000}, + { PLL1_CFG(24, 1, 0, 0), 1152000000}, + { PLL1_CFG(25, 1, 0, 0), 1200000000}, + { PLL1_CFG(26, 1, 0, 0), 1248000000}, + { PLL1_CFG(27, 1, 0, 0), 1296000000}, + { PLL1_CFG(28, 1, 0, 0), 1344000000}, + { PLL1_CFG(29, 1, 0, 0), 1392000000}, + { PLL1_CFG(30, 1, 0, 0), 1440000000}, + { PLL1_CFG(31, 1, 0, 0), 1488000000}, + /* Final catchall entry */ + { PLL1_CFG(31, 1, 0, 0), ~0}, +}; + +void clock_set_pll1(unsigned int hz) +{ + int i = 0; + int axi, ahb, apb0; + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* Find target frequency */ + while (pll1_para[i].freq < hz) + i++; + + hz = pll1_para[i].freq; + + /* Calculate system clock divisors */ + axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ + ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */ + apb0 = 2; /* Max 150MHz */ + + printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0); + + /* Map divisors to register values */ + axi = axi - 1; + if (ahb > 4) + ahb = 3; + else if (ahb > 2) + ahb = 2; + else if (ahb > 1) + ahb = 1; + else + ahb = 0; + + apb0 = apb0 - 1; + + /* Switch to 24MHz clock while changing PLL1 */ + writel(AXI_DIV_1 << AXI_DIV_SHIFT | + AHB_DIV_2 << AHB_DIV_SHIFT | + APB0_DIV_1 << APB0_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); + sdelay(20); + + /* Configure sys clock divisors */ + writel(axi << AXI_DIV_SHIFT | + ahb << AHB_DIV_SHIFT | + apb0 << APB0_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); + + /* Configure PLL1 at the desired frequency */ + writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg); + sdelay(200); + + /* Switch CPU to PLL1 */ + writel(axi << AXI_DIV_SHIFT | + ahb << AHB_DIV_SHIFT | + apb0 << APB0_DIV_SHIFT | + CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); + sdelay(20); +} +#endif + +unsigned int clock_get_pll6(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll6_cfg); + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); + int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; + return 24000000 * n * k / 2; +} diff --git a/arch/arm/cpu/armv7/sunxi/config.mk b/arch/arm/cpu/armv7/sunxi/config.mk new file mode 100644 index 000000000..00f5ffc68 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/config.mk @@ -0,0 +1,8 @@ +# Build a combined spl + u-boot image +ifdef CONFIG_SPL +ifndef CONFIG_SPL_BUILD +ifndef CONFIG_SPL_FEL +ALL-y += u-boot-sunxi-with-spl.bin +endif +endif +endif diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c new file mode 100644 index 000000000..b4c3d5c6d --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -0,0 +1,19 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + puts("CPU: Allwinner A20 (SUN7I)\n"); + return 0; +} +#endif diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c new file mode 100644 index 000000000..b43c4b41d --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/dram.c @@ -0,0 +1,593 @@ +/* + * sunxi DRAM controller initialization + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net> + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> + * + * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c + * and earlier U-Boot Allwiner A10 SPL work + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Berg Xing <bergxing@allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Unfortunately the only documentation we have on the sun7i DRAM + * controller is Allwinner boot0 + boot1 code, and that code uses + * magic numbers & shifts with no explanations. Hence this code is + * rather undocumented and full of magic. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/dram.h> +#include <asm/arch/timer.h> +#include <asm/arch/sys_proto.h> + +#define CPU_CFG_CHIP_VER(n) ((n) << 6) +#define CPU_CFG_CHIP_VER_MASK CPU_CFG_CHIP_VER(0x3) +#define CPU_CFG_CHIP_REV_A 0x0 +#define CPU_CFG_CHIP_REV_C1 0x1 +#define CPU_CFG_CHIP_REV_C2 0x2 +#define CPU_CFG_CHIP_REV_B 0x3 + +/* + * Wait up to 1s for mask to be clear in given reg. + */ +static void await_completion(u32 *reg, u32 mask) +{ + unsigned long tmo = timer_get_us() + 1000000; + + while (readl(reg) & mask) { + if (timer_get_us() > tmo) + panic("Timeout initialising DRAM\n"); + } +} + +static void mctl_ddr3_reset(void) +{ + struct sunxi_dram_reg *dram = + (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + clrbits_le32(&dram->mcr, DRAM_MCR_RESET); + udelay(2); + setbits_le32(&dram->mcr, DRAM_MCR_RESET); +} + +static void mctl_set_drive(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28), + DRAM_MCR_MODE_EN(0x3) | + 0xffc); +} + +static void mctl_itm_disable(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF); +} + +static void mctl_itm_enable(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF); +} + +static void mctl_enable_dll0(u32 phase) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + clrsetbits_le32(&dram->dllcr[0], 0x3f << 6, + ((phase >> 16) & 0x3f) << 6); + clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE); + udelay(2); + + clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE); + udelay(22); + + clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET); + udelay(22); +} + +/* + * Note: This differs from pm/standby in that it checks the bus width + */ +static void mctl_enable_dllx(u32 phase) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 i, n, bus_width; + + bus_width = readl(&dram->dcr); + + if ((bus_width & DRAM_DCR_BUS_WIDTH_MASK) == + DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT)) + n = DRAM_DCR_NR_DLLCR_32BIT; + else + n = DRAM_DCR_NR_DLLCR_16BIT; + + for (i = 1; i < n; i++) { + clrsetbits_le32(&dram->dllcr[i], 0xf << 14, + (phase & 0xf) << 14); + clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET, + DRAM_DLLCR_DISABLE); + phase >>= 4; + } + udelay(2); + + for (i = 1; i < n; i++) + clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET | + DRAM_DLLCR_DISABLE); + udelay(22); + + for (i = 1; i < n; i++) + clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE, + DRAM_DLLCR_NRESET); + udelay(22); +} + +static u32 hpcr_value[32] = { +#ifdef CONFIG_SUN7I + 0x0301, 0x0301, 0x0301, 0x0301, + 0x0301, 0x0301, 0x0301, 0x0301, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x1031, 0x1031, 0x0735, 0x1035, + 0x1035, 0x0731, 0x1031, 0x0735, + 0x1035, 0x1031, 0x0731, 0x1035, + 0x0001, 0x1031, 0, 0x1031 + /* last row differs from boot0 source table + * 0x1031, 0x0301, 0x0301, 0x0731 + * but boot0 code skips #28 and #30, and sets #29 and #31 to the + * value from #28 entry (0x1031) + */ +#endif +}; + +static void mctl_configure_hostport(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 i; + + for (i = 0; i < 32; i++) + writel(hpcr_value[i], &dram->hpcr[i]); +} + +static void mctl_setup_dram_clock(u32 clk) +{ + u32 reg_val; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* setup DRAM PLL */ + reg_val = readl(&ccm->pll5_cfg); + reg_val &= ~CCM_PLL5_CTRL_M_MASK; /* set M to 0 (x1) */ + reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */ + reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */ + reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */ + if (clk >= 540 && clk < 552) { + /* dram = 540MHz, pll5p = 540MHz */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); + reg_val |= CCM_PLL5_CTRL_P(1); + } else if (clk >= 512 && clk < 528) { + /* dram = 512MHz, pll5p = 384MHz */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); + reg_val |= CCM_PLL5_CTRL_P(2); + } else if (clk >= 496 && clk < 504) { + /* dram = 496MHz, pll5p = 372MHz */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); + reg_val |= CCM_PLL5_CTRL_P(2); + } else if (clk >= 468 && clk < 480) { + /* dram = 468MHz, pll5p = 468MHz */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); + reg_val |= CCM_PLL5_CTRL_P(1); + } else if (clk >= 396 && clk < 408) { + /* dram = 396MHz, pll5p = 396MHz */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); + reg_val |= CCM_PLL5_CTRL_P(1); + } else { + /* any other frequency that is a multiple of 24 */ + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2)); + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24)); + reg_val |= CCM_PLL5_CTRL_P(CCM_PLL5_CTRL_P_X(2)); + } + reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN; /* PLL VCO Gain off */ + reg_val |= CCM_PLL5_CTRL_EN; /* PLL On */ + writel(reg_val, &ccm->pll5_cfg); + udelay(5500); + + setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK); + +#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I) + /* reset GPS */ + clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE); + setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); + udelay(1); + clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); +#endif + + /* setup MBUS clock */ + reg_val = CCM_MBUS_CTRL_GATE | + CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) | + CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) | + CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2)); + writel(reg_val, &ccm->mbus_clk_cfg); + + /* + * open DRAMC AHB & DLL register clock + * close it first + */ + clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); + udelay(22); + + /* then open it */ + setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); + udelay(22); +} + +static int dramc_scan_readpipe(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 reg_val; + + /* data training trigger */ +#ifdef CONFIG_SUN7I + clrbits_le32(&dram->csr, DRAM_CSR_FAILED); +#endif + setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING); + + /* check whether data training process has completed */ + await_completion(&dram->ccr, DRAM_CCR_DATA_TRAINING); + + /* check data training result */ + reg_val = readl(&dram->csr); + if (reg_val & DRAM_CSR_FAILED) + return -1; + + return 0; +} + +static int dramc_scan_dll_para(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + const u32 dqs_dly[7] = {0x3, 0x2, 0x1, 0x0, 0xe, 0xd, 0xc}; + const u32 clk_dly[15] = {0x07, 0x06, 0x05, 0x04, 0x03, + 0x02, 0x01, 0x00, 0x08, 0x10, + 0x18, 0x20, 0x28, 0x30, 0x38}; + u32 clk_dqs_count[15]; + u32 dqs_i, clk_i, cr_i; + u32 max_val, min_val; + u32 dqs_index, clk_index; + + /* Find DQS_DLY Pass Count for every CLK_DLY */ + for (clk_i = 0; clk_i < 15; clk_i++) { + clk_dqs_count[clk_i] = 0; + clrsetbits_le32(&dram->dllcr[0], 0x3f << 6, + (clk_dly[clk_i] & 0x3f) << 6); + for (dqs_i = 0; dqs_i < 7; dqs_i++) { + for (cr_i = 1; cr_i < 5; cr_i++) { + clrsetbits_le32(&dram->dllcr[cr_i], + 0x4f << 14, + (dqs_dly[dqs_i] & 0x4f) << 14); + } + udelay(2); + if (dramc_scan_readpipe() == 0) + clk_dqs_count[clk_i]++; + } + } + /* Test DQS_DLY Pass Count for every CLK_DLY from up to down */ + for (dqs_i = 15; dqs_i > 0; dqs_i--) { + max_val = 15; + min_val = 15; + for (clk_i = 0; clk_i < 15; clk_i++) { + if (clk_dqs_count[clk_i] == dqs_i) { + max_val = clk_i; + if (min_val == 15) + min_val = clk_i; + } + } + if (max_val < 15) + break; + } + + /* Check if Find a CLK_DLY failed */ + if (!dqs_i) + goto fail; + + /* Find the middle index of CLK_DLY */ + clk_index = (max_val + min_val) >> 1; + if ((max_val == (15 - 1)) && (min_val > 0)) + /* if CLK_DLY[MCTL_CLK_DLY_COUNT] is very good, then the middle + * value can be more close to the max_val + */ + clk_index = (15 + clk_index) >> 1; + else if ((max_val < (15 - 1)) && (min_val == 0)) + /* if CLK_DLY[0] is very good, then the middle value can be more + * close to the min_val + */ + clk_index >>= 1; + if (clk_dqs_count[clk_index] < dqs_i) + clk_index = min_val; + + /* Find the middle index of DQS_DLY for the CLK_DLY got above, and Scan + * read pipe again + */ + clrsetbits_le32(&dram->dllcr[0], 0x3f << 6, + (clk_dly[clk_index] & 0x3f) << 6); + max_val = 7; + min_val = 7; + for (dqs_i = 0; dqs_i < 7; dqs_i++) { + clk_dqs_count[dqs_i] = 0; + for (cr_i = 1; cr_i < 5; cr_i++) { + clrsetbits_le32(&dram->dllcr[cr_i], + 0x4f << 14, + (dqs_dly[dqs_i] & 0x4f) << 14); + } + udelay(2); + if (dramc_scan_readpipe() == 0) { + clk_dqs_count[dqs_i] = 1; + max_val = dqs_i; + if (min_val == 7) + min_val = dqs_i; + } + } + + if (max_val < 7) { + dqs_index = (max_val + min_val) >> 1; + if ((max_val == (7-1)) && (min_val > 0)) + dqs_index = (7 + dqs_index) >> 1; + else if ((max_val < (7-1)) && (min_val == 0)) + dqs_index >>= 1; + if (!clk_dqs_count[dqs_index]) + dqs_index = min_val; + for (cr_i = 1; cr_i < 5; cr_i++) { + clrsetbits_le32(&dram->dllcr[cr_i], + 0x4f << 14, + (dqs_dly[dqs_index] & 0x4f) << 14); + } + udelay(2); + return dramc_scan_readpipe(); + } + +fail: + clrbits_le32(&dram->dllcr[0], 0x3f << 6); + for (cr_i = 1; cr_i < 5; cr_i++) + clrbits_le32(&dram->dllcr[cr_i], 0x4f << 14); + udelay(2); + + return dramc_scan_readpipe(); +} + +static void dramc_clock_output_en(u32 on) +{ +#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + if (on) + setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); + else + clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); +#endif +} + +static const u16 tRFC_table[2][6] = { + /* 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb */ + /* DDR2 75ns 105ns 127.5ns 195ns 327.5ns invalid */ + { 77, 108, 131, 200, 336, 336 }, + /* DDR3 invalid 90ns 110ns 160ns 300ns 350ns */ + { 93, 93, 113, 164, 308, 359 } +}; + +static void dramc_set_autorefresh_cycle(u32 clk, u32 type, u32 density) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 tRFC, tREFI; + + tRFC = (tRFC_table[type][density] * clk + 1023) >> 10; + tREFI = (7987 * clk) >> 10; /* <= 7.8us */ + + writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr); +} + +unsigned long dramc_init(struct dram_para *para) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 reg_val; + u32 density; + int ret_val; + + /* check input dram parameter structure */ + if (!para) + return 0; + + /* setup DRAM relative clock */ + mctl_setup_dram_clock(para->clock); + + /* reset external DRAM */ + mctl_set_drive(); + + /* dram clock off */ + dramc_clock_output_en(0); + + mctl_itm_disable(); + mctl_enable_dll0(para->tpr3); + + /* configure external DRAM */ + reg_val = 0x0; + if (para->type == DRAM_MEMORY_TYPE_DDR3) + reg_val |= DRAM_DCR_TYPE_DDR3; + reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3); + + if (para->density == 256) + density = DRAM_DCR_CHIP_DENSITY_256M; + else if (para->density == 512) + density = DRAM_DCR_CHIP_DENSITY_512M; + else if (para->density == 1024) + density = DRAM_DCR_CHIP_DENSITY_1024M; + else if (para->density == 2048) + density = DRAM_DCR_CHIP_DENSITY_2048M; + else if (para->density == 4096) + density = DRAM_DCR_CHIP_DENSITY_4096M; + else if (para->density == 8192) + density = DRAM_DCR_CHIP_DENSITY_8192M; + else + density = DRAM_DCR_CHIP_DENSITY_256M; + + reg_val |= DRAM_DCR_CHIP_DENSITY(density); + reg_val |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1); + reg_val |= DRAM_DCR_RANK_SEL(para->rank_num - 1); + reg_val |= DRAM_DCR_CMD_RANK_ALL; + reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE); + writel(reg_val, &dram->dcr); + +#ifdef CONFIG_SUN7I + setbits_le32(&dram->zqcr1, (0x1 << 24) | (0x1 << 1)); + if (para->tpr4 & 0x2) + clrsetbits_le32(&dram->zqcr1, (0x1 << 24), (0x1 << 1)); + dramc_clock_output_en(1); +#endif + +#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)) + /* set odt impendance divide ratio */ + reg_val = ((para->zq) >> 8) & 0xfffff; + reg_val |= ((para->zq) & 0xff) << 20; + reg_val |= (para->zq) & 0xf0000000; + writel(reg_val, &dram->zqcr0); +#endif + +#ifdef CONFIG_SUN7I + /* Set CKE Delay to about 1ms */ + setbits_le32(&dram->idcr, 0x1ffff); +#endif + +#ifdef CONFIG_SUN7I + if ((readl(&dram->ppwrsctl) & 0x1) != 0x1) + mctl_ddr3_reset(); + else + setbits_le32(&dram->mcr, DRAM_MCR_RESET); +#endif + + udelay(1); + + await_completion(&dram->ccr, DRAM_CCR_INIT); + + mctl_enable_dllx(para->tpr3); + + /* set refresh period */ + dramc_set_autorefresh_cycle(para->clock, para->type - 2, density); + + /* set timing parameters */ + writel(para->tpr0, &dram->tpr0); + writel(para->tpr1, &dram->tpr1); + writel(para->tpr2, &dram->tpr2); + + if (para->type == DRAM_MEMORY_TYPE_DDR3) { + reg_val = DRAM_MR_BURST_LENGTH(0x0); +#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)) + reg_val |= DRAM_MR_POWER_DOWN; +#endif + reg_val |= DRAM_MR_CAS_LAT(para->cas - 4); + reg_val |= DRAM_MR_WRITE_RECOVERY(0x5); + } else if (para->type == DRAM_MEMORY_TYPE_DDR2) { + reg_val = DRAM_MR_BURST_LENGTH(0x2); + reg_val |= DRAM_MR_CAS_LAT(para->cas); + reg_val |= DRAM_MR_WRITE_RECOVERY(0x5); + } + writel(reg_val, &dram->mr); + + writel(para->emr1, &dram->emr); + writel(para->emr2, &dram->emr2); + writel(para->emr3, &dram->emr3); + + /* set DQS window mode */ + clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE); + +#ifdef CONFIG_SUN7I + /* Command rate timing mode 2T & 1T */ + if (para->tpr4 & 0x1) + setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T); +#endif + /* reset external DRAM */ + setbits_le32(&dram->ccr, DRAM_CCR_INIT); + await_completion(&dram->ccr, DRAM_CCR_INIT); + +#ifdef CONFIG_SUN7I + /* setup zq calibration manual */ + reg_val = readl(&dram->ppwrsctl); + if ((reg_val & 0x1) == 1) { + /* super_standby_flag = 1 */ + + reg_val = readl(0x01c20c00 + 0x120); /* rtc */ + reg_val &= 0x000fffff; + reg_val |= 0x17b00000; + writel(reg_val, &dram->zqcr0); + + /* exit self-refresh state */ + clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27); + /* check whether command has been executed */ + await_completion(&dram->dcr, 0x1 << 31); + + udelay(2); + + /* dram pad hold off */ + setbits_le32(&dram->ppwrsctl, 0x16510000); + + await_completion(&dram->ppwrsctl, 0x1); + + /* exit self-refresh state */ + clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27); + + /* check whether command has been executed */ + await_completion(&dram->dcr, 0x1 << 31); + + udelay(2); + + /* issue a refresh command */ + clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x13 << 27); + await_completion(&dram->dcr, 0x1 << 31); + + udelay(2); + } +#endif + + /* scan read pipe value */ + mctl_itm_enable(); + if (para->tpr3 & (0x1 << 31)) { + ret_val = dramc_scan_dll_para(); + if (ret_val == 0) + para->tpr3 = + (((readl(&dram->dllcr[0]) >> 6) & 0x3f) << 16) | + (((readl(&dram->dllcr[1]) >> 14) & 0xf) << 0) | + (((readl(&dram->dllcr[2]) >> 14) & 0xf) << 4) | + (((readl(&dram->dllcr[3]) >> 14) & 0xf) << 8) | + (((readl(&dram->dllcr[4]) >> 14) & 0xf) << 12 + ); + } else { + ret_val = dramc_scan_readpipe(); + } + + if (ret_val < 0) + return 0; + + /* configure all host port */ + mctl_configure_hostport(); + + return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); +} diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c b/arch/arm/cpu/armv7/sunxi/pinmux.c new file mode 100644 index 000000000..1f2843fca --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/pinmux.c @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> + +int sunxi_gpio_set_cfgpin(u32 pin, u32 val) +{ + u32 bank = GPIO_BANK(pin); + u32 index = GPIO_CFG_INDEX(pin); + u32 offset = GPIO_CFG_OFFSET(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset); + + return 0; +} + +int sunxi_gpio_get_cfgpin(u32 pin) +{ + u32 cfg; + u32 bank = GPIO_BANK(pin); + u32 index = GPIO_CFG_INDEX(pin); + u32 offset = GPIO_CFG_OFFSET(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + cfg = readl(&pio->cfg[0] + index); + cfg >>= offset; + + return cfg & 0xf; +} + +int sunxi_gpio_set_drv(u32 pin, u32 val) +{ + u32 bank = GPIO_BANK(pin); + u32 index = GPIO_DRV_INDEX(pin); + u32 offset = GPIO_DRV_OFFSET(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset); + + return 0; +} + +int sunxi_gpio_set_pull(u32 pin, u32 val) +{ + u32 bank = GPIO_BANK(pin); + u32 index = GPIO_PULL_INDEX(pin); + u32 offset = GPIO_PULL_OFFSET(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset); + + return 0; +} diff --git a/arch/arm/cpu/armv7/sunxi/start.c b/arch/arm/cpu/armv7/sunxi/start.c new file mode 100644 index 000000000..6b392fa83 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/start.c @@ -0,0 +1 @@ +/* Intentionally empty. Only needed to get FEL SPL link line right */ diff --git a/arch/arm/cpu/armv7/sunxi/timer.c b/arch/arm/cpu/armv7/sunxi/timer.c new file mode 100644 index 000000000..36263896d --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/timer.c @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/timer.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define TIMER_MODE (0x0 << 7) /* continuous mode */ +#define TIMER_DIV (0x0 << 4) /* pre scale 1 */ +#define TIMER_SRC (0x1 << 2) /* osc24m */ +#define TIMER_RELOAD (0x1 << 1) /* reload internal value */ +#define TIMER_EN (0x1 << 0) /* enable timer */ + +#define TIMER_CLOCK (24 * 1000 * 1000) +#define COUNT_TO_USEC(x) ((x) / 24) +#define USEC_TO_COUNT(x) ((x) * 24) +#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) +#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ) + +#define TIMER_LOAD_VAL 0xffffffff + +#define TIMER_NUM 0 /* we use timer 0 */ + +/* read the 32-bit timer */ +static ulong read_timer(void) +{ + struct sunxi_timer_reg *timers = + (struct sunxi_timer_reg *)SUNXI_TIMER_BASE; + struct sunxi_timer *timer = &timers->timer[TIMER_NUM]; + + /* + * The hardware timer counts down, therefore we invert to + * produce an incrementing timer. + */ + return ~readl(&timer->val); +} + +/* init timer register */ +int timer_init(void) +{ + struct sunxi_timer_reg *timers = + (struct sunxi_timer_reg *)SUNXI_TIMER_BASE; + struct sunxi_timer *timer = &timers->timer[TIMER_NUM]; + writel(TIMER_LOAD_VAL, &timer->inter); + writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN, + &timer->ctl); + + return 0; +} + +/* timer without interrupts */ +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +ulong get_timer_masked(void) +{ + /* current tick value */ + ulong now = TICKS_TO_HZ(read_timer()); + + if (now >= gd->arch.lastinc) /* normal (non rollover) */ + gd->arch.tbl += (now - gd->arch.lastinc); + else { + /* rollover */ + gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) + - gd->arch.lastinc) + now; + } + gd->arch.lastinc = now; + + return gd->arch.tbl; +} + +/* delay x useconds */ +void __udelay(unsigned long usec) +{ + long tmo = USEC_TO_COUNT(usec); + ulong now, last = read_timer(); + + while (tmo > 0) { + now = read_timer(); + if (now > last) /* normal (non rollover) */ + tmo -= now - last; + else /* rollover */ + tmo -= TIMER_LOAD_VAL - last + now; + last = now; + } +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds new file mode 100644 index 000000000..364e35c32 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2013 + * Henrik Nordstrom <henrik@henriknordstrom.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(s_init) +SECTIONS +{ + . = 0x00002000; + + . = ALIGN(4); + .text : + { + *(.text.s_init) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + . = .; + + . = ALIGN(4); + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + . = ALIGN(4); + .note.gnu.build-id : + { + *(.note.gnu.build-id) + } + _end = .; + + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } + /DISCARD/ : { *(.note*) } +} diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds new file mode 100644 index 000000000..5008028aa --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * Based on omap-common/u-boot-spl.lds: + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Aneesh V <aneesh@ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + arch/arm/cpu/armv7/start.o (.text) + *(.text*) + } > .sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + __image_copy_end = .; + _end = .; + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } > .sdram +} diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index 7626b5c1a..816d0c5da 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -14,6 +14,9 @@ void lowlevel_init(void) { } +#define ZYNQ_SILICON_VER_MASK 0xF0000000 +#define ZYNQ_SILICON_VER_SHIFT 28 + int arch_cpu_init(void) { zynq_slcr_unlock(); @@ -42,6 +45,16 @@ int arch_cpu_init(void) return 0; } +unsigned int zynq_get_silicon_version(void) +{ + unsigned int ver; + + ver = (readl(&devcfg_base->mctrl) & + ZYNQ_SILICON_VER_MASK) >> ZYNQ_SILICON_VER_SHIFT; + + return ver; +} + void reset_cpu(ulong addr) { zynq_slcr_cpu_reset(); diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c index ba6a6aee5..e0ed3bfb4 100644 --- a/arch/arm/cpu/armv7/zynq/ddrc.c +++ b/arch/arm/cpu/armv7/zynq/ddrc.c @@ -40,11 +40,8 @@ void zynq_ddrc_init(void) * first stage bootloader. To get ECC to work all memory has * been initialized by writing any value. */ - memset(0, 0, 1 * 1024 * 1024); + memset((void *)0, 0, 1 * 1024 * 1024); } else { puts("Memory: ECC disabled\n"); } - - if (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT) - gd->ram_size /= 2; } diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index d7c188233..934ccc31c 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -8,26 +8,75 @@ #include <asm/io.h> #include <malloc.h> #include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> #include <asm/arch/clk.h> #define SLCR_LOCK_MAGIC 0x767B #define SLCR_UNLOCK_MAGIC 0xDF0D +#define SLCR_USB_L1_SEL 0x04 + #define SLCR_IDCODE_MASK 0x1F000 #define SLCR_IDCODE_SHIFT 12 +/* + * zynq_slcr_mio_get_status - Get the status of MIO peripheral. + * + * @peri_name: Name of the peripheral for checking MIO status + * @get_pins: Pointer to array of get pin for this peripheral + * @num_pins: Number of pins for this peripheral + * @mask: Mask value + * @check_val: Required check value to get the status of periph + */ +struct zynq_slcr_mio_get_status { + const char *peri_name; + const int *get_pins; + int num_pins; + u32 mask; + u32 check_val; +}; + +static const int usb0_pins[] = { + 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39 +}; + +static const int usb1_pins[] = { + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51 +}; + +static const struct zynq_slcr_mio_get_status mio_periphs[] = { + { + "usb0", + usb0_pins, + ARRAY_SIZE(usb0_pins), + SLCR_USB_L1_SEL, + SLCR_USB_L1_SEL, + }, + { + "usb1", + usb1_pins, + ARRAY_SIZE(usb1_pins), + SLCR_USB_L1_SEL, + SLCR_USB_L1_SEL, + }, +}; + static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */ void zynq_slcr_lock(void) { - if (!slcr_lock) + if (!slcr_lock) { writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock); + slcr_lock = 1; + } } void zynq_slcr_unlock(void) { - if (slcr_lock) + if (slcr_lock) { writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock); + slcr_lock = 0; + } } /* Reset the entire system */ @@ -82,7 +131,7 @@ void zynq_slcr_devcfg_disable(void) { zynq_slcr_unlock(); - /* Disable AXI interface */ + /* Disable AXI interface by asserting FPGA resets */ writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl); /* Set Level Shifters DT618760 */ @@ -98,7 +147,7 @@ void zynq_slcr_devcfg_enable(void) /* Set Level Shifters DT618760 */ writel(0xF, &slcr_base->lvl_shftr_en); - /* Disable AXI interface */ + /* Enable AXI interface by de-asserting FPGA resets */ writel(0x0, &slcr_base->fpga_rst_ctrl); zynq_slcr_lock(); @@ -115,3 +164,33 @@ u32 zynq_slcr_get_idcode(void) return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >> SLCR_IDCODE_SHIFT; } + +/* + * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral. + * + * @periph: Name of the peripheral + * + * Returns count to indicate the number of pins configured for the + * given @periph. + */ +int zynq_slcr_get_mio_pin_status(const char *periph) +{ + const struct zynq_slcr_mio_get_status *mio_ptr; + int val, i, j; + int mio = 0; + + for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) { + if (strcmp(periph, mio_periphs[i].peri_name) == 0) { + mio_ptr = &mio_periphs[i]; + for (j = 0; j < mio_ptr->num_pins; j++) { + val = readl(&slcr_base->mio_pin + [mio_ptr->get_pins[j]]); + if ((val & mio_ptr->mask) == mio_ptr->check_val) + mio++; + } + break; + } + } + + return mio; +} diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c index fcad762c0..d73e5cbaa 100644 --- a/arch/arm/cpu/armv7/zynq/spl.c +++ b/arch/arm/cpu/armv7/zynq/spl.c @@ -28,6 +28,13 @@ void board_init_f(ulong dummy) board_init_r(NULL, 0); } +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + board_init(); +} +#endif + u32 spl_boot_device(void) { u32 mode; @@ -67,3 +74,11 @@ int spl_start_uboot(void) return 0; } #endif + +__weak void ps7_init(void) +{ + /* + * This function is overridden by the one in + * board/xilinx/zynq/ps7_init.c, if it exists. + */ +} diff --git a/arch/arm/cpu/armv7/zynq/u-boot.lds b/arch/arm/cpu/armv7/zynq/u-boot.lds index f2a596598..69500a64e 100644 --- a/arch/arm/cpu/armv7/zynq/u-boot.lds +++ b/arch/arm/cpu/armv7/zynq/u-boot.lds @@ -88,7 +88,7 @@ SECTIONS } /* - * Zynq needs to discard more sections because the user + * Zynq needs to discard these sections because the user * is expected to pass this image on to tools for boot.bin * generation that require them to be dropped. */ diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 33d3f3688..4b11aa4f2 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -50,10 +50,10 @@ reset: */ adr x0, vectors switch_el x1, 3f, 2f, 1f -3: mrs x0, scr_el3 +3: msr vbar_el3, x0 + mrs x0, scr_el3 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */ msr scr_el3, x0 - msr vbar_el3, x0 msr cptr_el3, xzr /* Enable FP/SIMD */ ldr x0, =COUNTER_FREQUENCY msr cntfrq_el0, x0 /* Initialize CNTFRQ */ diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/cpu/at91-common/spl.c index 7f4debb91..cbb5a529d 100644 --- a/arch/arm/cpu/at91-common/spl.c +++ b/arch/arm/cpu/at91-common/spl.c @@ -20,6 +20,43 @@ static void at91_disable_wdt(void) writel(AT91_WDT_MR_WDDIS, &wdt->mr); } +static void switch_to_main_crystal_osc(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = readl(&pmc->mor); + tmp &= ~AT91_PMC_MOR_OSCOUNT(0xff); + tmp &= ~AT91_PMC_MOR_KEY(0xff); + tmp |= AT91_PMC_MOR_MOSCEN; + tmp |= AT91_PMC_MOR_OSCOUNT(8); + tmp |= AT91_PMC_MOR_KEY(0x37); + writel(tmp, &pmc->mor); + while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCS)) + ; + + tmp = readl(&pmc->mor); + tmp &= ~AT91_PMC_MOR_OSCBYPASS; + tmp &= ~AT91_PMC_MOR_KEY(0xff); + tmp |= AT91_PMC_MOR_KEY(0x37); + writel(tmp, &pmc->mor); + + tmp = readl(&pmc->mor); + tmp |= AT91_PMC_MOR_MOSCSEL; + tmp &= ~AT91_PMC_MOR_KEY(0xff); + tmp |= AT91_PMC_MOR_KEY(0x37); + writel(tmp, &pmc->mor); + + while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCSELS)) + ; + + tmp = readl(&pmc->mor); + tmp &= ~AT91_PMC_MOR_MOSCRCEN; + tmp &= ~AT91_PMC_MOR_KEY(0xff); + tmp |= AT91_PMC_MOR_KEY(0x37); + writel(tmp, &pmc->mor); +} + void at91_plla_init(u32 pllar) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; @@ -76,6 +113,8 @@ u32 spl_boot_mode(void) void s_init(void) { + switch_to_main_crystal_osc(); + /* disable watchdog */ at91_disable_wdt(); diff --git a/arch/arm/cpu/pxa/cpuinfo.c b/arch/arm/cpu/pxa/cpuinfo.c index 9d1607995..17d8be5b5 100644 --- a/arch/arm/cpu/pxa/cpuinfo.c +++ b/arch/arm/cpu/pxa/cpuinfo.c @@ -11,6 +11,12 @@ #include <errno.h> #include <linux/compiler.h> +#ifdef CONFIG_CPU_PXA25X +#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) +#error "Init SP address must be set to 0xfffff800 for PXA250" +#endif +#endif + #define CPU_MASK_PXA_PRODID 0x000003f0 #define CPU_MASK_PXA_REVID 0x0000000f diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index ae0d13ce8..c77d51e6d 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -23,54 +23,6 @@ #include <config.h> #include <version.h> -#ifdef CONFIG_CPU_PXA25X -#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) -#error "Init SP address must be set to 0xfffff800 for PXA250" -#endif -#endif - -.globl _start -_start: b reset -#ifdef CONFIG_SPL_BUILD - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - -_hang: - .word do_hang - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 /* now 16*4=64 */ -#else - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -#endif /* CONFIG_SPL_BUILD */ -.global _end_vect -_end_vect: - - .balignl 16,0xdeadbeef /* ************************************************************************* * @@ -84,26 +36,7 @@ _end_vect: ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -174,190 +107,6 @@ cpu_init_crit: mov pc, lr /* back to my caller */ #endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ -#ifndef CONFIG_SPL_BUILD -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack - ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_bad_stack_swi - sub r13, r13, #4 @ space on current stack for scratch reg. - str r0, [r13] @ save R0's value. - ldr r0, IRQ_STACK_START_IN @ get data regions start - str lr, [r0] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r0, #4] @ save spsr in position 1 of saved stack - ldr lr, [r0] @ restore lr - ldr r0, [r13] @ restore r0 - add r13, r13, #4 @ pop stack entry - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm -#endif /* CONFIG_SPL_BUILD */ - -/* - * exception handlers - */ -#ifdef CONFIG_SPL_BUILD - .align 5 -do_hang: - bl hang /* hang and never return */ -#else /* !CONFIG_SPL_BUILD */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - .align 5 -#endif /* CONFIG_SPL_BUILD */ - - /* * Enable MMU to use DCache as DRAM. * diff --git a/arch/arm/cpu/sa1100/cpu.c b/arch/arm/cpu/sa1100/cpu.c index 6651898de..4c9752a1c 100644 --- a/arch/arm/cpu/sa1100/cpu.c +++ b/arch/arm/cpu/sa1100/cpu.c @@ -17,6 +17,7 @@ #include <common.h> #include <command.h> #include <asm/system.h> +#include <asm/io.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; @@ -52,3 +53,16 @@ static void cache_flush (void) asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); } + +#define RST_BASE 0x90030000 +#define RSRR 0x00 +#define RCSR 0x04 + +__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused))) +{ + /* repeat endlessly */ + while (1) { + writel(0, RST_BASE + RCSR); + writel(1, RST_BASE + RSRR); + } +} diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index bf80937a7..78e0cb886 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -16,36 +16,6 @@ /* ************************************************************************* * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * * Startup Code (reset vector) * * do important init only if we don't start from memory! @@ -56,26 +26,7 @@ _fiq: .word fiq ************************************************************************* */ -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ + .globl reset reset: /* @@ -173,177 +124,3 @@ cpu_init_crit: mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ mov pc, lr - - -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - msr spsr_c, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - - .align 5 -.globl reset_cpu -reset_cpu: - ldr r0, RST_BASE - mov r1, #0x0 @ set bit 3-0 ... - str r1, [r0, #RCSR] @ ... to clear in RCSR - mov r1, #0x1 - str r1, [r0, #RSRR] @ and perform reset - b reset_cpu @ silly, but repeat endlessly diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/cpu/tegra-common/pinmux-common.c index d62618cd0..6e3ab0c14 100644 --- a/arch/arm/cpu/tegra-common/pinmux-common.c +++ b/arch/arm/cpu/tegra-common/pinmux-common.c @@ -86,12 +86,31 @@ #define IO_RESET_SHIFT 8 #define RCV_SEL_SHIFT 9 +#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30) +/* This register/field only exists on Tegra114 and later */ +#define APB_MISC_PP_PINMUX_GLOBAL_0 0x40 +#define CLAMP_INPUTS_WHEN_TRISTATED 1 + +void pinmux_set_tristate_input_clamping(void) +{ + u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0); + u32 val; + + val = readl(reg); + val |= CLAMP_INPUTS_WHEN_TRISTATED; + writel(val, reg); +} +#endif + void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func) { u32 *reg = MUX_REG(pin); int i, mux = -1; u32 val; + if (func == PMUX_FUNC_DEFAULT) + return; + /* Error check on pin and func */ assert(pmux_pingrp_isvalid(pin)); assert(pmux_func_isvalid(func)); diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index 3e886680e..4beddf08e 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -18,6 +18,7 @@ SECTIONS .text : { __image_copy_start = .; + *(.vectors) CPUDIR/start.o (.text*) *(.text*) } diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 33c1f99fc..a7728e0a2 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -18,6 +18,7 @@ SECTIONS .text : { *(.__image_copy_start) + *(.vectors) CPUDIR/start.o (.text*) *(.text*) } diff --git a/arch/arm/dts/exynos4210-origen.dts b/arch/arm/dts/exynos4210-origen.dts index 5c9d2aed6..15059d220 100644 --- a/arch/arm/dts/exynos4210-origen.dts +++ b/arch/arm/dts/exynos4210-origen.dts @@ -36,10 +36,10 @@ sdhci@12530000 { samsung,bus-width = <4>; samsung,timing = <1 2 3>; - cd-gpios = <&gpio 0x2008002 0>; + cd-gpios = <&gpio 0xA2 0>; }; sdhci@12540000 { status = "disabled"; }; -};
\ No newline at end of file +}; diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts index 992e0234c..0ff69393b 100644 --- a/arch/arm/dts/exynos4210-trats.dts +++ b/arch/arm/dts/exynos4210-trats.dts @@ -101,7 +101,7 @@ sdhci@12510000 { samsung,bus-width = <8>; samsung,timing = <1 3 3>; - pwr-gpios = <&gpio 0x2008002 0>; + pwr-gpios = <&gpio 0xA2 0>; }; sdhci@12520000 { @@ -111,10 +111,10 @@ sdhci@12530000 { samsung,bus-width = <4>; samsung,timing = <1 2 3>; - cd-gpios = <&gpio 0x20c6004 0>; + cd-gpios = <&gpio 0x39C 0>; }; sdhci@12540000 { status = "disabled"; }; -};
\ No newline at end of file +}; diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts index 1cdd981d6..6941906aa 100644 --- a/arch/arm/dts/exynos4210-universal_c210.dts +++ b/arch/arm/dts/exynos4210-universal_c210.dts @@ -24,7 +24,7 @@ sdhci@12510000 { samsung,bus-width = <8>; samsung,timing = <1 3 3>; - pwr-gpios = <&gpio 0x2008002 0>; + pwr-gpios = <&gpio 0xA2 0>; }; sdhci@12520000 { @@ -34,7 +34,7 @@ sdhci@12530000 { samsung,bus-width = <4>; samsung,timing = <1 2 3>; - cd-gpios = <&gpio 0x20c6004 0>; + cd-gpios = <&gpio 0x39C 0>; }; sdhci@12540000 { diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts index 7d32067fd..1596f8328 100644 --- a/arch/arm/dts/exynos4412-trats2.dts +++ b/arch/arm/dts/exynos4412-trats2.dts @@ -415,7 +415,7 @@ sdhci@12510000 { samsung,bus-width = <8>; samsung,timing = <1 3 3>; - pwr-gpios = <&gpio 0x2004002 0>; + pwr-gpios = <&gpio 0xB2 0>; }; sdhci@12520000 { @@ -425,7 +425,7 @@ sdhci@12530000 { samsung,bus-width = <4>; samsung,timing = <1 2 3>; - cd-gpios = <&gpio 0x20C6004 0>; + cd-gpios = <&gpio 0x3BC 0>; }; sdhci@12540000 { diff --git a/arch/arm/dts/imx6q-sabreauto.dts b/arch/arm/dts/imx6q-sabreauto.dts index a3c9c91f3..7af2a88fd 100644 --- a/arch/arm/dts/imx6q-sabreauto.dts +++ b/arch/arm/dts/imx6q-sabreauto.dts @@ -1,9 +1,9 @@ /* - + * Copyright 2012 Freescale Semiconductor, Inc. - + * Copyright 2011 Linaro Ltd. - + * - + * SPDX-License-Identifier: GPL-2.0+ - + */ + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ /dts-v1/; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index f20b8bd60..2d076f194 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -10,4 +10,198 @@ / { compatible = "xlnx,zynq-7000"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + clocks = <&clkc 3>; + clock-latency = <1000>; + operating-points = < + /* kHz uV */ + 666667 1000000 + 333334 1000000 + 222223 1000000 + >; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + clocks = <&clkc 3>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 5 4>, <0 6 4>; + interrupt-parent = <&intc>; + reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + i2c0: zynq-i2c@e0004000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + clocks = <&clkc 38>; + interrupt-parent = <&intc>; + interrupts = <0 25 4>; + reg = <0xe0004000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: zynq-i2c@e0005000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + clocks = <&clkc 39>; + interrupt-parent = <&intc>; + interrupts = <0 48 4>; + reg = <0xe0005000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + intc: interrupt-controller@f8f01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xF8F01000 0x1000>, + <0xF8F00100 0x100>; + }; + + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xF8F02000 0x1000>; + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + cache-unified; + cache-level = <2>; + }; + + uart0: uart@e0000000 { + compatible = "xlnx,xuartps"; + status = "disabled"; + clocks = <&clkc 23>, <&clkc 40>; + clock-names = "ref_clk", "aper_clk"; + reg = <0xE0000000 0x1000>; + interrupts = <0 27 4>; + }; + + uart1: uart@e0001000 { + compatible = "xlnx,xuartps"; + status = "disabled"; + clocks = <&clkc 24>, <&clkc 41>; + clock-names = "ref_clk", "aper_clk"; + reg = <0xE0001000 0x1000>; + interrupts = <0 50 4>; + }; + + gem0: ethernet@e000b000 { + compatible = "cdns,gem"; + reg = <0xe000b000 0x4000>; + status = "disabled"; + interrupts = <0 22 4>; + clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; + clock-names = "pclk", "hclk", "tx_clk"; + }; + + gem1: ethernet@e000c000 { + compatible = "cdns,gem"; + reg = <0xe000c000 0x4000>; + status = "disabled"; + interrupts = <0 45 4>; + clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; + clock-names = "pclk", "hclk", "tx_clk"; + }; + + sdhci0: ps7-sdhci@e0100000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 21>, <&clkc 32>; + interrupt-parent = <&intc>; + interrupts = <0 24 4>; + reg = <0xe0100000 0x1000>; + } ; + + sdhci1: ps7-sdhci@e0101000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 22>, <&clkc 33>; + interrupt-parent = <&intc>; + interrupts = <0 47 4>; + reg = <0xe0101000 0x1000>; + } ; + + slcr: slcr@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-slcr", "syscon"; + reg = <0xF8000000 0x1000>; + ranges; + clkc: clkc@100 { + #clock-cells = <1>; + compatible = "xlnx,ps7-clkc"; + ps-clk-frequency = <33333333>; + fclk-enable = <0>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", + "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", + "dci", "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", + "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", + "dma", "usb0_aper", "usb1_aper", "gem0_aper", + "gem1_aper", "sdio0_aper", "sdio1_aper", + "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", + "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", + "gpio_aper", "lqspi_aper", "smc_aper", "swdt", + "dbg_trc", "dbg_apb"; + reg = <0x100 0x100>; + }; + }; + + global_timer: timer@f8f00200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xf8f00200 0x20>; + interrupts = <1 11 0x301>; + interrupt-parent = <&intc>; + clocks = <&clkc 4>; + }; + + ttc0: ttc0@f8001000 { + interrupt-parent = <&intc>; + interrupts = < 0 10 4 0 11 4 0 12 4 >; + compatible = "cdns,ttc"; + clocks = <&clkc 6>; + reg = <0xF8001000 0x1000>; + }; + + ttc1: ttc1@f8002000 { + interrupt-parent = <&intc>; + interrupts = < 0 37 4 0 38 4 0 39 4 >; + compatible = "cdns,ttc"; + clocks = <&clkc 6>; + reg = <0xF8002000 0x1000>; + }; + scutimer: scutimer@f8f00600 { + interrupt-parent = <&intc>; + interrupts = < 1 13 0x301 >; + compatible = "arm,cortex-a9-twd-timer"; + reg = < 0xf8f00600 0x20 >; + clocks = <&clkc 4>; + } ; + }; }; diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts index 6da71c116..c373a2cc3 100644 --- a/arch/arm/dts/zynq-microzed.dts +++ b/arch/arm/dts/zynq-microzed.dts @@ -11,4 +11,13 @@ / { model = "Zynq MicroZED Board"; compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 667dc2825..4fa0b00b3 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -11,4 +11,13 @@ / { model = "Zynq ZC702 Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index 526fc8888..2a8019575 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -11,4 +11,13 @@ / { model = "Zynq ZC706 Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 8b542a109..5e6617497 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -11,4 +11,13 @@ / { model = "Zynq ZC770 XM010 Board"; compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 0379a0706..127a6619c 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -11,4 +11,13 @@ / { model = "Zynq ZC770 XM012 Board"; compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index a4f9e05fc..c61c7e759 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -11,4 +11,13 @@ / { model = "Zynq ZC770 XM013 Board"; compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 91a5deba4..70cc8a6c0 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -11,4 +11,13 @@ / { model = "Zynq ZED Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x20000000>; + }; }; diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index b04dfbbcb..0e713952d 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -19,6 +19,7 @@ obj-y += misc.o endif ifeq ($(SOC),$(filter $(SOC),mx6)) obj-$(CONFIG_CMD_SATA) += sata.o +obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o endif obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index b59b80283..6e46ea8dc 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -30,6 +30,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; +#if defined CONFIG_MX6SL + /* Check whether LVE bit needs to be set */ + if (pad_ctrl & PAD_CTL_LVE) { + pad_ctrl &= ~PAD_CTL_LVE; + pad_ctrl |= PAD_CTL_LVE_BIT; + } +#endif + if (mux_ctrl_ofs) __raw_writel(mux_mode, base + mux_ctrl_ofs); diff --git a/arch/arm/imx-common/video.c b/arch/arm/imx-common/video.c new file mode 100644 index 000000000..0121cd78f --- /dev/null +++ b/arch/arm/imx-common/video.c @@ -0,0 +1,65 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/imx-common/video.h> + +extern struct display_info_t const displays[]; +extern size_t display_count; + +int board_video_skip(void) +{ + int i; + int ret; + char const *panel = getenv("panel"); + if (!panel) { + for (i = 0; i < display_count; i++) { + struct display_info_t const *dev = displays+i; + if (dev->detect && dev->detect(dev)) { + panel = dev->mode.name; + printf("auto-detected panel %s\n", panel); + break; + } + } + if (!panel) { + panel = displays[0].mode.name; + printf("No panel detected: default to %s\n", panel); + i = 0; + } + } else { + for (i = 0; i < display_count; i++) { + if (!strcmp(panel, displays[i].mode.name)) + break; + } + } + if (i < display_count) { + ret = ipuv3_fb_init(&displays[i].mode, 0, + displays[i].pixfmt); + if (!ret) { + displays[i].enable(displays+i); + printf("Display: %s (%ux%u)\n", + displays[i].mode.name, + displays[i].mode.xres, + displays[i].mode.yres); + } else + printf("LCD %s cannot be configured: %d\n", + displays[i].mode.name, ret); + } else { + printf("unsupported panel %s\n", panel); + return -EINVAL; + } + + return 0; +} + +#ifdef CONFIG_IMX_HDMI +#include <asm/arch/mxc_hdmi.h> +#include <asm/io.h> +int detect_hdmi(struct display_info_t const *dev) +{ + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT; +} +#endif diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 763745754..f00fad38f 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -42,6 +42,8 @@ #define MODULE_CLKCTRL_IDLEST_DISABLED 3 /* CM_CLKMODE_DPLL */ +#define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12 +#define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12) #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 91ff2ad0e..33a82fca9 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -11,6 +11,7 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ #include <linux/mtd/omap_gpmc.h> +#include <asm/ti-common/sys_proto.h> #include <asm/arch/cpu.h> #define BOARD_REV_ID 0x0 diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h index 453560843..04f6239fd 100644 --- a/arch/arm/include/asm/arch-at91/at91_pmc.h +++ b/arch/arm/include/asm/arch-at91/at91_pmc.h @@ -70,7 +70,10 @@ typedef struct at91_pmc { #define AT91_PMC_MOR_MOSCEN 0x01 #define AT91_PMC_MOR_OSCBYPASS 0x02 +#define AT91_PMC_MOR_MOSCRCEN 0x08 #define AT91_PMC_MOR_OSCOUNT(x) ((x & 0xff) << 8) +#define AT91_PMC_MOR_KEY(x) ((x & 0xff) << 16) +#define AT91_PMC_MOR_MOSCSEL (1 << 24) #define AT91_PMC_PLLXR_DIV(x) (x & 0xFF) #define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8) @@ -142,6 +145,7 @@ typedef struct at91_pmc { #define AT91_PMC_IXR_PCKRDY1 0x00000200 #define AT91_PMC_IXR_PCKRDY2 0x00000400 #define AT91_PMC_IXR_PCKRDY3 0x00000800 +#define AT91_PMC_IXR_MOSCSELS 0x00010000 #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/include/asm/arch-at91/at91sam9x5.h index a47103851..d49c18480 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9x5.h +++ b/arch/arm/include/asm/arch-at91/at91sam9x5.h @@ -12,6 +12,9 @@ #ifndef __AT91SAM9X5_H__ #define __AT91SAM9X5_H__ +#define CONFIG_ARM926EJS /* ARM926EJS Core */ +#define CONFIG_AT91FAMILY /* it's a member of AT91 family */ + /* * Peripheral identifiers/interrupts. */ diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h index a63f97406..d712a0dc9 100644 --- a/arch/arm/include/asm/arch-at91/hardware.h +++ b/arch/arm/include/asm/arch-at91/hardware.h @@ -25,8 +25,6 @@ # include <asm/arch/at91sam9x5.h> #elif defined(CONFIG_AT91CAP9) # include <asm/arch/at91cap9.h> -#elif defined(CONFIG_AT91X40) -# include <asm/arch/at91x40.h> #elif defined(CONFIG_SAMA5D3) # include <asm/arch/sama5d3.h> #else diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index fdf73b507..ba717146f 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -98,7 +98,7 @@ #define EXYNOS5_I2C_SPACING 0x10000 #define EXYNOS5_AUDIOSS_BASE 0x03810000 -#define EXYNOS5_GPIO_PART4_BASE 0x03860000 +#define EXYNOS5_GPIO_PART8_BASE 0x03860000 #define EXYNOS5_PRO_ID 0x10000000 #define EXYNOS5_CLOCK_BASE 0x10010000 #define EXYNOS5_POWER_BASE 0x10040000 @@ -108,9 +108,13 @@ #define EXYNOS5_WATCHDOG_BASE 0x101D0000 #define EXYNOS5_ACE_SFR_BASE 0x10830000 #define EXYNOS5_DMC_PHY_BASE 0x10C00000 -#define EXYNOS5_GPIO_PART3_BASE 0x10D10000 +#define EXYNOS5_GPIO_PART5_BASE 0x10D10000 +#define EXYNOS5_GPIO_PART6_BASE 0x10D10060 +#define EXYNOS5_GPIO_PART7_BASE 0x10D100C0 #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 #define EXYNOS5_GPIO_PART1_BASE 0x11400000 +#define EXYNOS5_GPIO_PART2_BASE 0x114002E0 +#define EXYNOS5_GPIO_PART3_BASE 0x11400C00 #define EXYNOS5_MIPI_DSIM_BASE 0x11D00000 #define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000 #define EXYNOS5_USB3PHY_BASE 0x12100000 @@ -125,7 +129,7 @@ #define EXYNOS5_I2S_BASE 0x12D60000 #define EXYNOS5_PWMTIMER_BASE 0x12DD0000 #define EXYNOS5_SPI_ISP_BASE 0x131A0000 -#define EXYNOS5_GPIO_PART2_BASE 0x13400000 +#define EXYNOS5_GPIO_PART4_BASE 0x13400000 #define EXYNOS5_FIMD_BASE 0x14400000 #define EXYNOS5_DP_BASE 0x145B0000 @@ -135,7 +139,7 @@ /* EXYNOS5420 */ #define EXYNOS5420_AUDIOSS_BASE 0x03810000 -#define EXYNOS5420_GPIO_PART5_BASE 0x03860000 +#define EXYNOS5420_GPIO_PART6_BASE 0x03860000 #define EXYNOS5420_PRO_ID 0x10000000 #define EXYNOS5420_CLOCK_BASE 0x10010000 #define EXYNOS5420_POWER_BASE 0x10040000 @@ -158,8 +162,9 @@ #define EXYNOS5420_PWMTIMER_BASE 0x12DD0000 #define EXYNOS5420_SPI_ISP_BASE 0x131A0000 #define EXYNOS5420_GPIO_PART2_BASE 0x13400000 -#define EXYNOS5420_GPIO_PART3_BASE 0x13410000 -#define EXYNOS5420_GPIO_PART4_BASE 0x14000000 +#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00 +#define EXYNOS5420_GPIO_PART4_BASE 0x13410000 +#define EXYNOS5420_GPIO_PART5_BASE 0x14000000 #define EXYNOS5420_GPIO_PART1_BASE 0x14010000 #define EXYNOS5420_MIPI_DSIM_BASE 0x14500000 #define EXYNOS5420_DP_BASE 0x145B0000 diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index d6868fa25..be5113f0e 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -19,328 +19,1515 @@ struct s5p_gpio_bank { unsigned char res1[8]; }; -struct exynos4_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank e2; - struct s5p_gpio_bank e3; - struct s5p_gpio_bank e4; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; -}; +/* GPIO pins per bank */ +#define GPIO_PER_BANK 8 -struct exynos4_gpio_part2 { - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; - struct s5p_gpio_bank k0; - struct s5p_gpio_bank k1; - struct s5p_gpio_bank k2; - struct s5p_gpio_bank k3; - struct s5p_gpio_bank l0; - struct s5p_gpio_bank l1; - struct s5p_gpio_bank l2; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; - struct s5p_gpio_bank res1[80]; - struct s5p_gpio_bank x0; - struct s5p_gpio_bank x1; - struct s5p_gpio_bank x2; - struct s5p_gpio_bank x3; -}; +/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */ +enum exynos4_gpio_pin { + /* GPIO_PART1_STARTS */ + EXYNOS4_GPIO_A00, /* 0 */ + EXYNOS4_GPIO_A01, + EXYNOS4_GPIO_A02, + EXYNOS4_GPIO_A03, + EXYNOS4_GPIO_A04, + EXYNOS4_GPIO_A05, + EXYNOS4_GPIO_A06, + EXYNOS4_GPIO_A07, + EXYNOS4_GPIO_A10, /* 8 */ + EXYNOS4_GPIO_A11, + EXYNOS4_GPIO_A12, + EXYNOS4_GPIO_A13, + EXYNOS4_GPIO_A14, + EXYNOS4_GPIO_A15, + EXYNOS4_GPIO_A16, + EXYNOS4_GPIO_A17, + EXYNOS4_GPIO_B0, /* 16 0x10 */ + EXYNOS4_GPIO_B1, + EXYNOS4_GPIO_B2, + EXYNOS4_GPIO_B3, + EXYNOS4_GPIO_B4, + EXYNOS4_GPIO_B5, + EXYNOS4_GPIO_B6, + EXYNOS4_GPIO_B7, + EXYNOS4_GPIO_C00, /* 24 0x18 */ + EXYNOS4_GPIO_C01, + EXYNOS4_GPIO_C02, + EXYNOS4_GPIO_C03, + EXYNOS4_GPIO_C04, + EXYNOS4_GPIO_C05, + EXYNOS4_GPIO_C06, + EXYNOS4_GPIO_C07, + EXYNOS4_GPIO_C10, /* 32 0x20*/ + EXYNOS4_GPIO_C11, + EXYNOS4_GPIO_C12, + EXYNOS4_GPIO_C13, + EXYNOS4_GPIO_C14, + EXYNOS4_GPIO_C15, + EXYNOS4_GPIO_C16, + EXYNOS4_GPIO_C17, + EXYNOS4_GPIO_D00, /* 40 0x28 */ + EXYNOS4_GPIO_D01, + EXYNOS4_GPIO_D02, + EXYNOS4_GPIO_D03, + EXYNOS4_GPIO_D04, + EXYNOS4_GPIO_D05, + EXYNOS4_GPIO_D06, + EXYNOS4_GPIO_D07, + EXYNOS4_GPIO_D10, /* 48 0x30 */ + EXYNOS4_GPIO_D11, + EXYNOS4_GPIO_D12, + EXYNOS4_GPIO_D13, + EXYNOS4_GPIO_D14, + EXYNOS4_GPIO_D15, + EXYNOS4_GPIO_D16, + EXYNOS4_GPIO_D17, + EXYNOS4_GPIO_E00, /* 56 0x38 */ + EXYNOS4_GPIO_E01, + EXYNOS4_GPIO_E02, + EXYNOS4_GPIO_E03, + EXYNOS4_GPIO_E04, + EXYNOS4_GPIO_E05, + EXYNOS4_GPIO_E06, + EXYNOS4_GPIO_E07, + EXYNOS4_GPIO_E10, /* 64 0x40 */ + EXYNOS4_GPIO_E11, + EXYNOS4_GPIO_E12, + EXYNOS4_GPIO_E13, + EXYNOS4_GPIO_E14, + EXYNOS4_GPIO_E15, + EXYNOS4_GPIO_E16, + EXYNOS4_GPIO_E17, + EXYNOS4_GPIO_E20, /* 72 0x48 */ + EXYNOS4_GPIO_E21, + EXYNOS4_GPIO_E22, + EXYNOS4_GPIO_E23, + EXYNOS4_GPIO_E24, + EXYNOS4_GPIO_E25, + EXYNOS4_GPIO_E26, + EXYNOS4_GPIO_E27, + EXYNOS4_GPIO_E30, /* 80 0x50 */ + EXYNOS4_GPIO_E31, + EXYNOS4_GPIO_E32, + EXYNOS4_GPIO_E33, + EXYNOS4_GPIO_E34, + EXYNOS4_GPIO_E35, + EXYNOS4_GPIO_E36, + EXYNOS4_GPIO_E37, + EXYNOS4_GPIO_E40, /* 88 0x58 */ + EXYNOS4_GPIO_E41, + EXYNOS4_GPIO_E42, + EXYNOS4_GPIO_E43, + EXYNOS4_GPIO_E44, + EXYNOS4_GPIO_E45, + EXYNOS4_GPIO_E46, + EXYNOS4_GPIO_E47, + EXYNOS4_GPIO_F00, /* 96 0x60 */ + EXYNOS4_GPIO_F01, + EXYNOS4_GPIO_F02, + EXYNOS4_GPIO_F03, + EXYNOS4_GPIO_F04, + EXYNOS4_GPIO_F05, + EXYNOS4_GPIO_F06, + EXYNOS4_GPIO_F07, + EXYNOS4_GPIO_F10, /* 104 0x68 */ + EXYNOS4_GPIO_F11, + EXYNOS4_GPIO_F12, + EXYNOS4_GPIO_F13, + EXYNOS4_GPIO_F14, + EXYNOS4_GPIO_F15, + EXYNOS4_GPIO_F16, + EXYNOS4_GPIO_F17, + EXYNOS4_GPIO_F20, /* 112 0x70 */ + EXYNOS4_GPIO_F21, + EXYNOS4_GPIO_F22, + EXYNOS4_GPIO_F23, + EXYNOS4_GPIO_F24, + EXYNOS4_GPIO_F25, + EXYNOS4_GPIO_F26, + EXYNOS4_GPIO_F27, + EXYNOS4_GPIO_F30, /* 120 0x78 */ + EXYNOS4_GPIO_F31, + EXYNOS4_GPIO_F32, + EXYNOS4_GPIO_F33, + EXYNOS4_GPIO_F34, + EXYNOS4_GPIO_F35, + EXYNOS4_GPIO_F36, + EXYNOS4_GPIO_F37, -struct exynos4_gpio_part3 { - struct s5p_gpio_bank z; -}; + /* GPIO_PART2_STARTS */ + EXYNOS4_GPIO_MAX_PORT_PART_1, /* 128 0x80 */ + EXYNOS4_GPIO_J00 = EXYNOS4_GPIO_MAX_PORT_PART_1, + EXYNOS4_GPIO_J01, + EXYNOS4_GPIO_J02, + EXYNOS4_GPIO_J03, + EXYNOS4_GPIO_J04, + EXYNOS4_GPIO_J05, + EXYNOS4_GPIO_J06, + EXYNOS4_GPIO_J07, + EXYNOS4_GPIO_J10, /* 136 0x88 */ + EXYNOS4_GPIO_J11, + EXYNOS4_GPIO_J12, + EXYNOS4_GPIO_J13, + EXYNOS4_GPIO_J14, + EXYNOS4_GPIO_J15, + EXYNOS4_GPIO_J16, + EXYNOS4_GPIO_J17, + EXYNOS4_GPIO_K00, /* 144 0x90 */ + EXYNOS4_GPIO_K01, + EXYNOS4_GPIO_K02, + EXYNOS4_GPIO_K03, + EXYNOS4_GPIO_K04, + EXYNOS4_GPIO_K05, + EXYNOS4_GPIO_K06, + EXYNOS4_GPIO_K07, + EXYNOS4_GPIO_K10, /* 152 0x98 */ + EXYNOS4_GPIO_K11, + EXYNOS4_GPIO_K12, + EXYNOS4_GPIO_K13, + EXYNOS4_GPIO_K14, + EXYNOS4_GPIO_K15, + EXYNOS4_GPIO_K16, + EXYNOS4_GPIO_K17, + EXYNOS4_GPIO_K20, /* 160 0xA0 */ + EXYNOS4_GPIO_K21, + EXYNOS4_GPIO_K22, + EXYNOS4_GPIO_K23, + EXYNOS4_GPIO_K24, + EXYNOS4_GPIO_K25, + EXYNOS4_GPIO_K26, + EXYNOS4_GPIO_K27, + EXYNOS4_GPIO_K30, /* 168 0xA8 */ + EXYNOS4_GPIO_K31, + EXYNOS4_GPIO_K32, + EXYNOS4_GPIO_K33, + EXYNOS4_GPIO_K34, + EXYNOS4_GPIO_K35, + EXYNOS4_GPIO_K36, + EXYNOS4_GPIO_K37, + EXYNOS4_GPIO_L00, /* 176 0xB0 */ + EXYNOS4_GPIO_L01, + EXYNOS4_GPIO_L02, + EXYNOS4_GPIO_L03, + EXYNOS4_GPIO_L04, + EXYNOS4_GPIO_L05, + EXYNOS4_GPIO_L06, + EXYNOS4_GPIO_L07, + EXYNOS4_GPIO_L10, /* 184 0xB8 */ + EXYNOS4_GPIO_L11, + EXYNOS4_GPIO_L12, + EXYNOS4_GPIO_L13, + EXYNOS4_GPIO_L14, + EXYNOS4_GPIO_L15, + EXYNOS4_GPIO_L16, + EXYNOS4_GPIO_L17, + EXYNOS4_GPIO_L20, /* 192 0xC0 */ + EXYNOS4_GPIO_L21, + EXYNOS4_GPIO_L22, + EXYNOS4_GPIO_L23, + EXYNOS4_GPIO_L24, + EXYNOS4_GPIO_L25, + EXYNOS4_GPIO_L26, + EXYNOS4_GPIO_L27, + EXYNOS4_GPIO_Y00, /* 200 0xC8 */ + EXYNOS4_GPIO_Y01, + EXYNOS4_GPIO_Y02, + EXYNOS4_GPIO_Y03, + EXYNOS4_GPIO_Y04, + EXYNOS4_GPIO_Y05, + EXYNOS4_GPIO_Y06, + EXYNOS4_GPIO_Y07, + EXYNOS4_GPIO_Y10, /* 208 0xD0 */ + EXYNOS4_GPIO_Y11, + EXYNOS4_GPIO_Y12, + EXYNOS4_GPIO_Y13, + EXYNOS4_GPIO_Y14, + EXYNOS4_GPIO_Y15, + EXYNOS4_GPIO_Y16, + EXYNOS4_GPIO_Y17, + EXYNOS4_GPIO_Y20, /* 216 0xD8 */ + EXYNOS4_GPIO_Y21, + EXYNOS4_GPIO_Y22, + EXYNOS4_GPIO_Y23, + EXYNOS4_GPIO_Y24, + EXYNOS4_GPIO_Y25, + EXYNOS4_GPIO_Y26, + EXYNOS4_GPIO_Y27, + EXYNOS4_GPIO_Y30, /* 224 0xE0 */ + EXYNOS4_GPIO_Y31, + EXYNOS4_GPIO_Y32, + EXYNOS4_GPIO_Y33, + EXYNOS4_GPIO_Y34, + EXYNOS4_GPIO_Y35, + EXYNOS4_GPIO_Y36, + EXYNOS4_GPIO_Y37, + EXYNOS4_GPIO_Y40, /* 232 0xE8 */ + EXYNOS4_GPIO_Y41, + EXYNOS4_GPIO_Y42, + EXYNOS4_GPIO_Y43, + EXYNOS4_GPIO_Y44, + EXYNOS4_GPIO_Y45, + EXYNOS4_GPIO_Y46, + EXYNOS4_GPIO_Y47, + EXYNOS4_GPIO_Y50, /* 240 0xF0 */ + EXYNOS4_GPIO_Y51, + EXYNOS4_GPIO_Y52, + EXYNOS4_GPIO_Y53, + EXYNOS4_GPIO_Y54, + EXYNOS4_GPIO_Y55, + EXYNOS4_GPIO_Y56, + EXYNOS4_GPIO_Y57, + EXYNOS4_GPIO_Y60, /* 248 0xF8 */ + EXYNOS4_GPIO_Y61, + EXYNOS4_GPIO_Y62, + EXYNOS4_GPIO_Y63, + EXYNOS4_GPIO_Y64, + EXYNOS4_GPIO_Y65, + EXYNOS4_GPIO_Y66, + EXYNOS4_GPIO_Y67, + EXYNOS4_GPIO_X00 = 896, /* 896 0x380 */ + EXYNOS4_GPIO_X01, + EXYNOS4_GPIO_X02, + EXYNOS4_GPIO_X03, + EXYNOS4_GPIO_X04, + EXYNOS4_GPIO_X05, + EXYNOS4_GPIO_X06, + EXYNOS4_GPIO_X07, + EXYNOS4_GPIO_X10, /* 904 0x388 */ + EXYNOS4_GPIO_X11, + EXYNOS4_GPIO_X12, + EXYNOS4_GPIO_X13, + EXYNOS4_GPIO_X14, + EXYNOS4_GPIO_X15, + EXYNOS4_GPIO_X16, + EXYNOS4_GPIO_X17, + EXYNOS4_GPIO_X20, /* 912 0x390 */ + EXYNOS4_GPIO_X21, + EXYNOS4_GPIO_X22, + EXYNOS4_GPIO_X23, + EXYNOS4_GPIO_X24, + EXYNOS4_GPIO_X25, + EXYNOS4_GPIO_X26, + EXYNOS4_GPIO_X27, + EXYNOS4_GPIO_X30, /* 920 0x398 */ + EXYNOS4_GPIO_X31, + EXYNOS4_GPIO_X32, + EXYNOS4_GPIO_X33, + EXYNOS4_GPIO_X34, + EXYNOS4_GPIO_X35, + EXYNOS4_GPIO_X36, + EXYNOS4_GPIO_X37, + + /* GPIO_PART3_STARTS */ + EXYNOS4_GPIO_MAX_PORT_PART_2, /* 928 0x3A0 */ + EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2, + EXYNOS4_GPIO_Z1, + EXYNOS4_GPIO_Z2, + EXYNOS4_GPIO_Z3, + EXYNOS4_GPIO_Z4, + EXYNOS4_GPIO_Z5, + EXYNOS4_GPIO_Z6, + EXYNOS4_GPIO_Z7, -struct exynos4x12_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank res1[0x5]; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; - struct s5p_gpio_bank res2[0x2]; - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; + EXYNOS4_GPIO_MAX_PORT }; -struct exynos4x12_gpio_part2 { - struct s5p_gpio_bank res1[0x2]; - struct s5p_gpio_bank k0; - struct s5p_gpio_bank k1; - struct s5p_gpio_bank k2; - struct s5p_gpio_bank k3; - struct s5p_gpio_bank l0; - struct s5p_gpio_bank l1; - struct s5p_gpio_bank l2; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; - struct s5p_gpio_bank res2[0x3]; - struct s5p_gpio_bank m0; - struct s5p_gpio_bank m1; - struct s5p_gpio_bank m2; - struct s5p_gpio_bank m3; - struct s5p_gpio_bank m4; - struct s5p_gpio_bank res3[0x48]; - struct s5p_gpio_bank x0; - struct s5p_gpio_bank x1; - struct s5p_gpio_bank x2; - struct s5p_gpio_bank x3; +enum exynos4X12_gpio_pin { + /* GPIO_PART1_STARTS */ + EXYNOS4X12_GPIO_A00, /* 0 */ + EXYNOS4X12_GPIO_A01, + EXYNOS4X12_GPIO_A02, + EXYNOS4X12_GPIO_A03, + EXYNOS4X12_GPIO_A04, + EXYNOS4X12_GPIO_A05, + EXYNOS4X12_GPIO_A06, + EXYNOS4X12_GPIO_A07, + EXYNOS4X12_GPIO_A10, /* 8 */ + EXYNOS4X12_GPIO_A11, + EXYNOS4X12_GPIO_A12, + EXYNOS4X12_GPIO_A13, + EXYNOS4X12_GPIO_A14, + EXYNOS4X12_GPIO_A15, + EXYNOS4X12_GPIO_A16, + EXYNOS4X12_GPIO_A17, + EXYNOS4X12_GPIO_B0, /* 16 0x10 */ + EXYNOS4X12_GPIO_B1, + EXYNOS4X12_GPIO_B2, + EXYNOS4X12_GPIO_B3, + EXYNOS4X12_GPIO_B4, + EXYNOS4X12_GPIO_B5, + EXYNOS4X12_GPIO_B6, + EXYNOS4X12_GPIO_B7, + EXYNOS4X12_GPIO_C00, /* 24 0x18 */ + EXYNOS4X12_GPIO_C01, + EXYNOS4X12_GPIO_C02, + EXYNOS4X12_GPIO_C03, + EXYNOS4X12_GPIO_C04, + EXYNOS4X12_GPIO_C05, + EXYNOS4X12_GPIO_C06, + EXYNOS4X12_GPIO_C07, + EXYNOS4X12_GPIO_C10, /* 32 0x20 */ + EXYNOS4X12_GPIO_C11, + EXYNOS4X12_GPIO_C12, + EXYNOS4X12_GPIO_C13, + EXYNOS4X12_GPIO_C14, + EXYNOS4X12_GPIO_C15, + EXYNOS4X12_GPIO_C16, + EXYNOS4X12_GPIO_C17, + EXYNOS4X12_GPIO_D00, /* 40 0x28 */ + EXYNOS4X12_GPIO_D01, + EXYNOS4X12_GPIO_D02, + EXYNOS4X12_GPIO_D03, + EXYNOS4X12_GPIO_D04, + EXYNOS4X12_GPIO_D05, + EXYNOS4X12_GPIO_D06, + EXYNOS4X12_GPIO_D07, + EXYNOS4X12_GPIO_D10, /* 48 0x30 */ + EXYNOS4X12_GPIO_D11, + EXYNOS4X12_GPIO_D12, + EXYNOS4X12_GPIO_D13, + EXYNOS4X12_GPIO_D14, + EXYNOS4X12_GPIO_D15, + EXYNOS4X12_GPIO_D16, + EXYNOS4X12_GPIO_D17, + EXYNOS4X12_GPIO_F00 = 96, /* 96 0x60 */ + EXYNOS4X12_GPIO_F01, + EXYNOS4X12_GPIO_F02, + EXYNOS4X12_GPIO_F03, + EXYNOS4X12_GPIO_F04, + EXYNOS4X12_GPIO_F05, + EXYNOS4X12_GPIO_F06, + EXYNOS4X12_GPIO_F07, + EXYNOS4X12_GPIO_F10, /* 104 0x68 */ + EXYNOS4X12_GPIO_F11, + EXYNOS4X12_GPIO_F12, + EXYNOS4X12_GPIO_F13, + EXYNOS4X12_GPIO_F14, + EXYNOS4X12_GPIO_F15, + EXYNOS4X12_GPIO_F16, + EXYNOS4X12_GPIO_F17, + EXYNOS4X12_GPIO_F20, /* 112 0x70 */ + EXYNOS4X12_GPIO_F21, + EXYNOS4X12_GPIO_F22, + EXYNOS4X12_GPIO_F23, + EXYNOS4X12_GPIO_F24, + EXYNOS4X12_GPIO_F25, + EXYNOS4X12_GPIO_F26, + EXYNOS4X12_GPIO_F27, + EXYNOS4X12_GPIO_F30, /* 120 0x78 */ + EXYNOS4X12_GPIO_F31, + EXYNOS4X12_GPIO_F32, + EXYNOS4X12_GPIO_F33, + EXYNOS4X12_GPIO_F34, + EXYNOS4X12_GPIO_F35, + EXYNOS4X12_GPIO_F36, + EXYNOS4X12_GPIO_F37, + EXYNOS4X12_GPIO_J00 = 144, /* 144 0x90 */ + EXYNOS4X12_GPIO_J01, + EXYNOS4X12_GPIO_J02, + EXYNOS4X12_GPIO_J03, + EXYNOS4X12_GPIO_J04, + EXYNOS4X12_GPIO_J05, + EXYNOS4X12_GPIO_J06, + EXYNOS4X12_GPIO_J07, + EXYNOS4X12_GPIO_J10, /* 152 0x98 */ + EXYNOS4X12_GPIO_J11, + EXYNOS4X12_GPIO_J12, + EXYNOS4X12_GPIO_J13, + EXYNOS4X12_GPIO_J14, + EXYNOS4X12_GPIO_J15, + EXYNOS4X12_GPIO_J16, + EXYNOS4X12_GPIO_J17, + + /* GPIO_PART2_STARTS */ + EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 160 0xA0 */ + EXYNOS4X12_GPIO_K00 = 176, /* 176 0xB0 */ + EXYNOS4X12_GPIO_K01, + EXYNOS4X12_GPIO_K02, + EXYNOS4X12_GPIO_K03, + EXYNOS4X12_GPIO_K04, + EXYNOS4X12_GPIO_K05, + EXYNOS4X12_GPIO_K06, + EXYNOS4X12_GPIO_K07, + EXYNOS4X12_GPIO_K10, /* 184 0xB8 */ + EXYNOS4X12_GPIO_K11, + EXYNOS4X12_GPIO_K12, + EXYNOS4X12_GPIO_K13, + EXYNOS4X12_GPIO_K14, + EXYNOS4X12_GPIO_K15, + EXYNOS4X12_GPIO_K16, + EXYNOS4X12_GPIO_K17, + EXYNOS4X12_GPIO_K20, /* 192 0xC0 */ + EXYNOS4X12_GPIO_K21, + EXYNOS4X12_GPIO_K22, + EXYNOS4X12_GPIO_K23, + EXYNOS4X12_GPIO_K24, + EXYNOS4X12_GPIO_K25, + EXYNOS4X12_GPIO_K26, + EXYNOS4X12_GPIO_K27, + EXYNOS4X12_GPIO_K30, /* 200 0xC8 */ + EXYNOS4X12_GPIO_K31, + EXYNOS4X12_GPIO_K32, + EXYNOS4X12_GPIO_K33, + EXYNOS4X12_GPIO_K34, + EXYNOS4X12_GPIO_K35, + EXYNOS4X12_GPIO_K36, + EXYNOS4X12_GPIO_K37, + EXYNOS4X12_GPIO_L00, /* 208 0xD0 */ + EXYNOS4X12_GPIO_L01, + EXYNOS4X12_GPIO_L02, + EXYNOS4X12_GPIO_L03, + EXYNOS4X12_GPIO_L04, + EXYNOS4X12_GPIO_L05, + EXYNOS4X12_GPIO_L06, + EXYNOS4X12_GPIO_L07, + EXYNOS4X12_GPIO_L10, /* 216 0xD8 */ + EXYNOS4X12_GPIO_L11, + EXYNOS4X12_GPIO_L12, + EXYNOS4X12_GPIO_L13, + EXYNOS4X12_GPIO_L14, + EXYNOS4X12_GPIO_L15, + EXYNOS4X12_GPIO_L16, + EXYNOS4X12_GPIO_L17, + EXYNOS4X12_GPIO_L20, /* 224 0xE0 */ + EXYNOS4X12_GPIO_L21, + EXYNOS4X12_GPIO_L22, + EXYNOS4X12_GPIO_L23, + EXYNOS4X12_GPIO_L24, + EXYNOS4X12_GPIO_L25, + EXYNOS4X12_GPIO_L26, + EXYNOS4X12_GPIO_L27, + EXYNOS4X12_GPIO_Y00, /* 232 0xE8 */ + EXYNOS4X12_GPIO_Y01, + EXYNOS4X12_GPIO_Y02, + EXYNOS4X12_GPIO_Y03, + EXYNOS4X12_GPIO_Y04, + EXYNOS4X12_GPIO_Y05, + EXYNOS4X12_GPIO_Y06, + EXYNOS4X12_GPIO_Y07, + EXYNOS4X12_GPIO_Y10, /* 240 0xF0 */ + EXYNOS4X12_GPIO_Y11, + EXYNOS4X12_GPIO_Y12, + EXYNOS4X12_GPIO_Y13, + EXYNOS4X12_GPIO_Y14, + EXYNOS4X12_GPIO_Y15, + EXYNOS4X12_GPIO_Y16, + EXYNOS4X12_GPIO_Y17, + EXYNOS4X12_GPIO_Y20, /* 248 0xF8 */ + EXYNOS4X12_GPIO_Y21, + EXYNOS4X12_GPIO_Y22, + EXYNOS4X12_GPIO_Y23, + EXYNOS4X12_GPIO_Y24, + EXYNOS4X12_GPIO_Y25, + EXYNOS4X12_GPIO_Y26, + EXYNOS4X12_GPIO_Y27, + EXYNOS4X12_GPIO_Y30, /* 256 0x100 */ + EXYNOS4X12_GPIO_Y31, + EXYNOS4X12_GPIO_Y32, + EXYNOS4X12_GPIO_Y33, + EXYNOS4X12_GPIO_Y34, + EXYNOS4X12_GPIO_Y35, + EXYNOS4X12_GPIO_Y36, + EXYNOS4X12_GPIO_Y37, + EXYNOS4X12_GPIO_Y40, /* 264 0x108 */ + EXYNOS4X12_GPIO_Y41, + EXYNOS4X12_GPIO_Y42, + EXYNOS4X12_GPIO_Y43, + EXYNOS4X12_GPIO_Y44, + EXYNOS4X12_GPIO_Y45, + EXYNOS4X12_GPIO_Y46, + EXYNOS4X12_GPIO_Y47, + EXYNOS4X12_GPIO_Y50, /* 272 0x110 */ + EXYNOS4X12_GPIO_Y51, + EXYNOS4X12_GPIO_Y52, + EXYNOS4X12_GPIO_Y53, + EXYNOS4X12_GPIO_Y54, + EXYNOS4X12_GPIO_Y55, + EXYNOS4X12_GPIO_Y56, + EXYNOS4X12_GPIO_Y57, + EXYNOS4X12_GPIO_Y60, /* 280 0x118 */ + EXYNOS4X12_GPIO_Y61, + EXYNOS4X12_GPIO_Y62, + EXYNOS4X12_GPIO_Y63, + EXYNOS4X12_GPIO_Y64, + EXYNOS4X12_GPIO_Y65, + EXYNOS4X12_GPIO_Y66, + EXYNOS4X12_GPIO_Y67, + EXYNOS4X12_GPIO_M00 = 312, /* 312 0xF0 */ + EXYNOS4X12_GPIO_M01, + EXYNOS4X12_GPIO_M02, + EXYNOS4X12_GPIO_M03, + EXYNOS4X12_GPIO_M04, + EXYNOS4X12_GPIO_M05, + EXYNOS4X12_GPIO_M06, + EXYNOS4X12_GPIO_M07, + EXYNOS4X12_GPIO_M10, /* 320 0xF8 */ + EXYNOS4X12_GPIO_M11, + EXYNOS4X12_GPIO_M12, + EXYNOS4X12_GPIO_M13, + EXYNOS4X12_GPIO_M14, + EXYNOS4X12_GPIO_M15, + EXYNOS4X12_GPIO_M16, + EXYNOS4X12_GPIO_M17, + EXYNOS4X12_GPIO_M20, /* 328 0x100 */ + EXYNOS4X12_GPIO_M21, + EXYNOS4X12_GPIO_M22, + EXYNOS4X12_GPIO_M23, + EXYNOS4X12_GPIO_M24, + EXYNOS4X12_GPIO_M25, + EXYNOS4X12_GPIO_M26, + EXYNOS4X12_GPIO_M27, + EXYNOS4X12_GPIO_M30, /* 336 0x108 */ + EXYNOS4X12_GPIO_M31, + EXYNOS4X12_GPIO_M32, + EXYNOS4X12_GPIO_M33, + EXYNOS4X12_GPIO_M34, + EXYNOS4X12_GPIO_M35, + EXYNOS4X12_GPIO_M36, + EXYNOS4X12_GPIO_M37, + EXYNOS4X12_GPIO_M40, /* 344 0x110 */ + EXYNOS4X12_GPIO_M41, + EXYNOS4X12_GPIO_M42, + EXYNOS4X12_GPIO_M43, + EXYNOS4X12_GPIO_M44, + EXYNOS4X12_GPIO_M45, + EXYNOS4X12_GPIO_M46, + EXYNOS4X12_GPIO_M47, + EXYNOS4X12_GPIO_X00 = 928, /* 928 0x3A0 */ + EXYNOS4X12_GPIO_X01, + EXYNOS4X12_GPIO_X02, + EXYNOS4X12_GPIO_X03, + EXYNOS4X12_GPIO_X04, + EXYNOS4X12_GPIO_X05, + EXYNOS4X12_GPIO_X06, + EXYNOS4X12_GPIO_X07, + EXYNOS4X12_GPIO_X10, /* 936 0x3A8 */ + EXYNOS4X12_GPIO_X11, + EXYNOS4X12_GPIO_X12, + EXYNOS4X12_GPIO_X13, + EXYNOS4X12_GPIO_X14, + EXYNOS4X12_GPIO_X15, + EXYNOS4X12_GPIO_X16, + EXYNOS4X12_GPIO_X17, + EXYNOS4X12_GPIO_X20, /* 944 0x3B0 */ + EXYNOS4X12_GPIO_X21, + EXYNOS4X12_GPIO_X22, + EXYNOS4X12_GPIO_X23, + EXYNOS4X12_GPIO_X24, + EXYNOS4X12_GPIO_X25, + EXYNOS4X12_GPIO_X26, + EXYNOS4X12_GPIO_X27, + EXYNOS4X12_GPIO_X30, /* 952 0x3B8 */ + EXYNOS4X12_GPIO_X31, + EXYNOS4X12_GPIO_X32, + EXYNOS4X12_GPIO_X33, + EXYNOS4X12_GPIO_X34, + EXYNOS4X12_GPIO_X35, + EXYNOS4X12_GPIO_X36, + EXYNOS4X12_GPIO_X37, + + /* GPIO_PART3_STARTS */ + EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 960 0x3C0 */ + EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2, + EXYNOS4X12_GPIO_Z1, + EXYNOS4X12_GPIO_Z2, + EXYNOS4X12_GPIO_Z3, + EXYNOS4X12_GPIO_Z4, + EXYNOS4X12_GPIO_Z5, + EXYNOS4X12_GPIO_Z6, + EXYNOS4X12_GPIO_Z7, + + /* GPIO_PART4_STARTS */ + EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 968 0x3C8 */ + EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3, + EXYNOS4X12_GPIO_V01, + EXYNOS4X12_GPIO_V02, + EXYNOS4X12_GPIO_V03, + EXYNOS4X12_GPIO_V04, + EXYNOS4X12_GPIO_V05, + EXYNOS4X12_GPIO_V06, + EXYNOS4X12_GPIO_V07, + EXYNOS4X12_GPIO_V10, /* 976 0x3D0 */ + EXYNOS4X12_GPIO_V11, + EXYNOS4X12_GPIO_V12, + EXYNOS4X12_GPIO_V13, + EXYNOS4X12_GPIO_V14, + EXYNOS4X12_GPIO_V15, + EXYNOS4X12_GPIO_V16, + EXYNOS4X12_GPIO_V17, + EXYNOS4X12_GPIO_V20 = 992, /* 992 0x3E0 */ + EXYNOS4X12_GPIO_V21, + EXYNOS4X12_GPIO_V22, + EXYNOS4X12_GPIO_V23, + EXYNOS4X12_GPIO_V24, + EXYNOS4X12_GPIO_V25, + EXYNOS4X12_GPIO_V26, + EXYNOS4X12_GPIO_V27, + EXYNOS4X12_GPIO_V30 = 1000, /* 1000 0x3E8 */ + EXYNOS4X12_GPIO_V31, + EXYNOS4X12_GPIO_V32, + EXYNOS4X12_GPIO_V33, + EXYNOS4X12_GPIO_V34, + EXYNOS4X12_GPIO_V35, + EXYNOS4X12_GPIO_V36, + EXYNOS4X12_GPIO_V37, + EXYNOS4X12_GPIO_V40 = 1016, /* 1016 0x3F8 */ + EXYNOS4X12_GPIO_V41, + EXYNOS4X12_GPIO_V42, + EXYNOS4X12_GPIO_V43, + EXYNOS4X12_GPIO_V44, + EXYNOS4X12_GPIO_V45, + EXYNOS4X12_GPIO_V46, + EXYNOS4X12_GPIO_V47, + + EXYNOS4X12_GPIO_MAX_PORT }; -struct exynos4x12_gpio_part3 { - struct s5p_gpio_bank z; +enum exynos5_gpio_pin { + /* GPIO_PART1_STARTS */ + EXYNOS5_GPIO_A00, /* 0 */ + EXYNOS5_GPIO_A01, + EXYNOS5_GPIO_A02, + EXYNOS5_GPIO_A03, + EXYNOS5_GPIO_A04, + EXYNOS5_GPIO_A05, + EXYNOS5_GPIO_A06, + EXYNOS5_GPIO_A07, + EXYNOS5_GPIO_A10, /* 8 */ + EXYNOS5_GPIO_A11, + EXYNOS5_GPIO_A12, + EXYNOS5_GPIO_A13, + EXYNOS5_GPIO_A14, + EXYNOS5_GPIO_A15, + EXYNOS5_GPIO_A16, + EXYNOS5_GPIO_A17, + EXYNOS5_GPIO_A20, /* 16 0x10 */ + EXYNOS5_GPIO_A21, + EXYNOS5_GPIO_A22, + EXYNOS5_GPIO_A23, + EXYNOS5_GPIO_A24, + EXYNOS5_GPIO_A25, + EXYNOS5_GPIO_A26, + EXYNOS5_GPIO_A27, + EXYNOS5_GPIO_B00, /* 24 0x18 */ + EXYNOS5_GPIO_B01, + EXYNOS5_GPIO_B02, + EXYNOS5_GPIO_B03, + EXYNOS5_GPIO_B04, + EXYNOS5_GPIO_B05, + EXYNOS5_GPIO_B06, + EXYNOS5_GPIO_B07, + EXYNOS5_GPIO_B10, /* 32 0x20 */ + EXYNOS5_GPIO_B11, + EXYNOS5_GPIO_B12, + EXYNOS5_GPIO_B13, + EXYNOS5_GPIO_B14, + EXYNOS5_GPIO_B15, + EXYNOS5_GPIO_B16, + EXYNOS5_GPIO_B17, + EXYNOS5_GPIO_B20, /* 40 0x28 */ + EXYNOS5_GPIO_B21, + EXYNOS5_GPIO_B22, + EXYNOS5_GPIO_B23, + EXYNOS5_GPIO_B24, + EXYNOS5_GPIO_B25, + EXYNOS5_GPIO_B26, + EXYNOS5_GPIO_B27, + EXYNOS5_GPIO_B30, /* 48 0x39 */ + EXYNOS5_GPIO_B31, + EXYNOS5_GPIO_B32, + EXYNOS5_GPIO_B33, + EXYNOS5_GPIO_B34, + EXYNOS5_GPIO_B35, + EXYNOS5_GPIO_B36, + EXYNOS5_GPIO_B37, + EXYNOS5_GPIO_C00, /* 56 0x38 */ + EXYNOS5_GPIO_C01, + EXYNOS5_GPIO_C02, + EXYNOS5_GPIO_C03, + EXYNOS5_GPIO_C04, + EXYNOS5_GPIO_C05, + EXYNOS5_GPIO_C06, + EXYNOS5_GPIO_C07, + EXYNOS5_GPIO_C10, /* 64 0x40 */ + EXYNOS5_GPIO_C11, + EXYNOS5_GPIO_C12, + EXYNOS5_GPIO_C13, + EXYNOS5_GPIO_C14, + EXYNOS5_GPIO_C15, + EXYNOS5_GPIO_C16, + EXYNOS5_GPIO_C17, + EXYNOS5_GPIO_C20, /* 72 0x48 */ + EXYNOS5_GPIO_C21, + EXYNOS5_GPIO_C22, + EXYNOS5_GPIO_C23, + EXYNOS5_GPIO_C24, + EXYNOS5_GPIO_C25, + EXYNOS5_GPIO_C26, + EXYNOS5_GPIO_C27, + EXYNOS5_GPIO_C30, /* 80 0x50 */ + EXYNOS5_GPIO_C31, + EXYNOS5_GPIO_C32, + EXYNOS5_GPIO_C33, + EXYNOS5_GPIO_C34, + EXYNOS5_GPIO_C35, + EXYNOS5_GPIO_C36, + EXYNOS5_GPIO_C37, + EXYNOS5_GPIO_D00, /* 88 0x58 */ + EXYNOS5_GPIO_D01, + EXYNOS5_GPIO_D02, + EXYNOS5_GPIO_D03, + EXYNOS5_GPIO_D04, + EXYNOS5_GPIO_D05, + EXYNOS5_GPIO_D06, + EXYNOS5_GPIO_D07, + EXYNOS5_GPIO_D10, /* 96 0x60 */ + EXYNOS5_GPIO_D11, + EXYNOS5_GPIO_D12, + EXYNOS5_GPIO_D13, + EXYNOS5_GPIO_D14, + EXYNOS5_GPIO_D15, + EXYNOS5_GPIO_D16, + EXYNOS5_GPIO_D17, + EXYNOS5_GPIO_Y00, /* 104 0x68 */ + EXYNOS5_GPIO_Y01, + EXYNOS5_GPIO_Y02, + EXYNOS5_GPIO_Y03, + EXYNOS5_GPIO_Y04, + EXYNOS5_GPIO_Y05, + EXYNOS5_GPIO_Y06, + EXYNOS5_GPIO_Y07, + EXYNOS5_GPIO_Y10, /* 112 0x70 */ + EXYNOS5_GPIO_Y11, + EXYNOS5_GPIO_Y12, + EXYNOS5_GPIO_Y13, + EXYNOS5_GPIO_Y14, + EXYNOS5_GPIO_Y15, + EXYNOS5_GPIO_Y16, + EXYNOS5_GPIO_Y17, + EXYNOS5_GPIO_Y20, /* 120 0x78 */ + EXYNOS5_GPIO_Y21, + EXYNOS5_GPIO_Y22, + EXYNOS5_GPIO_Y23, + EXYNOS5_GPIO_Y24, + EXYNOS5_GPIO_Y25, + EXYNOS5_GPIO_Y26, + EXYNOS5_GPIO_Y27, + EXYNOS5_GPIO_Y30, /* 128 0x80 */ + EXYNOS5_GPIO_Y31, + EXYNOS5_GPIO_Y32, + EXYNOS5_GPIO_Y33, + EXYNOS5_GPIO_Y34, + EXYNOS5_GPIO_Y35, + EXYNOS5_GPIO_Y36, + EXYNOS5_GPIO_Y37, + EXYNOS5_GPIO_Y40, /* 136 0x88 */ + EXYNOS5_GPIO_Y41, + EXYNOS5_GPIO_Y42, + EXYNOS5_GPIO_Y43, + EXYNOS5_GPIO_Y44, + EXYNOS5_GPIO_Y45, + EXYNOS5_GPIO_Y46, + EXYNOS5_GPIO_Y47, + EXYNOS5_GPIO_Y50, /* 144 0x90 */ + EXYNOS5_GPIO_Y51, + EXYNOS5_GPIO_Y52, + EXYNOS5_GPIO_Y53, + EXYNOS5_GPIO_Y54, + EXYNOS5_GPIO_Y55, + EXYNOS5_GPIO_Y56, + EXYNOS5_GPIO_Y57, + EXYNOS5_GPIO_Y60, /* 152 0x98 */ + EXYNOS5_GPIO_Y61, + EXYNOS5_GPIO_Y62, + EXYNOS5_GPIO_Y63, + EXYNOS5_GPIO_Y64, + EXYNOS5_GPIO_Y65, + EXYNOS5_GPIO_Y66, + EXYNOS5_GPIO_Y67, + + /* GPIO_PART2_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_1, /* 160 0xa0 */ + EXYNOS5_GPIO_C40 = EXYNOS5_GPIO_MAX_PORT_PART_1, + EXYNOS5_GPIO_C41, + EXYNOS5_GPIO_C42, + EXYNOS5_GPIO_C43, + EXYNOS5_GPIO_C44, + EXYNOS5_GPIO_C45, + EXYNOS5_GPIO_C46, + EXYNOS5_GPIO_C47, + + /* GPIO_PART3_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_2, /* 168 0xa8 */ + EXYNOS5_GPIO_X00 = EXYNOS5_GPIO_MAX_PORT_PART_2, + EXYNOS5_GPIO_X01, + EXYNOS5_GPIO_X02, + EXYNOS5_GPIO_X03, + EXYNOS5_GPIO_X04, + EXYNOS5_GPIO_X05, + EXYNOS5_GPIO_X06, + EXYNOS5_GPIO_X07, + EXYNOS5_GPIO_X10, /* 176 0xb0 */ + EXYNOS5_GPIO_X11, + EXYNOS5_GPIO_X12, + EXYNOS5_GPIO_X13, + EXYNOS5_GPIO_X14, + EXYNOS5_GPIO_X15, + EXYNOS5_GPIO_X16, + EXYNOS5_GPIO_X17, + EXYNOS5_GPIO_X20, /* 184 0xb8 */ + EXYNOS5_GPIO_X21, + EXYNOS5_GPIO_X22, + EXYNOS5_GPIO_X23, + EXYNOS5_GPIO_X24, + EXYNOS5_GPIO_X25, + EXYNOS5_GPIO_X26, + EXYNOS5_GPIO_X27, + EXYNOS5_GPIO_X30, /* 192 0xc0 */ + EXYNOS5_GPIO_X31, + EXYNOS5_GPIO_X32, + EXYNOS5_GPIO_X33, + EXYNOS5_GPIO_X34, + EXYNOS5_GPIO_X35, + EXYNOS5_GPIO_X36, + EXYNOS5_GPIO_X37, + + /* GPIO_PART4_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_3, /* 200 0xc8 */ + EXYNOS5_GPIO_E00 = EXYNOS5_GPIO_MAX_PORT_PART_3, + EXYNOS5_GPIO_E01, + EXYNOS5_GPIO_E02, + EXYNOS5_GPIO_E03, + EXYNOS5_GPIO_E04, + EXYNOS5_GPIO_E05, + EXYNOS5_GPIO_E06, + EXYNOS5_GPIO_E07, + EXYNOS5_GPIO_E10, /* 208 0xd0 */ + EXYNOS5_GPIO_E11, + EXYNOS5_GPIO_E12, + EXYNOS5_GPIO_E13, + EXYNOS5_GPIO_E14, + EXYNOS5_GPIO_E15, + EXYNOS5_GPIO_E16, + EXYNOS5_GPIO_E17, + EXYNOS5_GPIO_F00, /* 216 0xd8 */ + EXYNOS5_GPIO_F01, + EXYNOS5_GPIO_F02, + EXYNOS5_GPIO_F03, + EXYNOS5_GPIO_F04, + EXYNOS5_GPIO_F05, + EXYNOS5_GPIO_F06, + EXYNOS5_GPIO_F07, + EXYNOS5_GPIO_F10, /* 224 0xe0 */ + EXYNOS5_GPIO_F11, + EXYNOS5_GPIO_F12, + EXYNOS5_GPIO_F13, + EXYNOS5_GPIO_F14, + EXYNOS5_GPIO_F15, + EXYNOS5_GPIO_F16, + EXYNOS5_GPIO_F17, + EXYNOS5_GPIO_G00, /* 232 0xe8 */ + EXYNOS5_GPIO_G01, + EXYNOS5_GPIO_G02, + EXYNOS5_GPIO_G03, + EXYNOS5_GPIO_G04, + EXYNOS5_GPIO_G05, + EXYNOS5_GPIO_G06, + EXYNOS5_GPIO_G07, + EXYNOS5_GPIO_G10, /* 240 0xf0 */ + EXYNOS5_GPIO_G11, + EXYNOS5_GPIO_G12, + EXYNOS5_GPIO_G13, + EXYNOS5_GPIO_G14, + EXYNOS5_GPIO_G15, + EXYNOS5_GPIO_G16, + EXYNOS5_GPIO_G17, + EXYNOS5_GPIO_G20, /* 248 0xf8 */ + EXYNOS5_GPIO_G21, + EXYNOS5_GPIO_G22, + EXYNOS5_GPIO_G23, + EXYNOS5_GPIO_G24, + EXYNOS5_GPIO_G25, + EXYNOS5_GPIO_G26, + EXYNOS5_GPIO_G27, + EXYNOS5_GPIO_H00, /* 256 0x100 */ + EXYNOS5_GPIO_H01, + EXYNOS5_GPIO_H02, + EXYNOS5_GPIO_H03, + EXYNOS5_GPIO_H04, + EXYNOS5_GPIO_H05, + EXYNOS5_GPIO_H06, + EXYNOS5_GPIO_H07, + EXYNOS5_GPIO_H10, /* 264 0x108 */ + EXYNOS5_GPIO_H11, + EXYNOS5_GPIO_H12, + EXYNOS5_GPIO_H13, + EXYNOS5_GPIO_H14, + EXYNOS5_GPIO_H15, + EXYNOS5_GPIO_H16, + EXYNOS5_GPIO_H17, + + /* GPIO_PART4_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_4, /* 272 0x110 */ + EXYNOS5_GPIO_V00 = EXYNOS5_GPIO_MAX_PORT_PART_4, + EXYNOS5_GPIO_V01, + EXYNOS5_GPIO_V02, + EXYNOS5_GPIO_V03, + EXYNOS5_GPIO_V04, + EXYNOS5_GPIO_V05, + EXYNOS5_GPIO_V06, + EXYNOS5_GPIO_V07, + EXYNOS5_GPIO_V10, /* 280 0x118 */ + EXYNOS5_GPIO_V11, + EXYNOS5_GPIO_V12, + EXYNOS5_GPIO_V13, + EXYNOS5_GPIO_V14, + EXYNOS5_GPIO_V15, + EXYNOS5_GPIO_V16, + EXYNOS5_GPIO_V17, + + /* GPIO_PART5_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_5, /* 288 0x120 */ + EXYNOS5_GPIO_V20 = EXYNOS5_GPIO_MAX_PORT_PART_5, + EXYNOS5_GPIO_V21, + EXYNOS5_GPIO_V22, + EXYNOS5_GPIO_V23, + EXYNOS5_GPIO_V24, + EXYNOS5_GPIO_V25, + EXYNOS5_GPIO_V26, + EXYNOS5_GPIO_V27, + EXYNOS5_GPIO_V30, /* 296 0x128 */ + EXYNOS5_GPIO_V31, + EXYNOS5_GPIO_V32, + EXYNOS5_GPIO_V33, + EXYNOS5_GPIO_V34, + EXYNOS5_GPIO_V35, + EXYNOS5_GPIO_V36, + EXYNOS5_GPIO_V37, + + /* GPIO_PART6_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_6, /* 304 0x130 */ + EXYNOS5_GPIO_V40 = EXYNOS5_GPIO_MAX_PORT_PART_6, + EXYNOS5_GPIO_V41, + EXYNOS5_GPIO_V42, + EXYNOS5_GPIO_V43, + EXYNOS5_GPIO_V44, + EXYNOS5_GPIO_V45, + EXYNOS5_GPIO_V46, + EXYNOS5_GPIO_V47, + + /* GPIO_PART7_STARTS */ /* 312 0x138 */ + EXYNOS5_GPIO_MAX_PORT_PART_7, + EXYNOS5_GPIO_Z0 = EXYNOS5_GPIO_MAX_PORT_PART_7, + EXYNOS5_GPIO_Z1, + EXYNOS5_GPIO_Z2, + EXYNOS5_GPIO_Z3, + EXYNOS5_GPIO_Z4, + EXYNOS5_GPIO_Z5, + EXYNOS5_GPIO_Z6, + EXYNOS5_GPIO_MAX_PORT }; -struct exynos4x12_gpio_part4 { - struct s5p_gpio_bank v0; - struct s5p_gpio_bank v1; - struct s5p_gpio_bank res1[0x1]; - struct s5p_gpio_bank v2; - struct s5p_gpio_bank v3; - struct s5p_gpio_bank res2[0x1]; - struct s5p_gpio_bank v4; +enum exynos5420_gpio_pin { + /* GPIO_PART1_STARTS */ + EXYNOS5420_GPIO_A00, /* 0 */ + EXYNOS5420_GPIO_A01, + EXYNOS5420_GPIO_A02, + EXYNOS5420_GPIO_A03, + EXYNOS5420_GPIO_A04, + EXYNOS5420_GPIO_A05, + EXYNOS5420_GPIO_A06, + EXYNOS5420_GPIO_A07, + EXYNOS5420_GPIO_A10, /* 8 */ + EXYNOS5420_GPIO_A11, + EXYNOS5420_GPIO_A12, + EXYNOS5420_GPIO_A13, + EXYNOS5420_GPIO_A14, + EXYNOS5420_GPIO_A15, + EXYNOS5420_GPIO_A16, + EXYNOS5420_GPIO_A17, + EXYNOS5420_GPIO_A20, /* 16 0x10 */ + EXYNOS5420_GPIO_A21, + EXYNOS5420_GPIO_A22, + EXYNOS5420_GPIO_A23, + EXYNOS5420_GPIO_A24, + EXYNOS5420_GPIO_A25, + EXYNOS5420_GPIO_A26, + EXYNOS5420_GPIO_A27, + EXYNOS5420_GPIO_B00, /* 24 0x18 */ + EXYNOS5420_GPIO_B01, + EXYNOS5420_GPIO_B02, + EXYNOS5420_GPIO_B03, + EXYNOS5420_GPIO_B04, + EXYNOS5420_GPIO_B05, + EXYNOS5420_GPIO_B06, + EXYNOS5420_GPIO_B07, + EXYNOS5420_GPIO_B10, /* 32 0x20 */ + EXYNOS5420_GPIO_B11, + EXYNOS5420_GPIO_B12, + EXYNOS5420_GPIO_B13, + EXYNOS5420_GPIO_B14, + EXYNOS5420_GPIO_B15, + EXYNOS5420_GPIO_B16, + EXYNOS5420_GPIO_B17, + EXYNOS5420_GPIO_B20, /* 40 0x28 */ + EXYNOS5420_GPIO_B21, + EXYNOS5420_GPIO_B22, + EXYNOS5420_GPIO_B23, + EXYNOS5420_GPIO_B24, + EXYNOS5420_GPIO_B25, + EXYNOS5420_GPIO_B26, + EXYNOS5420_GPIO_B27, + EXYNOS5420_GPIO_B30, /* 48 0x30 */ + EXYNOS5420_GPIO_B31, + EXYNOS5420_GPIO_B32, + EXYNOS5420_GPIO_B33, + EXYNOS5420_GPIO_B34, + EXYNOS5420_GPIO_B35, + EXYNOS5420_GPIO_B36, + EXYNOS5420_GPIO_B37, + EXYNOS5420_GPIO_B40, /* 56 0x38 */ + EXYNOS5420_GPIO_B41, + EXYNOS5420_GPIO_B42, + EXYNOS5420_GPIO_B43, + EXYNOS5420_GPIO_B44, + EXYNOS5420_GPIO_B45, + EXYNOS5420_GPIO_B46, + EXYNOS5420_GPIO_B47, + EXYNOS5420_GPIO_H00, /* 64 0x40 */ + EXYNOS5420_GPIO_H01, + EXYNOS5420_GPIO_H02, + EXYNOS5420_GPIO_H03, + EXYNOS5420_GPIO_H04, + EXYNOS5420_GPIO_H05, + EXYNOS5420_GPIO_H06, + EXYNOS5420_GPIO_H07, + + /* GPIO PART 2 STARTS*/ + EXYNOS5420_GPIO_MAX_PORT_PART_1,/* 72 0x48 */ + EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1, + EXYNOS5420_GPIO_Y71, + EXYNOS5420_GPIO_Y72, + EXYNOS5420_GPIO_Y73, + EXYNOS5420_GPIO_Y74, + EXYNOS5420_GPIO_Y75, + EXYNOS5420_GPIO_Y76, + EXYNOS5420_GPIO_Y77, + + /* GPIO PART 3 STARTS*/ + EXYNOS5420_GPIO_MAX_PORT_PART_2,/* 80 0x50 */ + EXYNOS5420_GPIO_X00 = EXYNOS5420_GPIO_MAX_PORT_PART_2, + EXYNOS5420_GPIO_X01, + EXYNOS5420_GPIO_X02, + EXYNOS5420_GPIO_X03, + EXYNOS5420_GPIO_X04, + EXYNOS5420_GPIO_X05, + EXYNOS5420_GPIO_X06, + EXYNOS5420_GPIO_X07, + EXYNOS5420_GPIO_X10, /* 88 0x58 */ + EXYNOS5420_GPIO_X11, + EXYNOS5420_GPIO_X12, + EXYNOS5420_GPIO_X13, + EXYNOS5420_GPIO_X14, + EXYNOS5420_GPIO_X15, + EXYNOS5420_GPIO_X16, + EXYNOS5420_GPIO_X17, + EXYNOS5420_GPIO_X20, /* 96 0x60 */ + EXYNOS5420_GPIO_X21, + EXYNOS5420_GPIO_X22, + EXYNOS5420_GPIO_X23, + EXYNOS5420_GPIO_X24, + EXYNOS5420_GPIO_X25, + EXYNOS5420_GPIO_X26, + EXYNOS5420_GPIO_X27, + EXYNOS5420_GPIO_X30, /* 104 0x68 */ + EXYNOS5420_GPIO_X31, + EXYNOS5420_GPIO_X32, + EXYNOS5420_GPIO_X33, + EXYNOS5420_GPIO_X34, + EXYNOS5420_GPIO_X35, + EXYNOS5420_GPIO_X36, + EXYNOS5420_GPIO_X37, + + /* GPIO PART 4 STARTS*/ + EXYNOS5420_GPIO_MAX_PORT_PART_3,/* 112 0x70 */ + EXYNOS5420_GPIO_C00 = EXYNOS5420_GPIO_MAX_PORT_PART_3, + EXYNOS5420_GPIO_C01, + EXYNOS5420_GPIO_C02, + EXYNOS5420_GPIO_C03, + EXYNOS5420_GPIO_C04, + EXYNOS5420_GPIO_C05, + EXYNOS5420_GPIO_C06, + EXYNOS5420_GPIO_C07, + EXYNOS5420_GPIO_C10, /* 120 0x78 */ + EXYNOS5420_GPIO_C11, + EXYNOS5420_GPIO_C12, + EXYNOS5420_GPIO_C13, + EXYNOS5420_GPIO_C14, + EXYNOS5420_GPIO_C15, + EXYNOS5420_GPIO_C16, + EXYNOS5420_GPIO_C17, + EXYNOS5420_GPIO_C20, /* 128 0x80 */ + EXYNOS5420_GPIO_C21, + EXYNOS5420_GPIO_C22, + EXYNOS5420_GPIO_C23, + EXYNOS5420_GPIO_C24, + EXYNOS5420_GPIO_C25, + EXYNOS5420_GPIO_C26, + EXYNOS5420_GPIO_C27, + EXYNOS5420_GPIO_C30, /* 136 0x88 */ + EXYNOS5420_GPIO_C31, + EXYNOS5420_GPIO_C32, + EXYNOS5420_GPIO_C33, + EXYNOS5420_GPIO_C34, + EXYNOS5420_GPIO_C35, + EXYNOS5420_GPIO_C36, + EXYNOS5420_GPIO_C37, + EXYNOS5420_GPIO_C40, /* 144 0x90 */ + EXYNOS5420_GPIO_C41, + EXYNOS5420_GPIO_C42, + EXYNOS5420_GPIO_C43, + EXYNOS5420_GPIO_C44, + EXYNOS5420_GPIO_C45, + EXYNOS5420_GPIO_C46, + EXYNOS5420_GPIO_C47, + EXYNOS5420_GPIO_D10, /* 152 0x98 */ + EXYNOS5420_GPIO_D11, + EXYNOS5420_GPIO_D12, + EXYNOS5420_GPIO_D13, + EXYNOS5420_GPIO_D14, + EXYNOS5420_GPIO_D15, + EXYNOS5420_GPIO_D16, + EXYNOS5420_GPIO_D17, + EXYNOS5420_GPIO_Y00, /* 160 0xa0 */ + EXYNOS5420_GPIO_Y01, + EXYNOS5420_GPIO_Y02, + EXYNOS5420_GPIO_Y03, + EXYNOS5420_GPIO_Y04, + EXYNOS5420_GPIO_Y05, + EXYNOS5420_GPIO_Y06, + EXYNOS5420_GPIO_Y07, + EXYNOS5420_GPIO_Y10, /* 168 0xa8 */ + EXYNOS5420_GPIO_Y11, + EXYNOS5420_GPIO_Y12, + EXYNOS5420_GPIO_Y13, + EXYNOS5420_GPIO_Y14, + EXYNOS5420_GPIO_Y15, + EXYNOS5420_GPIO_Y16, + EXYNOS5420_GPIO_Y17, + EXYNOS5420_GPIO_Y20, /* 176 0xb0 */ + EXYNOS5420_GPIO_Y21, + EXYNOS5420_GPIO_Y22, + EXYNOS5420_GPIO_Y23, + EXYNOS5420_GPIO_Y24, + EXYNOS5420_GPIO_Y25, + EXYNOS5420_GPIO_Y26, + EXYNOS5420_GPIO_Y27, + EXYNOS5420_GPIO_Y30, /* 184 0xb8 */ + EXYNOS5420_GPIO_Y31, + EXYNOS5420_GPIO_Y32, + EXYNOS5420_GPIO_Y33, + EXYNOS5420_GPIO_Y34, + EXYNOS5420_GPIO_Y35, + EXYNOS5420_GPIO_Y36, + EXYNOS5420_GPIO_Y37, + EXYNOS5420_GPIO_Y40, /* 192 0xc0 */ + EXYNOS5420_GPIO_Y41, + EXYNOS5420_GPIO_Y42, + EXYNOS5420_GPIO_Y43, + EXYNOS5420_GPIO_Y44, + EXYNOS5420_GPIO_Y45, + EXYNOS5420_GPIO_Y46, + EXYNOS5420_GPIO_Y47, + EXYNOS5420_GPIO_Y50, /* 200 0xc8 */ + EXYNOS5420_GPIO_Y51, + EXYNOS5420_GPIO_Y52, + EXYNOS5420_GPIO_Y53, + EXYNOS5420_GPIO_Y54, + EXYNOS5420_GPIO_Y55, + EXYNOS5420_GPIO_Y56, + EXYNOS5420_GPIO_Y57, + EXYNOS5420_GPIO_Y60, /* 208 0xd0 */ + EXYNOS5420_GPIO_Y61, + EXYNOS5420_GPIO_Y62, + EXYNOS5420_GPIO_Y63, + EXYNOS5420_GPIO_Y64, + EXYNOS5420_GPIO_Y65, + EXYNOS5420_GPIO_Y66, + EXYNOS5420_GPIO_Y67, + + /* GPIO_PART5_STARTS */ + EXYNOS5420_GPIO_MAX_PORT_PART_4,/* 216 0xd8 */ + EXYNOS5420_GPIO_E00 = EXYNOS5420_GPIO_MAX_PORT_PART_4, + EXYNOS5420_GPIO_E01, + EXYNOS5420_GPIO_E02, + EXYNOS5420_GPIO_E03, + EXYNOS5420_GPIO_E04, + EXYNOS5420_GPIO_E05, + EXYNOS5420_GPIO_E06, + EXYNOS5420_GPIO_E07, + EXYNOS5420_GPIO_E10, /* 224 0xe0 */ + EXYNOS5420_GPIO_E11, + EXYNOS5420_GPIO_E12, + EXYNOS5420_GPIO_E13, + EXYNOS5420_GPIO_E14, + EXYNOS5420_GPIO_E15, + EXYNOS5420_GPIO_E16, + EXYNOS5420_GPIO_E17, + EXYNOS5420_GPIO_F00, /* 232 0xe8 */ + EXYNOS5420_GPIO_F01, + EXYNOS5420_GPIO_F02, + EXYNOS5420_GPIO_F03, + EXYNOS5420_GPIO_F04, + EXYNOS5420_GPIO_F05, + EXYNOS5420_GPIO_F06, + EXYNOS5420_GPIO_F07, + EXYNOS5420_GPIO_F10, /* 240 0xf0 */ + EXYNOS5420_GPIO_F11, + EXYNOS5420_GPIO_F12, + EXYNOS5420_GPIO_F13, + EXYNOS5420_GPIO_F14, + EXYNOS5420_GPIO_F15, + EXYNOS5420_GPIO_F16, + EXYNOS5420_GPIO_F17, + EXYNOS5420_GPIO_G00, /* 248 0xf8 */ + EXYNOS5420_GPIO_G01, + EXYNOS5420_GPIO_G02, + EXYNOS5420_GPIO_G03, + EXYNOS5420_GPIO_G04, + EXYNOS5420_GPIO_G05, + EXYNOS5420_GPIO_G06, + EXYNOS5420_GPIO_G07, + EXYNOS5420_GPIO_G10, /* 256 0x100 */ + EXYNOS5420_GPIO_G11, + EXYNOS5420_GPIO_G12, + EXYNOS5420_GPIO_G13, + EXYNOS5420_GPIO_G14, + EXYNOS5420_GPIO_G15, + EXYNOS5420_GPIO_G16, + EXYNOS5420_GPIO_G17, + EXYNOS5420_GPIO_G20, /* 264 0x108 */ + EXYNOS5420_GPIO_G21, + EXYNOS5420_GPIO_G22, + EXYNOS5420_GPIO_G23, + EXYNOS5420_GPIO_G24, + EXYNOS5420_GPIO_G25, + EXYNOS5420_GPIO_G26, + EXYNOS5420_GPIO_G27, + EXYNOS5420_GPIO_J40, /* 272 0x110 */ + EXYNOS5420_GPIO_J41, + EXYNOS5420_GPIO_J42, + EXYNOS5420_GPIO_J43, + EXYNOS5420_GPIO_J44, + EXYNOS5420_GPIO_J45, + EXYNOS5420_GPIO_J46, + EXYNOS5420_GPIO_J47, + + /* GPIO_PART6_STARTS */ + EXYNOS5420_GPIO_MAX_PORT_PART_5,/* 280 0x118 */ + EXYNOS5420_GPIO_Z0 = EXYNOS5420_GPIO_MAX_PORT_PART_5, + EXYNOS5420_GPIO_Z1, + EXYNOS5420_GPIO_Z2, + EXYNOS5420_GPIO_Z3, + EXYNOS5420_GPIO_Z4, + EXYNOS5420_GPIO_Z5, + EXYNOS5420_GPIO_Z6, + EXYNOS5420_GPIO_MAX_PORT }; -struct exynos5420_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank a2; - struct s5p_gpio_bank b0; - struct s5p_gpio_bank b1; - struct s5p_gpio_bank b2; - struct s5p_gpio_bank b3; - struct s5p_gpio_bank b4; - struct s5p_gpio_bank h0; +struct gpio_info { + unsigned int reg_addr; /* Address of register for this part */ + unsigned int max_gpio; /* Maximum GPIO in this part */ }; -struct exynos5420_gpio_part2 { - struct s5p_gpio_bank y7; /* 0x1340_0000 */ - struct s5p_gpio_bank res[0x5f]; /* */ - struct s5p_gpio_bank x0; /* 0x1340_0C00 */ - struct s5p_gpio_bank x1; /* 0x1340_0C20 */ - struct s5p_gpio_bank x2; /* 0x1340_0C40 */ - struct s5p_gpio_bank x3; /* 0x1340_0C60 */ +#define EXYNOS4_GPIO_NUM_PARTS 3 +static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = { + { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 }, + { EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 }, + { EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT }, }; -struct exynos5420_gpio_part3 { - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank c2; - struct s5p_gpio_bank c3; - struct s5p_gpio_bank c4; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; +#define EXYNOS4X12_GPIO_NUM_PARTS 4 +static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = { + { EXYNOS4X12_GPIO_PART1_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_1 }, + { EXYNOS4X12_GPIO_PART2_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_2 }, + { EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 }, + { EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT }, }; -struct exynos5420_gpio_part4 { - struct s5p_gpio_bank e0; /* 0x1400_0000 */ - struct s5p_gpio_bank e1; /* 0x1400_0020 */ - struct s5p_gpio_bank f0; /* 0x1400_0040 */ - struct s5p_gpio_bank f1; /* 0x1400_0060 */ - struct s5p_gpio_bank g0; /* 0x1400_0080 */ - struct s5p_gpio_bank g1; /* 0x1400_00A0 */ - struct s5p_gpio_bank g2; /* 0x1400_00C0 */ - struct s5p_gpio_bank j4; /* 0x1400_00E0 */ +#define EXYNOS5_GPIO_NUM_PARTS 8 +static struct gpio_info exynos5_gpio_data[EXYNOS5_GPIO_NUM_PARTS] = { + { EXYNOS5_GPIO_PART1_BASE, EXYNOS5_GPIO_MAX_PORT_PART_1 }, + { EXYNOS5_GPIO_PART2_BASE, EXYNOS5_GPIO_MAX_PORT_PART_2 }, + { EXYNOS5_GPIO_PART3_BASE, EXYNOS5_GPIO_MAX_PORT_PART_3 }, + { EXYNOS5_GPIO_PART4_BASE, EXYNOS5_GPIO_MAX_PORT_PART_4 }, + { EXYNOS5_GPIO_PART5_BASE, EXYNOS5_GPIO_MAX_PORT_PART_5 }, + { EXYNOS5_GPIO_PART6_BASE, EXYNOS5_GPIO_MAX_PORT_PART_6 }, + { EXYNOS5_GPIO_PART7_BASE, EXYNOS5_GPIO_MAX_PORT_PART_7 }, + { EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT }, }; -struct exynos5420_gpio_part5 { - struct s5p_gpio_bank z0; /* 0x0386_0000 */ +#define EXYNOS5420_GPIO_NUM_PARTS 6 +static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = { + { EXYNOS5420_GPIO_PART1_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_1 }, + { EXYNOS5420_GPIO_PART2_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_2 }, + { EXYNOS5420_GPIO_PART3_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_3 }, + { EXYNOS5420_GPIO_PART4_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_4 }, + { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_5 }, + { EXYNOS5420_GPIO_PART6_BASE, EXYNOS5420_GPIO_MAX_PORT }, }; -struct exynos5_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank a2; - struct s5p_gpio_bank b0; - struct s5p_gpio_bank b1; - struct s5p_gpio_bank b2; - struct s5p_gpio_bank b3; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank c2; - struct s5p_gpio_bank c3; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; - struct s5p_gpio_bank res1[0x3]; - struct s5p_gpio_bank c4; - struct s5p_gpio_bank res2[0x48]; - struct s5p_gpio_bank x0; - struct s5p_gpio_bank x1; - struct s5p_gpio_bank x2; - struct s5p_gpio_bank x3; +static inline struct gpio_info *get_gpio_data(void) +{ + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + return exynos5420_gpio_data; + else + return exynos5_gpio_data; + } else if (cpu_is_exynos4()) { + if (proid_is_exynos4412()) + return exynos4x12_gpio_data; + else + return exynos4_gpio_data; + } + + return NULL; +} + +static inline unsigned int get_bank_num(void) +{ + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + return EXYNOS5420_GPIO_NUM_PARTS; + else + return EXYNOS5_GPIO_NUM_PARTS; + } else if (cpu_is_exynos4()) { + if (proid_is_exynos4412()) + return EXYNOS4X12_GPIO_NUM_PARTS; + else + return EXYNOS4_GPIO_NUM_PARTS; + } + + return 0; +} + +/* + * This structure helps mapping symbolic GPIO names into indices from + * exynos5_gpio_pin/exynos5420_gpio_pin enums. + * + * By convention, symbolic GPIO name is defined as follows: + * + * g[p]<bank><set><bit>, where + * p is optional + * <bank> - a single character bank name, as defined by the SOC + * <set> - a single digit set number + * <bit> - bit number within the set (in 0..7 range). + * + * <set><bit> essentially form an octal number of the GPIO pin within the bank + * space. On the 5420 architecture some banks' sets do not start not from zero + * ('d' starts from 1 and 'j' starts from 4). To compensate for that and + * maintain flat number space withoout holes, those banks use offsets to be + * deducted from the pin number. + */ +struct gpio_name_num_table { + char bank; /* bank name symbol */ + unsigned int bank_size; /* total number of pins in the bank */ + char bank_offset; /* offset of the first bank's pin */ + unsigned int base; /* index of the first bank's pin in the enum */ }; -struct exynos5_gpio_part2 { - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank g0; - struct s5p_gpio_bank g1; - struct s5p_gpio_bank g2; - struct s5p_gpio_bank h0; - struct s5p_gpio_bank h1; +#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base } +static const struct gpio_name_num_table exynos4_gpio_table[] = { + GPIO_ENTRY('a', EXYNOS4_GPIO_A00, EXYNOS4_GPIO_B0, 0), + GPIO_ENTRY('b', EXYNOS4_GPIO_B0, EXYNOS4_GPIO_C00, 0), + GPIO_ENTRY('c', EXYNOS4_GPIO_C00, EXYNOS4_GPIO_D00, 0), + GPIO_ENTRY('d', EXYNOS4_GPIO_D00, EXYNOS4_GPIO_E00, 0), + GPIO_ENTRY('e', EXYNOS4_GPIO_E00, EXYNOS4_GPIO_F00, 0), + GPIO_ENTRY('f', EXYNOS4_GPIO_F00, EXYNOS4_GPIO_J00, 0), + GPIO_ENTRY('j', EXYNOS4_GPIO_J00, EXYNOS4_GPIO_K00, 0), + GPIO_ENTRY('k', EXYNOS4_GPIO_K00, EXYNOS4_GPIO_L00, 0), + GPIO_ENTRY('l', EXYNOS4_GPIO_L00, EXYNOS4_GPIO_Y00, 0), + GPIO_ENTRY('y', EXYNOS4_GPIO_Y00, EXYNOS4_GPIO_X00, 0), + GPIO_ENTRY('x', EXYNOS4_GPIO_X00, EXYNOS4_GPIO_Z0, 0), + GPIO_ENTRY('z', EXYNOS4_GPIO_Z0, EXYNOS4_GPIO_MAX_PORT, 0), + { 0 } }; -struct exynos5_gpio_part3 { - struct s5p_gpio_bank v0; - struct s5p_gpio_bank v1; - struct s5p_gpio_bank res1[0x1]; - struct s5p_gpio_bank v2; - struct s5p_gpio_bank v3; - struct s5p_gpio_bank res2[0x1]; - struct s5p_gpio_bank v4; +static const struct gpio_name_num_table exynos4x12_gpio_table[] = { + GPIO_ENTRY('a', EXYNOS4X12_GPIO_A00, EXYNOS4X12_GPIO_B0, 0), + GPIO_ENTRY('b', EXYNOS4X12_GPIO_B0, EXYNOS4X12_GPIO_C00, 0), + GPIO_ENTRY('c', EXYNOS4X12_GPIO_C00, EXYNOS4X12_GPIO_D00, 0), + GPIO_ENTRY('d', EXYNOS4X12_GPIO_D00, EXYNOS4X12_GPIO_F00, 0), + GPIO_ENTRY('f', EXYNOS4X12_GPIO_F00, EXYNOS4X12_GPIO_J00, 0), + GPIO_ENTRY('j', EXYNOS4X12_GPIO_J00, EXYNOS4X12_GPIO_K00, 0), + GPIO_ENTRY('k', EXYNOS4X12_GPIO_K00, EXYNOS4X12_GPIO_L00, 0), + GPIO_ENTRY('l', EXYNOS4X12_GPIO_L00, EXYNOS4X12_GPIO_Y00, 0), + GPIO_ENTRY('y', EXYNOS4X12_GPIO_Y00, EXYNOS4X12_GPIO_M00, 0), + GPIO_ENTRY('m', EXYNOS4X12_GPIO_M00, EXYNOS4X12_GPIO_X00, 0), + GPIO_ENTRY('x', EXYNOS4X12_GPIO_X00, EXYNOS4X12_GPIO_Z0, 0), + GPIO_ENTRY('z', EXYNOS4X12_GPIO_Z0, EXYNOS4X12_GPIO_V00, 0), + GPIO_ENTRY('v', EXYNOS4X12_GPIO_V00, EXYNOS4X12_GPIO_MAX_PORT, 0), + { 0 } }; -struct exynos5_gpio_part4 { - struct s5p_gpio_bank z; +static const struct gpio_name_num_table exynos5_gpio_table[] = { + GPIO_ENTRY('a', EXYNOS5_GPIO_A00, EXYNOS5_GPIO_B00, 0), + GPIO_ENTRY('b', EXYNOS5_GPIO_B00, EXYNOS5_GPIO_C00, 0), + GPIO_ENTRY('c', EXYNOS5_GPIO_C00, EXYNOS5_GPIO_D00, 0), + GPIO_ENTRY('d', EXYNOS5_GPIO_D00, EXYNOS5_GPIO_Y00, 0), + GPIO_ENTRY('y', EXYNOS5_GPIO_Y00, EXYNOS5_GPIO_C40, 0), + GPIO_ENTRY('x', EXYNOS5_GPIO_X00, EXYNOS5_GPIO_E00, 0), + GPIO_ENTRY('e', EXYNOS5_GPIO_E00, EXYNOS5_GPIO_F00, 0), + GPIO_ENTRY('f', EXYNOS5_GPIO_F00, EXYNOS5_GPIO_G00, 0), + GPIO_ENTRY('g', EXYNOS5_GPIO_G00, EXYNOS5_GPIO_H00, 0), + GPIO_ENTRY('h', EXYNOS5_GPIO_H00, EXYNOS5_GPIO_V00, 0), + GPIO_ENTRY('v', EXYNOS5_GPIO_V00, EXYNOS5_GPIO_Z0, 0), + GPIO_ENTRY('z', EXYNOS5_GPIO_Z0, EXYNOS5_GPIO_MAX_PORT, 0), + { 0 } }; -/* functions */ -void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg); -void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en); -void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en); -unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); +static const struct gpio_name_num_table exynos5420_gpio_table[] = { + GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0), + GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0), + GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Y70, 0), + GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0), + GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0), + GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 010), + GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0), + GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0), + GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0), + GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0), + GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_Z0, 040), + GPIO_ENTRY('z', EXYNOS5420_GPIO_Z0, EXYNOS5420_GPIO_MAX_PORT, 0), + { 0 } +}; -/* GPIO pins per bank */ -#define GPIO_PER_BANK 8 -#define S5P_GPIO_PART_SHIFT (24) -#define S5P_GPIO_PART_MASK (0xff) -#define S5P_GPIO_BANK_SHIFT (8) -#define S5P_GPIO_BANK_MASK (0xffff) -#define S5P_GPIO_PIN_MASK (0xff) - -#define S5P_GPIO_SET_PART(x) \ - (((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT) - -#define S5P_GPIO_GET_PART(x) \ - (((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK) - -#define S5P_GPIO_SET_PIN(x) \ - ((x) & S5P_GPIO_PIN_MASK) - -#define EXYNOS4_GPIO_SET_BANK(part, bank) \ - ((((unsigned)&(((struct exynos4_gpio_part##part *) \ - EXYNOS4_GPIO_PART##part##_BASE)->bank) \ - - EXYNOS4_GPIO_PART##part##_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) - -#define EXYNOS4X12_GPIO_SET_BANK(part, bank) \ - ((((unsigned)&(((struct exynos4x12_gpio_part##part *) \ - EXYNOS4X12_GPIO_PART##part##_BASE)->bank) \ - - EXYNOS4X12_GPIO_PART##part##_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) - -#define EXYNOS5_GPIO_SET_BANK(part, bank) \ - ((((unsigned)&(((struct exynos5420_gpio_part##part *) \ - EXYNOS5420_GPIO_PART##part##_BASE)->bank) \ - - EXYNOS5_GPIO_PART##part##_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) - -#define EXYNOS5420_GPIO_SET_BANK(part, bank) \ - ((((unsigned)&(((struct exynos5420_gpio_part##part *) \ - EXYNOS5420_GPIO_PART##part##_BASE)->bank) \ - - EXYNOS5420_GPIO_PART##part##_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) - -#define exynos4_gpio_get(part, bank, pin) \ - (S5P_GPIO_SET_PART(part) | \ - EXYNOS4_GPIO_SET_BANK(part, bank) | \ - S5P_GPIO_SET_PIN(pin)) - -#define exynos4x12_gpio_get(part, bank, pin) \ - (S5P_GPIO_SET_PART(part) | \ - EXYNOS4X12_GPIO_SET_BANK(part, bank) | \ - S5P_GPIO_SET_PIN(pin)) - -#define exynos5420_gpio_get(part, bank, pin) \ - (S5P_GPIO_SET_PART(part) | \ - EXYNOS5420_GPIO_SET_BANK(part, bank) | \ - S5P_GPIO_SET_PIN(pin)) - -#define exynos5_gpio_get(part, bank, pin) \ - (S5P_GPIO_SET_PART(part) | \ - EXYNOS5_GPIO_SET_BANK(part, bank) | \ - S5P_GPIO_SET_PIN(pin)) - -static inline unsigned int s5p_gpio_base(int gpio) -{ - unsigned gpio_part = S5P_GPIO_GET_PART(gpio); - - switch (gpio_part) { - case 1: - return samsung_get_base_gpio_part1(); - case 2: - return samsung_get_base_gpio_part2(); - case 3: - return samsung_get_base_gpio_part3(); - case 4: - return samsung_get_base_gpio_part4(); - default: - return 0; - } -} +void gpio_cfg_pin(int gpio, int cfg); +void gpio_set_pull(int gpio, int mode); +void gpio_set_drv(int gpio, int mode); +int gpio_direction_output(unsigned gpio, int value); +int gpio_set_value(unsigned gpio, int value); +int gpio_get_value(unsigned gpio); +void gpio_set_rate(int gpio, int mode); +struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio); +int s5p_gpio_get_pin(unsigned gpio); #endif /* Pin configurations */ -#define GPIO_INPUT 0x0 -#define GPIO_OUTPUT 0x1 -#define GPIO_IRQ 0xf -#define GPIO_FUNC(x) (x) +#define S5P_GPIO_INPUT 0x0 +#define S5P_GPIO_OUTPUT 0x1 +#define S5P_GPIO_IRQ 0xf +#define S5P_GPIO_FUNC(x) (x) /* Pull mode */ -#define GPIO_PULL_NONE 0x0 -#define GPIO_PULL_DOWN 0x1 -#define GPIO_PULL_UP 0x3 +#define S5P_GPIO_PULL_NONE 0x0 +#define S5P_GPIO_PULL_DOWN 0x1 +#define S5P_GPIO_PULL_UP 0x3 /* Drive Strength level */ -#define GPIO_DRV_1X 0x0 -#define GPIO_DRV_3X 0x1 -#define GPIO_DRV_2X 0x2 -#define GPIO_DRV_4X 0x3 -#define GPIO_DRV_FAST 0x0 -#define GPIO_DRV_SLOW 0x1 +#define S5P_GPIO_DRV_1X 0x0 +#define S5P_GPIO_DRV_3X 0x1 +#define S5P_GPIO_DRV_2X 0x2 +#define S5P_GPIO_DRV_4X 0x3 +#define S5P_GPIO_DRV_FAST 0x0 +#define S5P_GPIO_DRV_SLOW 0x1 #endif diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index a17f82834..3dffa4a39 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -161,6 +161,126 @@ struct aips_regs { u32 mpr_0_7; u32 mpr_8_15; }; +/* LCD controller registers */ +struct lcdc_regs { + u32 lssar; /* Screen Start Address */ + u32 lsr; /* Size */ + u32 lvpwr; /* Virtual Page Width */ + u32 lcpr; /* Cursor Position */ + u32 lcwhb; /* Cursor Width Height and Blink */ + u32 lccmr; /* Color Cursor Mapping */ + u32 lpcr; /* Panel Configuration */ + u32 lhcr; /* Horizontal Configuration */ + u32 lvcr; /* Vertical Configuration */ + u32 lpor; /* Panning Offset */ + u32 lscr; /* Sharp Configuration */ + u32 lpccr; /* PWM Contrast Control */ + u32 ldcr; /* DMA Control */ + u32 lrmcr; /* Refresh Mode Control */ + u32 licr; /* Interrupt Configuration */ + u32 lier; /* Interrupt Enable */ + u32 lisr; /* Interrupt Status */ + u32 res0[3]; + u32 lgwsar; /* Graphic Window Start Address */ + u32 lgwsr; /* Graphic Window Size */ + u32 lgwvpwr; /* Graphic Window Virtual Page Width Regist */ + u32 lgwpor; /* Graphic Window Panning Offset */ + u32 lgwpr; /* Graphic Window Position */ + u32 lgwcr; /* Graphic Window Control */ + u32 lgwdcr; /* Graphic Window DMA Control */ + u32 res1[5]; + u32 lauscr; /* AUS Mode Control */ + u32 lausccr; /* AUS mode Cursor Control */ + u32 res2[31 + 64*7]; + u32 bglut; /* Background Lookup Table */ + u32 gwlut; /* Graphic Window Lookup Table */ +}; + +/* Wireless External Interface Module Registers */ +struct weim_regs { + u32 cscr0u; /* Chip Select 0 Upper Register */ + u32 cscr0l; /* Chip Select 0 Lower Register */ + u32 cscr0a; /* Chip Select 0 Addition Register */ + u32 pad0; + u32 cscr1u; /* Chip Select 1 Upper Register */ + u32 cscr1l; /* Chip Select 1 Lower Register */ + u32 cscr1a; /* Chip Select 1 Addition Register */ + u32 pad1; + u32 cscr2u; /* Chip Select 2 Upper Register */ + u32 cscr2l; /* Chip Select 2 Lower Register */ + u32 cscr2a; /* Chip Select 2 Addition Register */ + u32 pad2; + u32 cscr3u; /* Chip Select 3 Upper Register */ + u32 cscr3l; /* Chip Select 3 Lower Register */ + u32 cscr3a; /* Chip Select 3 Addition Register */ + u32 pad3; + u32 cscr4u; /* Chip Select 4 Upper Register */ + u32 cscr4l; /* Chip Select 4 Lower Register */ + u32 cscr4a; /* Chip Select 4 Addition Register */ + u32 pad4; + u32 cscr5u; /* Chip Select 5 Upper Register */ + u32 cscr5l; /* Chip Select 5 Lower Register */ + u32 cscr5a; /* Chip Select 5 Addition Register */ + u32 pad5; + u32 wcr; /* WEIM Configuration Register */ +}; + +/* Multi-Master Memory Interface */ +struct m3if_regs { + u32 ctl; /* Control Register */ + u32 wcfg0; /* Watermark Configuration Register 0 */ + u32 wcfg1; /* Watermark Configuration Register1 */ + u32 wcfg2; /* Watermark Configuration Register2 */ + u32 wcfg3; /* Watermark Configuration Register 3 */ + u32 wcfg4; /* Watermark Configuration Register 4 */ + u32 wcfg5; /* Watermark Configuration Register 5 */ + u32 wcfg6; /* Watermark Configuration Register 6 */ + u32 wcfg7; /* Watermark Configuration Register 7 */ + u32 wcsr; /* Watermark Control and Status Register */ + u32 scfg0; /* Snooping Configuration Register 0 */ + u32 scfg1; /* Snooping Configuration Register 1 */ + u32 scfg2; /* Snooping Configuration Register 2 */ + u32 ssr0; /* Snooping Status Register 0 */ + u32 ssr1; /* Snooping Status Register 1 */ + u32 res0; + u32 mlwe0; /* Master Lock WEIM CS0 Register */ + u32 mlwe1; /* Master Lock WEIM CS1 Register */ + u32 mlwe2; /* Master Lock WEIM CS2 Register */ + u32 mlwe3; /* Master Lock WEIM CS3 Register */ + u32 mlwe4; /* Master Lock WEIM CS4 Register */ + u32 mlwe5; /* Master Lock WEIM CS5 Register */ +}; + +/* Pulse width modulation */ +struct pwm_regs { + u32 cr; /* Control Register */ + u32 sr; /* Status Register */ + u32 ir; /* Interrupt Register */ + u32 sar; /* Sample Register */ + u32 pr; /* Period Register */ + u32 cnr; /* Counter Register */ +}; + +/* Enhanced Periodic Interrupt Timer */ +struct epit_regs { + u32 cr; /* Control register */ + u32 sr; /* Status register */ + u32 lr; /* Load register */ + u32 cmpr; /* Compare register */ + u32 cnr; /* Counter register */ +}; + +/* CSPI registers */ +struct cspi_regs { + u32 rxdata; + u32 txdata; + u32 ctrl; + u32 intr; + u32 dma; + u32 stat; + u32 period; + u32 test; +}; #endif @@ -289,6 +409,8 @@ struct aips_regs { #define CCM_PERCLK_MASK 0x3f #define CCM_RCSR_NF_16BIT_SEL (1 << 14) #define CCM_RCSR_NF_PS(v) ((v >> 26) & 3) +#define CCM_CRDR_BT_UART_SRC_SHIFT 29 +#define CCM_CRDR_BT_UART_SRC_MASK 7 /* ESDRAM Controller register bitfields */ #define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) @@ -345,12 +467,65 @@ struct aips_regs { #define WSR_UNLOCK1 0x5555 #define WSR_UNLOCK2 0xAAAA +/* MAX bits */ +#define MAX_MGPCR_AULB(x) (((x) & 0x7) << 0) + +/* M3IF bits */ +#define M3IF_CTL_MRRP(x) (((x) & 0xff) << 0) + +/* WEIM bits */ +/* 13 fields of the upper CS control register */ +#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ + cnc, wsc, ew, wws, edc) \ + ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \ + (psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \ + (cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0) +/* 12 fields of the lower CS control register */ +#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \ + csa, ebc, dsz, csn, psr, cre, wrap, csen) \ + ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ + (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ + (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) +/* 14 fields of the additional CS control register */ +#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ + wwu, age, cnc2, fce) \ + ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ + (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ + (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ + (age) << 2 | (cnc2) << 1 | (fce) << 0) + /* Names used in GPIO driver */ #define GPIO1_BASE_ADDR IMX_GPIO1_BASE #define GPIO2_BASE_ADDR IMX_GPIO2_BASE #define GPIO3_BASE_ADDR IMX_GPIO3_BASE #define GPIO4_BASE_ADDR IMX_GPIO4_BASE +/* + * CSPI register definitions + */ +#define MXC_CSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_SMC (1 << 3) +#define MXC_CSPICTRL_POL (1 << 4) +#define MXC_CSPICTRL_PHA (1 << 5) +#define MXC_CSPICTRL_SSCTL (1 << 6) +#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 4 + +#define MXC_SPI_BASE_ADDRESSES \ + IMX_CSPI1_BASE, \ + IMX_CSPI2_BASE, \ + IMX_CSPI3_BASE + #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_1 0x11 #define CHIP_REV_1_2 0x12 diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h index 5f9c90ad8..045ccc451 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h @@ -10,6 +10,10 @@ #include <asm/imx-common/iomux-v3.h> enum { + MX6_PAD_ECSPI1_MISO__ECSPI_MISO = IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, 0), + MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0), + MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0), + MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0), MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0), MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 18041913c..bdb143529 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -344,6 +344,7 @@ enum { * MAP - Map this CS to which address(GPMC address space)- Absolute address * >>24 before being used. */ +#define GPMC_SIZE_256M 0x0 #define GPMC_SIZE_128M 0x8 #define GPMC_SIZE_64M 0xC #define GPMC_SIZE_32M 0xE diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h index c21fb5471..f7595ae57 100644 --- a/arch/arm/include/asm/arch-omap4/cpu.h +++ b/arch/arm/include/asm/arch-omap4/cpu.h @@ -12,6 +12,8 @@ #include <asm/types.h> #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ +#include <asm/arch/hardware.h> + #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ struct gptimer { @@ -57,9 +59,6 @@ struct watchdog { #define TCLR_AR (0x1 << 1) #define TCLR_PRE (0x1 << 5) -/* GPMC BASE */ -#define GPMC_BASE (OMAP44XX_GPMC_BASE) - /* I2C base */ #define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000) #define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000) diff --git a/arch/arm/include/asm/arch-omap4/hardware.h b/arch/arm/include/asm/arch-omap4/hardware.h new file mode 100644 index 000000000..f7011b4e9 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/hardware.h @@ -0,0 +1,26 @@ +/* + * hardware.h + * + * hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __OMAP_HARDWARE_H +#define __OMAP_HARDWARE_H + +#include <asm/arch/omap.h> + +/* + * Common hardware definitions + */ + +/* BCH Error Location Module */ +#define ELM_BASE 0x48078000 + +/* GPMC Base address */ +#define GPMC_BASE 0x50000000 + +#endif diff --git a/arch/arm/include/asm/arch-omap4/mem.h b/arch/arm/include/asm/arch-omap4/mem.h new file mode 100644 index 000000000..d2e708bba --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/mem.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * + * Author + * Mansoor Ahamed <mansoor.ahamed@ti.com> + * + * Initial Code from: + * Richard Woodruff <r-woodruff2@ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MEM_H_ +#define _MEM_H_ + +/* + * GPMC settings - + * Definitions is as per the following format + * #define <PART>_GPMC_CONFIG<x> <value> + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * M_NAND - Micron NAND + * STNOR - STMicrolelctronics M29W128GL + */ +#define GPMC_SIZE_256M 0x0 +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#define M_NAND_GPMC_CONFIG1 0x00000800 +#define M_NAND_GPMC_CONFIG2 0x001e1e00 +#define M_NAND_GPMC_CONFIG3 0x001e1e00 +#define M_NAND_GPMC_CONFIG4 0x16051807 +#define M_NAND_GPMC_CONFIG5 0x00151e1e +#define M_NAND_GPMC_CONFIG6 0x16000f80 +#define M_NAND_GPMC_CONFIG7 0x00000008 + +#define STNOR_GPMC_CONFIG1 0x00001200 +#define STNOR_GPMC_CONFIG2 0x00101000 +#define STNOR_GPMC_CONFIG3 0x00030301 +#define STNOR_GPMC_CONFIG4 0x10041004 +#define STNOR_GPMC_CONFIG5 0x000C1010 +#define STNOR_GPMC_CONFIG6 0x08070280 +#define STNOR_GPMC_CONFIG7 0x00000F48 + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index f66da0d60..d43dc265c 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -60,9 +60,6 @@ /* Watchdog Timer2 - MPU watchdog */ #define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) -/* GPMC */ -#define OMAP44XX_GPMC_BASE 0x50000000 - /* * Hardware Register Details */ diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index 80172f379..83d858f30 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -14,6 +14,7 @@ #include <asm/omap_common.h> #include <linux/mtd/omap_gpmc.h> #include <asm/arch/mux_omap4.h> +#include <asm/ti-common/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -53,54 +54,4 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); void setup_warmreset_time(void); - -static inline u32 running_from_sdram(void) -{ - u32 pc; - asm volatile ("mov %0, pc" : "=r" (pc)); - return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) && - (pc < OMAP44XX_DRAM_ADDR_SPACE_END)); -} - -static inline u8 uboot_loaded_by_spl(void) -{ - /* - * u-boot can be running from sdram either because of configuration - * Header or by SPL. If because of CH, then the romcode sets the - * CHSETTINGS executed bit to true in the boot parameter structure that - * it passes to the bootloader.This parameter is stored in the ch_flags - * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a - * mandatory section if CH is present. - */ - if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) - return 0; - else - return running_from_sdram(); -} -/* - * The basic hardware init of OMAP(s_init()) can happen in 4 - * different contexts: - * 1. SPL running from SRAM - * 2. U-Boot running from FLASH - * 3. Non-XIP U-Boot loaded to SDRAM by SPL - * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the - * Configuration Header feature - * - * This function finds this context. - * Defining as inline may help in compiling out unused functions in SPL - */ -static inline u32 omap_hw_init_context(void) -{ -#ifdef CONFIG_SPL_BUILD - return OMAP_INIT_CONTEXT_SPL; -#else - if (uboot_loaded_by_spl()) - return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL; - else if (running_from_sdram()) - return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH; - else - return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR; -#endif -} - #endif diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 2dfe4efb4..30d9de276 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -322,6 +322,9 @@ #define V_SCLK V_OSCK +/* CKO buffer control */ +#define CKOBUFFER_CLK_ENABLE_MASK (1 << 28) + /* AUXCLKx reg fields */ #define AUXCLK_ENABLE_MASK (1 << 8) #define AUXCLK_SRCSELECT_SHIFT 1 diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 5f1d7454d..6109b9277 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -14,6 +14,8 @@ #include <asm/types.h> #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ +#include <asm/arch/hardware.h> + #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ struct gptimer { @@ -63,9 +65,6 @@ struct watchdog { #define TCLR_AR (0x1 << 1) #define TCLR_PRE (0x1 << 5) -/* GPMC BASE */ -#define GPMC_BASE (OMAP54XX_GPMC_BASE) - /* I2C base */ #define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000) #define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000) diff --git a/arch/arm/include/asm/arch-omap5/hardware.h b/arch/arm/include/asm/arch-omap5/hardware.h new file mode 100644 index 000000000..f7011b4e9 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/hardware.h @@ -0,0 +1,26 @@ +/* + * hardware.h + * + * hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __OMAP_HARDWARE_H +#define __OMAP_HARDWARE_H + +#include <asm/arch/omap.h> + +/* + * Common hardware definitions + */ + +/* BCH Error Location Module */ +#define ELM_BASE 0x48078000 + +/* GPMC Base address */ +#define GPMC_BASE 0x50000000 + +#endif diff --git a/arch/arm/include/asm/arch-omap5/mem.h b/arch/arm/include/asm/arch-omap5/mem.h new file mode 100644 index 000000000..d2e708bba --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/mem.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * + * Author + * Mansoor Ahamed <mansoor.ahamed@ti.com> + * + * Initial Code from: + * Richard Woodruff <r-woodruff2@ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MEM_H_ +#define _MEM_H_ + +/* + * GPMC settings - + * Definitions is as per the following format + * #define <PART>_GPMC_CONFIG<x> <value> + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * M_NAND - Micron NAND + * STNOR - STMicrolelctronics M29W128GL + */ +#define GPMC_SIZE_256M 0x0 +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#define M_NAND_GPMC_CONFIG1 0x00000800 +#define M_NAND_GPMC_CONFIG2 0x001e1e00 +#define M_NAND_GPMC_CONFIG3 0x001e1e00 +#define M_NAND_GPMC_CONFIG4 0x16051807 +#define M_NAND_GPMC_CONFIG5 0x00151e1e +#define M_NAND_GPMC_CONFIG6 0x16000f80 +#define M_NAND_GPMC_CONFIG7 0x00000008 + +#define STNOR_GPMC_CONFIG1 0x00001200 +#define STNOR_GPMC_CONFIG2 0x00101000 +#define STNOR_GPMC_CONFIG3 0x00030301 +#define STNOR_GPMC_CONFIG4 0x10041004 +#define STNOR_GPMC_CONFIG5 0x000C1010 +#define STNOR_GPMC_CONFIG6 0x08070280 +#define STNOR_GPMC_CONFIG7 0x00000F48 + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 19fdecec0..b9600cf42 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -23,11 +23,6 @@ #define OMAP54XX_L4_WKUP_BASE 0x4Ae00000 #define OMAP54XX_L4_PER_BASE 0x48000000 -#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000 -#define OMAP54XX_DRAM_ADDR_SPACE_END 0xFFFFFFFF -#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START -#define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END - /* CONTROL ID CODE */ #define CONTROL_CORE_ID_CODE 0x4A002204 #define CONTROL_WKUP_ID_CODE 0x4AE0C204 @@ -45,11 +40,13 @@ #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F #define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F +#define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F /* UART */ #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) #define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000) +#define UART4_BASE (OMAP54XX_L4_PER_BASE + 0x6e000) /* General Purpose Timers */ #define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000) @@ -59,9 +56,6 @@ /* Watchdog Timer2 - MPU watchdog */ #define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) -/* GPMC */ -#define OMAP54XX_GPMC_BASE 0x50000000 - /* QSPI */ #define QSPI_BASE 0x4B300000 diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index bf12c7337..103830319 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -14,6 +14,7 @@ #include <asm/omap_common.h> #include <linux/mtd/omap_gpmc.h> #include <asm/arch/clock.h> +#include <asm/ti-common/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -56,55 +57,6 @@ void get_ioregs(const struct ctrl_ioregs **regs); void srcomp_enable(void); void setup_warmreset_time(void); -static inline u32 running_from_sdram(void) -{ - u32 pc; - asm volatile ("mov %0, pc" : "=r" (pc)); - return ((pc >= OMAP54XX_DRAM_ADDR_SPACE_START) && - (pc < OMAP54XX_DRAM_ADDR_SPACE_END)); -} - -static inline u8 uboot_loaded_by_spl(void) -{ - /* - * u-boot can be running from sdram either because of configuration - * Header or by SPL. If because of CH, then the romcode sets the - * CHSETTINGS executed bit to true in the boot parameter structure that - * it passes to the bootloader.This parameter is stored in the ch_flags - * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a - * mandatory section if CH is present. - */ - if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) - return 0; - else - return running_from_sdram(); -} -/* - * The basic hardware init of OMAP(s_init()) can happen in 4 - * different contexts: - * 1. SPL running from SRAM - * 2. U-Boot running from FLASH - * 3. Non-XIP U-Boot loaded to SDRAM by SPL - * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the - * Configuration Header feature - * - * This function finds this context. - * Defining as inline may help in compiling out unused functions in SPL - */ -static inline u32 omap_hw_init_context(void) -{ -#ifdef CONFIG_SPL_BUILD - return OMAP_INIT_CONTEXT_SPL; -#else - if (uboot_loaded_by_spl()) - return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL; - else if (running_from_sdram()) - return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH; - else - return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR; -#endif -} - static inline u32 div_round_up(u32 num, u32 den) { return (num + den - 1)/den; diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h index 444e361c0..74b5f1df5 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h @@ -1,5 +1,5 @@ -#ifndef __ASM_R8A7790_H__ -#define __ASM_R8A7790_H__ +#ifndef __ASM_R8A7790_GPIO_H__ +#define __ASM_R8A7790_GPIO_H__ /* Pin Function Controller: * GPIO_FN_xx - GPIO used to select pin function @@ -384,4 +384,4 @@ enum { GPIO_FN_TCLK1_B, }; -#endif /* __ASM_R8A7790_H__ */ +#endif /* __ASM_R8A7790_GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/include/asm/arch-rmobile/r8a7790.h index d9ea71fa1..6ef665d58 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7790.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7790.h @@ -1,615 +1,18 @@ /* * arch/arm/include/asm/arch-rmobile/r8a7790.h * - * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013,2014 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0 - */ +*/ #ifndef __ASM_ARCH_R8A7790_H #define __ASM_ARCH_R8A7790_H -/* - * R8A7790 I/O Addresses - */ -#define RWDT_BASE 0xE6020000 -#define SWDT_BASE 0xE6030000 -#define LBSC_BASE 0xFEC00200 -#define DBSC3_0_BASE 0xE6790000 -#define DBSC3_1_BASE 0xE67A0000 -#define TMU_BASE 0xE61E0000 -#define GPIO5_BASE 0xE6055000 -#define SH_QSPI_BASE 0xE6B10000 - -#define S3C_BASE 0xE6784000 -#define S3C_INT_BASE 0xE6784A00 -#define S3C_MEDIA_BASE 0xE6784B00 - -#define S3C_QOS_DCACHE_BASE 0xE6784BDC -#define S3C_QOS_CCI0_BASE 0xE6784C00 -#define S3C_QOS_CCI1_BASE 0xE6784C24 -#define S3C_QOS_MXI_BASE 0xE6784C48 -#define S3C_QOS_AXI_BASE 0xE6784C6C - -#define DBSC3_0_QOS_R0_BASE 0xE6791000 -#define DBSC3_0_QOS_R1_BASE 0xE6791100 -#define DBSC3_0_QOS_R2_BASE 0xE6791200 -#define DBSC3_0_QOS_R3_BASE 0xE6791300 -#define DBSC3_0_QOS_R4_BASE 0xE6791400 -#define DBSC3_0_QOS_R5_BASE 0xE6791500 -#define DBSC3_0_QOS_R6_BASE 0xE6791600 -#define DBSC3_0_QOS_R7_BASE 0xE6791700 -#define DBSC3_0_QOS_R8_BASE 0xE6791800 -#define DBSC3_0_QOS_R9_BASE 0xE6791900 -#define DBSC3_0_QOS_R10_BASE 0xE6791A00 -#define DBSC3_0_QOS_R11_BASE 0xE6791B00 -#define DBSC3_0_QOS_R12_BASE 0xE6791C00 -#define DBSC3_0_QOS_R13_BASE 0xE6791D00 -#define DBSC3_0_QOS_R14_BASE 0xE6791E00 -#define DBSC3_0_QOS_R15_BASE 0xE6791F00 -#define DBSC3_0_QOS_W0_BASE 0xE6792000 -#define DBSC3_0_QOS_W1_BASE 0xE6792100 -#define DBSC3_0_QOS_W2_BASE 0xE6792200 -#define DBSC3_0_QOS_W3_BASE 0xE6792300 -#define DBSC3_0_QOS_W4_BASE 0xE6792400 -#define DBSC3_0_QOS_W5_BASE 0xE6792500 -#define DBSC3_0_QOS_W6_BASE 0xE6792600 -#define DBSC3_0_QOS_W7_BASE 0xE6792700 -#define DBSC3_0_QOS_W8_BASE 0xE6792800 -#define DBSC3_0_QOS_W9_BASE 0xE6792900 -#define DBSC3_0_QOS_W10_BASE 0xE6792A00 -#define DBSC3_0_QOS_W11_BASE 0xE6792B00 -#define DBSC3_0_QOS_W12_BASE 0xE6792C00 -#define DBSC3_0_QOS_W13_BASE 0xE6792D00 -#define DBSC3_0_QOS_W14_BASE 0xE6792E00 -#define DBSC3_0_QOS_W15_BASE 0xE6792F00 - -#define DBSC3_0_DBADJ2 0xE67900C8 - -#define CCI_400_MAXOT_1 0xF0091110 -#define CCI_400_MAXOT_2 0xF0092110 -#define CCI_400_QOSCNTL_1 0xF009110C -#define CCI_400_QOSCNTL_2 0xF009210C - -#define MXI_BASE 0xFE960000 -#define MXI_QOS_BASE 0xFE960300 - -#define SYS_AXI_SYX64TO128_BASE 0xFF800300 -#define SYS_AXI_AVB_BASE 0xFF800340 -#define SYS_AXI_G2D_BASE 0xFF800540 -#define SYS_AXI_IMP0_BASE 0xFF800580 -#define SYS_AXI_IMP1_BASE 0xFF8005C0 -#define SYS_AXI_IMUX0_BASE 0xFF800600 -#define SYS_AXI_IMUX1_BASE 0xFF800640 -#define SYS_AXI_IMUX2_BASE 0xFF800680 -#define SYS_AXI_LBS_BASE 0xFF8006C0 -#define SYS_AXI_MMUDS_BASE 0xFF800700 -#define SYS_AXI_MMUM_BASE 0xFF800740 -#define SYS_AXI_MMUR_BASE 0xFF800780 -#define SYS_AXI_MMUS0_BASE 0xFF8007C0 -#define SYS_AXI_MMUS1_BASE 0xFF800800 -#define SYS_AXI_MTSB0_BASE 0xFF800880 -#define SYS_AXI_MTSB1_BASE 0xFF8008C0 -#define SYS_AXI_PCI_BASE 0xFF800900 -#define SYS_AXI_RTX_BASE 0xFF800940 -#define SYS_AXI_SDS0_BASE 0xFF800A80 -#define SYS_AXI_SDS1_BASE 0xFF800AC0 -#define SYS_AXI_USB20_BASE 0xFF800C00 -#define SYS_AXI_USB21_BASE 0xFF800C40 -#define SYS_AXI_USB22_BASE 0xFF800C80 -#define SYS_AXI_USB30_BASE 0xFF800CC0 - -#define RT_AXI_SHX_BASE 0xFF810100 -#define RT_AXI_RDS_BASE 0xFF8101C0 -#define RT_AXI_RTX64TO128_BASE 0xFF810200 -#define RT_AXI_STPRO_BASE 0xFF810240 - -#define MP_AXI_ADSP_BASE 0xFF820100 -#define MP_AXI_ASDS0_BASE 0xFF8201C0 -#define MP_AXI_ASDS1_BASE 0xFF820200 -#define MP_AXI_MLP_BASE 0xFF820240 -#define MP_AXI_MMUMP_BASE 0xFF820280 -#define MP_AXI_SPU_BASE 0xFF8202C0 -#define MP_AXI_SPUC_BASE 0xFF820300 - -#define SYS_AXI256_AXI128TO256_BASE 0xFF860100 -#define SYS_AXI256_SYX_BASE 0xFF860140 -#define SYS_AXI256_MPX_BASE 0xFF860180 -#define SYS_AXI256_MXI_BASE 0xFF8601C0 - -#define CCI_AXI_MMUS0_BASE 0xFF880100 -#define CCI_AXI_SYX2_BASE 0xFF880140 -#define CCI_AXI_MMUR_BASE 0xFF880180 -#define CCI_AXI_MMUDS_BASE 0xFF8801C0 -#define CCI_AXI_MMUM_BASE 0xFF880200 -#define CCI_AXI_MXI_BASE 0xFF880240 -#define CCI_AXI_MMUS1_BASE 0xFF880280 -#define CCI_AXI_MMUMP_BASE 0xFF8802C0 - -#define MEDIA_AXI_JPR_BASE 0xFE964100 -#define MEDIA_AXI_JPW_BASE 0xFE966100 -#define MEDIA_AXI_GCU0R_BASE 0xFE964140 -#define MEDIA_AXI_GCU0W_BASE 0xFE966140 -#define MEDIA_AXI_GCU1R_BASE 0xFE964180 -#define MEDIA_AXI_GCU1W_BASE 0xFE966180 -#define MEDIA_AXI_TDMR_BASE 0xFE964500 -#define MEDIA_AXI_TDMW_BASE 0xFE966500 -#define MEDIA_AXI_VSP0CR_BASE 0xFE964540 -#define MEDIA_AXI_VSP0CW_BASE 0xFE966540 -#define MEDIA_AXI_VSP1CR_BASE 0xFE964580 -#define MEDIA_AXI_VSP1CW_BASE 0xFE966580 -#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0 -#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0 -#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600 -#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600 -#define MEDIA_AXI_VIN0W_BASE 0xFE966900 -#define MEDIA_AXI_VSP0R_BASE 0xFE964D00 -#define MEDIA_AXI_VSP0W_BASE 0xFE966D00 -#define MEDIA_AXI_FDP0R_BASE 0xFE964D40 -#define MEDIA_AXI_FDP0W_BASE 0xFE966D40 -#define MEDIA_AXI_IMSR_BASE 0xFE964D80 -#define MEDIA_AXI_IMSW_BASE 0xFE966D80 -#define MEDIA_AXI_VSP1R_BASE 0xFE965100 -#define MEDIA_AXI_VSP1W_BASE 0xFE967100 -#define MEDIA_AXI_FDP1R_BASE 0xFE965140 -#define MEDIA_AXI_FDP1W_BASE 0xFE967140 -#define MEDIA_AXI_IMRR_BASE 0xFE965180 -#define MEDIA_AXI_IMRW_BASE 0xFE967180 -#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0 -#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0 -#define MEDIA_AXI_VSPD0R_BASE 0xFE965500 -#define MEDIA_AXI_VSPD0W_BASE 0xFE967500 -#define MEDIA_AXI_VSPD1R_BASE 0xFE965540 -#define MEDIA_AXI_VSPD1W_BASE 0xFE967540 -#define MEDIA_AXI_DU0R_BASE 0xFE965580 -#define MEDIA_AXI_DU0W_BASE 0xFE967580 -#define MEDIA_AXI_DU1R_BASE 0xFE9655C0 -#define MEDIA_AXI_DU1W_BASE 0xFE9675C0 -#define MEDIA_AXI_VCP0CR_BASE 0xFE965900 -#define MEDIA_AXI_VCP0CW_BASE 0xFE967900 -#define MEDIA_AXI_VCP0VR_BASE 0xFE965940 -#define MEDIA_AXI_VCP0VW_BASE 0xFE967940 -#define MEDIA_AXI_VPC0R_BASE 0xFE965980 -#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00 -#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00 -#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40 -#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40 -#define MEDIA_AXI_VPC1R_BASE 0xFE965D80 - -#define SYS_AXI_AVBDMSCR 0xFF802000 -#define SYS_AXI_SYX2DMSCR 0xFF802004 -#define SYS_AXI_CC50DMSCR 0xFF802008 -#define SYS_AXI_CC51DMSCR 0xFF80200C -#define SYS_AXI_CCIDMSCR 0xFF802010 -#define SYS_AXI_CSDMSCR 0xFF802014 -#define SYS_AXI_DDMDMSCR 0xFF802018 -#define SYS_AXI_ETHDMSCR 0xFF80201C -#define SYS_AXI_G2DDMSCR 0xFF802020 -#define SYS_AXI_IMP0DMSCR 0xFF802024 -#define SYS_AXI_IMP1DMSCR 0xFF802028 -#define SYS_AXI_LBSDMSCR 0xFF80202C -#define SYS_AXI_MMUDSDMSCR 0xFF802030 -#define SYS_AXI_MMUMXDMSCR 0xFF802034 -#define SYS_AXI_MMURDDMSCR 0xFF802038 -#define SYS_AXI_MMUS0DMSCR 0xFF80203C -#define SYS_AXI_MMUS1DMSCR 0xFF802040 -#define SYS_AXI_MPXDMSCR 0xFF802044 -#define SYS_AXI_MTSB0DMSCR 0xFF802048 -#define SYS_AXI_MTSB1DMSCR 0xFF80204C -#define SYS_AXI_PCIDMSCR 0xFF802050 -#define SYS_AXI_RTXDMSCR 0xFF802054 -#define SYS_AXI_SAT0DMSCR 0xFF802058 -#define SYS_AXI_SAT1DMSCR 0xFF80205C -#define SYS_AXI_SDM0DMSCR 0xFF802060 -#define SYS_AXI_SDM1DMSCR 0xFF802064 -#define SYS_AXI_SDS0DMSCR 0xFF802068 -#define SYS_AXI_SDS1DMSCR 0xFF80206C -#define SYS_AXI_ETRABDMSCR 0xFF802070 -#define SYS_AXI_ETRKFDMSCR 0xFF802074 -#define SYS_AXI_UDM0DMSCR 0xFF802078 -#define SYS_AXI_UDM1DMSCR 0xFF80207C -#define SYS_AXI_USB20DMSCR 0xFF802080 -#define SYS_AXI_USB21DMSCR 0xFF802084 -#define SYS_AXI_USB22DMSCR 0xFF802088 -#define SYS_AXI_USB30DMSCR 0xFF80208C -#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100 -#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104 -#define SYS_AXI_AVBSLVDMSCR 0xFF802108 -#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C -#define SYS_AXI_ETHSLVDMSCR 0xFF802110 -#define SYS_AXI_GICSLVDMSCR 0xFF802114 -#define SYS_AXI_IMPSLVDMSCR 0xFF802118 -#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C -#define SYS_AXI_IMX1SLVDMSCR 0xFF802120 -#define SYS_AXI_IMX2SLVDMSCR 0xFF802124 -#define SYS_AXI_LBSSLVDMSCR 0xFF802128 -#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C -#define SYS_AXI_MMC1SLVDMSCR 0xFF802130 -#define SYS_AXI_MPXSLVDMSCR 0xFF802134 -#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138 -#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C -#define SYS_AXI_MXTSLVDMSCR 0xFF802140 -#define SYS_AXI_PCISLVDMSCR 0xFF802144 -#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148 -#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C -#define SYS_AXI_RTXSLVDMSCR 0xFF802150 -#define SYS_AXI_SAT0SLVDMSCR 0xFF802168 -#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C -#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170 -#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174 -#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178 -#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C -#define SYS_AXI_SGXSLVDMSCR 0xFF802180 -#define SYS_AXI_STBSLVDMSCR 0xFF802188 -#define SYS_AXI_STMSLVDMSCR 0xFF80218C -#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194 -#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198 -#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C -#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0 -#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4 -#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8 -#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC - -#define RT_AXI_CBMDMSCR 0xFF812000 -#define RT_AXI_DBDMSCR 0xFF812004 -#define RT_AXI_RDMDMSCR 0xFF812008 -#define RT_AXI_RDSDMSCR 0xFF81200C -#define RT_AXI_STRDMSCR 0xFF812010 -#define RT_AXI_SY2RTDMSCR 0xFF812014 -#define RT_AXI_CBSSLVDMSCR 0xFF812100 -#define RT_AXI_DBSSLVDMSCR 0xFF812104 -#define RT_AXI_RTAP1SLVDMSCR 0xFF812108 -#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C -#define RT_AXI_RTAP3SLVDMSCR 0xFF812110 -#define RT_AXI_RT2SYSLVDMSCR 0xFF812114 -#define RT_AXI_A128TO64SLVDMSCR 0xFF812118 -#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C -#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120 -#define RT_AXI_UTLBRSLVDMSCR 0xFF812128 - -#define MP_AXI_ADSPDMSCR 0xFF822000 -#define MP_AXI_ASDM0DMSCR 0xFF822004 -#define MP_AXI_ASDM1DMSCR 0xFF822008 -#define MP_AXI_ASDS0DMSCR 0xFF82200C -#define MP_AXI_ASDS1DMSCR 0xFF822010 -#define MP_AXI_MLPDMSCR 0xFF822014 -#define MP_AXI_MMUMPDMSCR 0xFF822018 -#define MP_AXI_SPUDMSCR 0xFF82201C -#define MP_AXI_SPUCDMSCR 0xFF822020 -#define MP_AXI_SY2MPDMSCR 0xFF822024 -#define MP_AXI_ADSPSLVDMSCR 0xFF822100 -#define MP_AXI_MLMSLVDMSCR 0xFF822104 -#define MP_AXI_MPAP4SLVDMSCR 0xFF822108 -#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C -#define MP_AXI_MPAP6SLVDMSCR 0xFF822110 -#define MP_AXI_MPAP7SLVDMSCR 0xFF822114 -#define MP_AXI_MP2SYSLVDMSCR 0xFF822118 -#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C -#define MP_AXI_MPXAPSLVDMSCR 0xFF822124 -#define MP_AXI_SPUSLVDMSCR 0xFF822128 -#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C - -#define ADM_AXI_ASDM0DMSCR 0xFF842000 -#define ADM_AXI_ASDM1DMSCR 0xFF842004 -#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104 -#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108 -#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C - -#define DM_AXI_RDMDMSCR 0xFF852000 -#define DM_AXI_SDM0DMSCR 0xFF852004 -#define DM_AXI_SDM1DMSCR 0xFF852008 -#define DM_AXI_MMAP0SLVDMSCR 0xFF852100 -#define DM_AXI_MMAP1SLVDMSCR 0xFF852104 -#define DM_AXI_QSPAPSLVDMSCR 0xFF852108 -#define DM_AXI_RAP4SLVDMSCR 0xFF85210C -#define DM_AXI_RAP5SLVDMSCR 0xFF852110 -#define DM_AXI_SAP4SLVDMSCR 0xFF852114 -#define DM_AXI_SAP5SLVDMSCR 0xFF852118 -#define DM_AXI_SAP6SLVDMSCR 0xFF85211C -#define DM_AXI_SAP65SLVDMSCR 0xFF852120 -#define DM_AXI_SDAP0SLVDMSCR 0xFF852124 -#define DM_AXI_SDAP1SLVDMSCR 0xFF852128 -#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C -#define DM_AXI_SDAP3SLVDMSCR 0xFF852130 - -#define SYS_AXI256_SYXDMSCR 0xFF862000 -#define SYS_AXI256_MPXDMSCR 0xFF862004 -#define SYS_AXI256_MXIDMSCR 0xFF862008 -#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100 -#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104 -#define SYS_AXI256_SYXSLVDMSCR 0xFF862108 -#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C -#define SYS_AXI256_S3CSLVDMSCR 0xFF862110 - -#define MXT_SYXDMSCR 0xFF872000 -#define MXT_CMM0SLVDMSCR 0xFF872100 -#define MXT_CMM1SLVDMSCR 0xFF872104 -#define MXT_CMM2SLVDMSCR 0xFF872108 -#define MXT_FDPSLVDMSCR 0xFF87210C -#define MXT_IMRSLVDMSCR 0xFF872110 -#define MXT_VINSLVDMSCR 0xFF872114 -#define MXT_VPC0SLVDMSCR 0xFF872118 -#define MXT_VPC1SLVDMSCR 0xFF87211C -#define MXT_VSP0SLVDMSCR 0xFF872120 -#define MXT_VSP1SLVDMSCR 0xFF872124 -#define MXT_VSPD0SLVDMSCR 0xFF872128 -#define MXT_VSPD1SLVDMSCR 0xFF87212C -#define MXT_MAP1SLVDMSCR 0xFF872130 -#define MXT_MAP2SLVDMSCR 0xFF872134 - -#define CCI_AXI_MMUS0DMSCR 0xFF882000 -#define CCI_AXI_SYX2DMSCR 0xFF882004 -#define CCI_AXI_MMURDMSCR 0xFF882008 -#define CCI_AXI_MMUDSDMSCR 0xFF88200C -#define CCI_AXI_MMUMDMSCR 0xFF882010 -#define CCI_AXI_MXIDMSCR 0xFF882014 -#define CCI_AXI_MMUS1DMSCR 0xFF882018 -#define CCI_AXI_MMUMPDMSCR 0xFF88201C -#define CCI_AXI_DVMDMSCR 0xFF882020 -#define CCI_AXI_CCISLVDMSCR 0xFF882100 - -#define CCI_AXI_IPMMUIDVMCR 0xFF880400 -#define CCI_AXI_IPMMURDVMCR 0xFF880404 -#define CCI_AXI_IPMMUS0DVMCR 0xFF880408 -#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C -#define CCI_AXI_IPMMUMPDVMCR 0xFF880410 -#define CCI_AXI_IPMMUDSDVMCR 0xFF880414 -#define CCI_AXI_AX2ADDRMASK 0xFF88041C - -#ifndef __ASSEMBLY__ -#include <asm/types.h> - -/* RWDT */ -struct r8a7790_rwdt { - u32 rwtcnt; /* 0x00 */ - u32 rwtcsra; /* 0x04 */ - u16 rwtcsrb; /* 0x08 */ -}; - -/* SWDT */ -struct r8a7790_swdt { - u32 swtcnt; /* 0x00 */ - u32 swtcsra; /* 0x04 */ - u16 swtcsrb; /* 0x08 */ -}; - -/* LBSC */ -struct r8a7790_lbsc { - u32 cs0ctrl; - u32 cs1ctrl; - u32 ecs0ctrl; - u32 ecs1ctrl; - u32 ecs2ctrl; - u32 ecs3ctrl; - u32 ecs4ctrl; - u32 ecs5ctrl; - u32 dummy0[4]; /* 0x20 .. 0x2C */ - u32 cswcr0; - u32 cswcr1; - u32 ecswcr0; - u32 ecswcr1; - u32 ecswcr2; - u32 ecswcr3; - u32 ecswcr4; - u32 ecswcr5; - u32 exdmawcr0; - u32 exdmawcr1; - u32 exdmawcr2; - u32 dummy1[9]; /* 0x5C .. 0x7C */ - u32 cspwcr0; - u32 cspwcr1; - u32 ecspwcr0; - u32 ecspwcr1; - u32 ecspwcr2; - u32 ecspwcr3; - u32 ecspwcr4; - u32 ecspwcr5; - u32 exwtsync; - u32 dummy2[3]; /* 0xA4 .. 0xAC */ - u32 cs0bstctl; - u32 cs0btph; - u32 dummy3[2]; /* 0xB8 .. 0xBC */ - u32 cs1gdst; - u32 ecs0gdst; - u32 ecs1gdst; - u32 ecs2gdst; - u32 ecs3gdst; - u32 ecs4gdst; - u32 ecs5gdst; - u32 dummy4[5]; /* 0xDC .. 0xEC */ - u32 exdmaset0; - u32 exdmaset1; - u32 exdmaset2; - u32 dummy5[5]; /* 0xFC .. 0x10C */ - u32 exdmcr0; - u32 exdmcr1; - u32 exdmcr2; - u32 dummy6[5]; /* 0x11C .. 0x12C */ - u32 bcintsr; - u32 bcintcr; - u32 bcintmr; - u32 dummy7; /* 0x13C */ - u32 exbatlv; - u32 exwtsts; - u32 dummy8[14]; /* 0x148 .. 0x17C */ - u32 atacsctrl; - u32 dummy9[15]; /* 0x184 .. 0x1BC */ - u32 exbct; - u32 extct; -}; - -/* DBSC3 */ -struct r8a7790_dbsc3 { - u32 dummy0[3]; /* 0x00 .. 0x08 */ - u32 dbstate1; - u32 dbacen; - u32 dbrfen; - u32 dbcmd; - u32 dbwait; - u32 dbkind; - u32 dbconf0; - u32 dummy1[2]; /* 0x28 .. 0x2C */ - u32 dbphytype; - u32 dummy2[3]; /* 0x34 .. 0x3C */ - u32 dbtr0; - u32 dbtr1; - u32 dbtr2; - u32 dummy3; /* 0x4C */ - u32 dbtr3; - u32 dbtr4; - u32 dbtr5; - u32 dbtr6; - u32 dbtr7; - u32 dbtr8; - u32 dbtr9; - u32 dbtr10; - u32 dbtr11; - u32 dbtr12; - u32 dbtr13; - u32 dbtr14; - u32 dbtr15; - u32 dbtr16; - u32 dbtr17; - u32 dbtr18; - u32 dbtr19; - u32 dummy4[7]; /* 0x94 .. 0xAC */ - u32 dbbl; - u32 dummy5[3]; /* 0xB4 .. 0xBC */ - u32 dbadj0; - u32 dummy6; /* 0xC4 */ - u32 dbadj2; - u32 dummy7[5]; /* 0xCC .. 0xDC */ - u32 dbrfcnf0; - u32 dbrfcnf1; - u32 dbrfcnf2; - u32 dummy8[2]; /* 0xEC .. 0xF0 */ - u32 dbcalcnf; - u32 dbcaltr; - u32 dummy9; /* 0xFC */ - u32 dbrnk0; - u32 dummy10[31]; /* 0x104 .. 0x17C */ - u32 dbpdncnf; - u32 dummy11[47]; /* 0x184 ..0x23C */ - u32 dbdfistat; - u32 dbdficnt; - u32 dummy12[14]; /* 0x248 .. 0x27C */ - u32 dbpdlck; - u32 dummy13[3]; /* 0x284 .. 0x28C */ - u32 dbpdrga; - u32 dummy14[3]; /* 0x294 .. 0x29C */ - u32 dbpdrgd; - u32 dummy15[24]; /* 0x2A4 .. 0x300 */ - u32 dbbs0cnt1; - u32 dummy16[30]; /* 0x308 .. 0x37C */ - u32 dbwt0cnf0; - u32 dbwt0cnf1; - u32 dbwt0cnf2; - u32 dbwt0cnf3; - u32 dbwt0cnf4; -}; - -/* GPIO */ -struct r8a7790_gpio { - u32 iointsel; - u32 inoutsel; - u32 outdt; - u32 indt; - u32 intdt; - u32 intclr; - u32 intmsk; - u32 posneg; - u32 edglevel; - u32 filonoff; - u32 intmsks; - u32 mskclrs; - u32 outdtsel; - u32 outdth; - u32 outdtl; - u32 bothedge; -}; - -/* S3C(QoS) */ -struct r8a7790_s3c { - u32 s3cexcladdmsk; - u32 s3cexclidmsk; - u32 s3cadsplcr; - u32 s3cmaar; - u32 s3carcr11; - u32 s3crorr; - u32 s3cworr; - u32 s3carcr22; - u32 dummy1[2]; /* 0x20 .. 0x24 */ - u32 s3cmctr; - u32 dummy2; /* 0x2C */ - u32 cconf0; - u32 cconf1; - u32 cconf2; - u32 cconf3; -}; - -struct r8a7790_s3c_qos { - u32 s3cqos0; - u32 s3cqos1; - u32 s3cqos2; - u32 s3cqos3; - u32 s3cqos4; - u32 s3cqos5; - u32 s3cqos6; - u32 s3cqos7; - u32 s3cqos8; -}; - -/* DBSC(QoS) */ -struct r8a7790_dbsc3_qos { - u32 dblgcnt; - u32 dbtmval0; - u32 dbtmval1; - u32 dbtmval2; - u32 dbtmval3; - u32 dbrqctr; - u32 dbthres0; - u32 dbthres1; - u32 dbthres2; - u32 dummy0; /* 0x24 */ - u32 dblgqon; -}; - -/* MXI(QoS) */ -struct r8a7790_mxi { - u32 mxsaar0; - u32 mxsaar1; - u32 dummy0[7]; /* 0x08 .. 0x20 */ - u32 mxaxiracr; - u32 mxs3cracr; - u32 dummy1[2]; /* 0x2C .. 0x30 */ - u32 mxaxiwacr; - u32 mxs3cwacr; - u32 dummy2; /* 0x3C */ - u32 mxrtcr; - u32 mxwtcr; -}; - -struct r8a7790_mxi_qos { - u32 vspdu0; - u32 vspdu1; - u32 du0; - u32 du1; -}; - -/* AXI(QoS) */ -struct r8a7790_axi_qos { - u32 qosconf; - u32 qosctset0; - u32 qosctset1; - u32 qosctset2; - u32 qosctset3; - u32 qosreqctr; - u32 qosthres0; - u32 qosthres1; - u32 qosthres2; - u32 qosqon; -}; +#include "rcar-base.h" -#endif +#define R8A7790_CUT_ES2X 2 +#define IS_R8A7790_ES2() \ + (rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X) #endif /* __ASM_ARCH_R8A7790_H */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h index d3cf0c10a..42e82597e 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h @@ -1,5 +1,5 @@ -#ifndef __ASM_R8A7791_H__ -#define __ASM_R8A7791_H__ +#ifndef __ASM_R8A7791_GPIO_H__ +#define __ASM_R8A7791_GPIO_H__ /* Pin Function Controller: * GPIO_FN_xx - GPIO used to select pin function @@ -435,4 +435,4 @@ enum { GPIO_FN_MLB_DAT, GPIO_FN_CAN1_RX_B, }; -#endif /* __ASM_R8A7791_H__ */ +#endif /* __ASM_R8A7791_GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h index ff3018059..592c52474 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7791.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h @@ -1,69 +1,18 @@ /* * arch/arm/include/asm/arch-rmobile/r8a7791.h * - * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013,2014 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0 - */ +*/ #ifndef __ASM_ARCH_R8A7791_H #define __ASM_ARCH_R8A7791_H +#include "rcar-base.h" /* - * R8A7791 I/O Addresses + * R-Car (R8A7791) I/O Addresses */ -#define RWDT_BASE 0xE6020000 -#define SWDT_BASE 0xE6030000 -#define LBSC_BASE 0xFEC00200 -#define DBSC3_0_BASE 0xE6790000 -#define DBSC3_1_BASE 0xE67A0000 -#define TMU_BASE 0xE61E0000 -#define GPIO5_BASE 0xE6055000 -#define SH_QSPI_BASE 0xE6B10000 - -#define S3C_BASE 0xE6784000 -#define S3C_INT_BASE 0xE6784A00 -#define S3C_MEDIA_BASE 0xE6784B00 - -#define S3C_QOS_DCACHE_BASE 0xE6784BDC -#define S3C_QOS_CCI0_BASE 0xE6784C00 -#define S3C_QOS_CCI1_BASE 0xE6784C24 -#define S3C_QOS_MXI_BASE 0xE6784C48 -#define S3C_QOS_AXI_BASE 0xE6784C6C - -#define DBSC3_0_QOS_R0_BASE 0xE6791000 -#define DBSC3_0_QOS_R1_BASE 0xE6791100 -#define DBSC3_0_QOS_R2_BASE 0xE6791200 -#define DBSC3_0_QOS_R3_BASE 0xE6791300 -#define DBSC3_0_QOS_R4_BASE 0xE6791400 -#define DBSC3_0_QOS_R5_BASE 0xE6791500 -#define DBSC3_0_QOS_R6_BASE 0xE6791600 -#define DBSC3_0_QOS_R7_BASE 0xE6791700 -#define DBSC3_0_QOS_R8_BASE 0xE6791800 -#define DBSC3_0_QOS_R9_BASE 0xE6791900 -#define DBSC3_0_QOS_R10_BASE 0xE6791A00 -#define DBSC3_0_QOS_R11_BASE 0xE6791B00 -#define DBSC3_0_QOS_R12_BASE 0xE6791C00 -#define DBSC3_0_QOS_R13_BASE 0xE6791D00 -#define DBSC3_0_QOS_R14_BASE 0xE6791E00 -#define DBSC3_0_QOS_R15_BASE 0xE6791F00 -#define DBSC3_0_QOS_W0_BASE 0xE6792000 -#define DBSC3_0_QOS_W1_BASE 0xE6792100 -#define DBSC3_0_QOS_W2_BASE 0xE6792200 -#define DBSC3_0_QOS_W3_BASE 0xE6792300 -#define DBSC3_0_QOS_W4_BASE 0xE6792400 -#define DBSC3_0_QOS_W5_BASE 0xE6792500 -#define DBSC3_0_QOS_W6_BASE 0xE6792600 -#define DBSC3_0_QOS_W7_BASE 0xE6792700 -#define DBSC3_0_QOS_W8_BASE 0xE6792800 -#define DBSC3_0_QOS_W9_BASE 0xE6792900 -#define DBSC3_0_QOS_W10_BASE 0xE6792A00 -#define DBSC3_0_QOS_W11_BASE 0xE6792B00 -#define DBSC3_0_QOS_W12_BASE 0xE6792C00 -#define DBSC3_0_QOS_W13_BASE 0xE6792D00 -#define DBSC3_0_QOS_W14_BASE 0xE6792E00 -#define DBSC3_0_QOS_W15_BASE 0xE6792F00 - #define DBSC3_1_QOS_R0_BASE 0xE67A1000 #define DBSC3_1_QOS_R1_BASE 0xE67A1100 #define DBSC3_1_QOS_R2_BASE 0xE67A1200 @@ -96,570 +45,10 @@ #define DBSC3_1_QOS_W13_BASE 0xE67A2D00 #define DBSC3_1_QOS_W14_BASE 0xE67A2E00 #define DBSC3_1_QOS_W15_BASE 0xE67A2F00 +#define DBSC3_1_DBADJ2 0xE67A00C8 -#define DBSC3_0_DBADJ2 0xE67900C8 - -#define CCI_400_MAXOT_1 0xF0091110 -#define CCI_400_MAXOT_2 0xF0092110 -#define CCI_400_QOSCNTL_1 0xF009110C -#define CCI_400_QOSCNTL_2 0xF009210C - -#define MXI_BASE 0xFE960000 -#define MXI_QOS_BASE 0xFE960300 - -#define SYS_AXI_SYX64TO128_BASE 0xFF800300 -#define SYS_AXI_AVB_BASE 0xFF800340 -#define SYS_AXI_G2D_BASE 0xFF800540 -#define SYS_AXI_IMP0_BASE 0xFF800580 -#define SYS_AXI_IMP1_BASE 0xFF8005C0 -#define SYS_AXI_IMUX0_BASE 0xFF800600 -#define SYS_AXI_IMUX1_BASE 0xFF800640 -#define SYS_AXI_IMUX2_BASE 0xFF800680 -#define SYS_AXI_LBS_BASE 0xFF8006C0 -#define SYS_AXI_MMUDS_BASE 0xFF800700 -#define SYS_AXI_MMUM_BASE 0xFF800740 -#define SYS_AXI_MMUR_BASE 0xFF800780 -#define SYS_AXI_MMUS0_BASE 0xFF8007C0 -#define SYS_AXI_MMUS1_BASE 0xFF800800 -#define SYS_AXI_MTSB0_BASE 0xFF800880 -#define SYS_AXI_MTSB1_BASE 0xFF8008C0 -#define SYS_AXI_PCI_BASE 0xFF800900 -#define SYS_AXI_RTX_BASE 0xFF800940 -#define SYS_AXI_SDS0_BASE 0xFF800A80 -#define SYS_AXI_SDS1_BASE 0xFF800AC0 -#define SYS_AXI_USB20_BASE 0xFF800C00 -#define SYS_AXI_USB21_BASE 0xFF800C40 -#define SYS_AXI_USB22_BASE 0xFF800C80 -#define SYS_AXI_USB30_BASE 0xFF800CC0 -#define SYS_AXI_AX2M_BASE 0xFF800380 -#define SYS_AXI_CC50_BASE 0xFF8003C0 -#define SYS_AXI_CCI_BASE 0xFF800440 -#define SYS_AXI_CS_BASE 0xFF800480 -#define SYS_AXI_DDM_BASE 0xFF8004C0 -#define SYS_AXI_ETH_BASE 0xFF800500 -#define SYS_AXI_MPXM_BASE 0xFF800840 -#define SYS_AXI_SAT0_BASE 0xFF800980 -#define SYS_AXI_SAT1_BASE 0xFF8009C0 -#define SYS_AXI_SDM0_BASE 0xFF800A00 -#define SYS_AXI_SDM1_BASE 0xFF800A40 -#define SYS_AXI_TRAB_BASE 0xFF800B00 -#define SYS_AXI_UDM0_BASE 0xFF800B80 -#define SYS_AXI_UDM1_BASE 0xFF800BC0 - -#define RT_AXI_SHX_BASE 0xFF810100 -#define RT_AXI_DBG_BASE 0xFF810140 -#define RT_AXI_RDM_BASE 0xFF810180 -#define RT_AXI_RDS_BASE 0xFF8101C0 -#define RT_AXI_RTX64TO128_BASE 0xFF810200 -#define RT_AXI_STPRO_BASE 0xFF810240 -#define RT_AXI_SY2RT_BASE 0xFF810280 - -#define MP_AXI_ADSP_BASE 0xFF820100 -#define MP_AXI_ASDS0_BASE 0xFF8201C0 -#define MP_AXI_ASDS1_BASE 0xFF820200 -#define MP_AXI_MLP_BASE 0xFF820240 -#define MP_AXI_MMUMP_BASE 0xFF820280 -#define MP_AXI_SPU_BASE 0xFF8202C0 -#define MP_AXI_SPUC_BASE 0xFF820300 - -#define SYS_AXI256_AXI128TO256_BASE 0xFF860100 -#define SYS_AXI256_SYX_BASE 0xFF860140 -#define SYS_AXI256_MPX_BASE 0xFF860180 -#define SYS_AXI256_MXI_BASE 0xFF8601C0 - -#define CCI_AXI_MMUS0_BASE 0xFF880100 -#define CCI_AXI_SYX2_BASE 0xFF880140 -#define CCI_AXI_MMUR_BASE 0xFF880180 -#define CCI_AXI_MMUDS_BASE 0xFF8801C0 -#define CCI_AXI_MMUM_BASE 0xFF880200 -#define CCI_AXI_MXI_BASE 0xFF880240 -#define CCI_AXI_MMUS1_BASE 0xFF880280 -#define CCI_AXI_MMUMP_BASE 0xFF8802C0 - -#define MEDIA_AXI_MXR_BASE 0xFE960080 -#define MEDIA_AXI_MXW_BASE 0xFE9600C0 -#define MEDIA_AXI_JPR_BASE 0xFE964100 -#define MEDIA_AXI_JPW_BASE 0xFE966100 -#define MEDIA_AXI_GCU0R_BASE 0xFE964140 -#define MEDIA_AXI_GCU0W_BASE 0xFE966140 -#define MEDIA_AXI_GCU1R_BASE 0xFE964180 -#define MEDIA_AXI_GCU1W_BASE 0xFE966180 -#define MEDIA_AXI_TDMR_BASE 0xFE964500 -#define MEDIA_AXI_TDMW_BASE 0xFE966500 -#define MEDIA_AXI_VSP0CR_BASE 0xFE964540 -#define MEDIA_AXI_VSP0CW_BASE 0xFE966540 -#define MEDIA_AXI_VSP1CR_BASE 0xFE964580 -#define MEDIA_AXI_VSP1CW_BASE 0xFE966580 -#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0 -#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0 -#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600 -#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600 -#define MEDIA_AXI_VIN0W_BASE 0xFE966900 -#define MEDIA_AXI_VSP0R_BASE 0xFE964D00 -#define MEDIA_AXI_VSP0W_BASE 0xFE966D00 -#define MEDIA_AXI_FDP0R_BASE 0xFE964D40 -#define MEDIA_AXI_FDP0W_BASE 0xFE966D40 -#define MEDIA_AXI_IMSR_BASE 0xFE964D80 -#define MEDIA_AXI_IMSW_BASE 0xFE966D80 -#define MEDIA_AXI_VSP1R_BASE 0xFE965100 -#define MEDIA_AXI_VSP1W_BASE 0xFE967100 -#define MEDIA_AXI_FDP1R_BASE 0xFE965140 -#define MEDIA_AXI_FDP1W_BASE 0xFE967140 -#define MEDIA_AXI_IMRR_BASE 0xFE965180 -#define MEDIA_AXI_IMRW_BASE 0xFE967180 -#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0 -#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0 -#define MEDIA_AXI_VSPD0R_BASE 0xFE965500 -#define MEDIA_AXI_VSPD0W_BASE 0xFE967500 -#define MEDIA_AXI_VSPD1R_BASE 0xFE965540 -#define MEDIA_AXI_VSPD1W_BASE 0xFE967540 -#define MEDIA_AXI_DU0R_BASE 0xFE965580 -#define MEDIA_AXI_DU0W_BASE 0xFE967580 -#define MEDIA_AXI_DU1R_BASE 0xFE9655C0 -#define MEDIA_AXI_DU1W_BASE 0xFE9675C0 -#define MEDIA_AXI_VCP0CR_BASE 0xFE965900 -#define MEDIA_AXI_VCP0CW_BASE 0xFE967900 -#define MEDIA_AXI_VCP0VR_BASE 0xFE965940 -#define MEDIA_AXI_VCP0VW_BASE 0xFE967940 -#define MEDIA_AXI_VPC0R_BASE 0xFE965980 -#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00 -#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00 -#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40 -#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40 -#define MEDIA_AXI_VPC1R_BASE 0xFE965D80 - -#define SYS_AXI_AVBDMSCR 0xFF802000 -#define SYS_AXI_SYX2DMSCR 0xFF802004 -#define SYS_AXI_CC50DMSCR 0xFF802008 -#define SYS_AXI_CC51DMSCR 0xFF80200C -#define SYS_AXI_CCIDMSCR 0xFF802010 -#define SYS_AXI_CSDMSCR 0xFF802014 -#define SYS_AXI_DDMDMSCR 0xFF802018 -#define SYS_AXI_ETHDMSCR 0xFF80201C -#define SYS_AXI_G2DDMSCR 0xFF802020 -#define SYS_AXI_IMP0DMSCR 0xFF802024 -#define SYS_AXI_IMP1DMSCR 0xFF802028 -#define SYS_AXI_LBSDMSCR 0xFF80202C -#define SYS_AXI_MMUDSDMSCR 0xFF802030 -#define SYS_AXI_MMUMXDMSCR 0xFF802034 -#define SYS_AXI_MMURDDMSCR 0xFF802038 -#define SYS_AXI_MMUS0DMSCR 0xFF80203C -#define SYS_AXI_MMUS1DMSCR 0xFF802040 -#define SYS_AXI_MPXDMSCR 0xFF802044 -#define SYS_AXI_MTSB0DMSCR 0xFF802048 -#define SYS_AXI_MTSB1DMSCR 0xFF80204C -#define SYS_AXI_PCIDMSCR 0xFF802050 -#define SYS_AXI_RTXDMSCR 0xFF802054 -#define SYS_AXI_SAT0DMSCR 0xFF802058 -#define SYS_AXI_SAT1DMSCR 0xFF80205C -#define SYS_AXI_SDM0DMSCR 0xFF802060 -#define SYS_AXI_SDM1DMSCR 0xFF802064 -#define SYS_AXI_SDS0DMSCR 0xFF802068 -#define SYS_AXI_SDS1DMSCR 0xFF80206C -#define SYS_AXI_ETRABDMSCR 0xFF802070 -#define SYS_AXI_ETRKFDMSCR 0xFF802074 -#define SYS_AXI_UDM0DMSCR 0xFF802078 -#define SYS_AXI_UDM1DMSCR 0xFF80207C -#define SYS_AXI_USB20DMSCR 0xFF802080 -#define SYS_AXI_USB21DMSCR 0xFF802084 -#define SYS_AXI_USB22DMSCR 0xFF802088 -#define SYS_AXI_USB30DMSCR 0xFF80208C -#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100 -#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104 -#define SYS_AXI_AVBSLVDMSCR 0xFF802108 -#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C -#define SYS_AXI_ETHSLVDMSCR 0xFF802110 -#define SYS_AXI_GICSLVDMSCR 0xFF802114 -#define SYS_AXI_IMPSLVDMSCR 0xFF802118 -#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C -#define SYS_AXI_IMX1SLVDMSCR 0xFF802120 -#define SYS_AXI_IMX2SLVDMSCR 0xFF802124 -#define SYS_AXI_LBSSLVDMSCR 0xFF802128 -#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C -#define SYS_AXI_MMC1SLVDMSCR 0xFF802130 -#define SYS_AXI_MPXSLVDMSCR 0xFF802134 -#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138 -#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C -#define SYS_AXI_MXTSLVDMSCR 0xFF802140 -#define SYS_AXI_PCISLVDMSCR 0xFF802144 -#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148 -#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C -#define SYS_AXI_RTXSLVDMSCR 0xFF802150 -#define SYS_AXI_SAT0SLVDMSCR 0xFF802168 -#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C -#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170 -#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174 -#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178 -#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C -#define SYS_AXI_SGXSLVDMSCR 0xFF802180 -#define SYS_AXI_STBSLVDMSCR 0xFF802188 -#define SYS_AXI_STMSLVDMSCR 0xFF80218C -#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194 -#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198 -#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C -#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0 -#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4 -#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8 -#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC - -#define RT_AXI_CBMDMSCR 0xFF812000 -#define RT_AXI_DBDMSCR 0xFF812004 -#define RT_AXI_RDMDMSCR 0xFF812008 -#define RT_AXI_RDSDMSCR 0xFF81200C -#define RT_AXI_STRDMSCR 0xFF812010 -#define RT_AXI_SY2RTDMSCR 0xFF812014 -#define RT_AXI_CBSSLVDMSCR 0xFF812100 -#define RT_AXI_DBSSLVDMSCR 0xFF812104 -#define RT_AXI_RTAP1SLVDMSCR 0xFF812108 -#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C -#define RT_AXI_RTAP3SLVDMSCR 0xFF812110 -#define RT_AXI_RT2SYSLVDMSCR 0xFF812114 -#define RT_AXI_A128TO64SLVDMSCR 0xFF812118 -#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C -#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120 -#define RT_AXI_UTLBRSLVDMSCR 0xFF812128 - -#define MP_AXI_ADSPDMSCR 0xFF822000 -#define MP_AXI_ASDM0DMSCR 0xFF822004 -#define MP_AXI_ASDM1DMSCR 0xFF822008 -#define MP_AXI_ASDS0DMSCR 0xFF82200C -#define MP_AXI_ASDS1DMSCR 0xFF822010 -#define MP_AXI_MLPDMSCR 0xFF822014 -#define MP_AXI_MMUMPDMSCR 0xFF822018 -#define MP_AXI_SPUDMSCR 0xFF82201C -#define MP_AXI_SPUCDMSCR 0xFF822020 -#define MP_AXI_SY2MPDMSCR 0xFF822024 -#define MP_AXI_ADSPSLVDMSCR 0xFF822100 -#define MP_AXI_MLMSLVDMSCR 0xFF822104 -#define MP_AXI_MPAP4SLVDMSCR 0xFF822108 -#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C -#define MP_AXI_MPAP6SLVDMSCR 0xFF822110 -#define MP_AXI_MPAP7SLVDMSCR 0xFF822114 -#define MP_AXI_MP2SYSLVDMSCR 0xFF822118 -#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C -#define MP_AXI_MPXAPSLVDMSCR 0xFF822124 -#define MP_AXI_SPUSLVDMSCR 0xFF822128 -#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C - -#define ADM_AXI_ASDM0DMSCR 0xFF842000 -#define ADM_AXI_ASDM1DMSCR 0xFF842004 -#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104 -#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108 -#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C - -#define DM_AXI_RDMDMSCR 0xFF852000 -#define DM_AXI_SDM0DMSCR 0xFF852004 -#define DM_AXI_SDM1DMSCR 0xFF852008 -#define DM_AXI_MMAP0SLVDMSCR 0xFF852100 -#define DM_AXI_MMAP1SLVDMSCR 0xFF852104 -#define DM_AXI_QSPAPSLVDMSCR 0xFF852108 -#define DM_AXI_RAP4SLVDMSCR 0xFF85210C -#define DM_AXI_RAP5SLVDMSCR 0xFF852110 -#define DM_AXI_SAP4SLVDMSCR 0xFF852114 -#define DM_AXI_SAP5SLVDMSCR 0xFF852118 -#define DM_AXI_SAP6SLVDMSCR 0xFF85211C -#define DM_AXI_SAP65SLVDMSCR 0xFF852120 -#define DM_AXI_SDAP0SLVDMSCR 0xFF852124 -#define DM_AXI_SDAP1SLVDMSCR 0xFF852128 -#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C -#define DM_AXI_SDAP3SLVDMSCR 0xFF852130 - -#define SYS_AXI256_SYXDMSCR 0xFF862000 -#define SYS_AXI256_MPXDMSCR 0xFF862004 -#define SYS_AXI256_MXIDMSCR 0xFF862008 -#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100 -#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104 -#define SYS_AXI256_SYXSLVDMSCR 0xFF862108 -#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C -#define SYS_AXI256_S3CSLVDMSCR 0xFF862110 - -#define MXT_SYXDMSCR 0xFF872000 -#define MXT_CMM0SLVDMSCR 0xFF872100 -#define MXT_CMM1SLVDMSCR 0xFF872104 -#define MXT_CMM2SLVDMSCR 0xFF872108 -#define MXT_FDPSLVDMSCR 0xFF87210C -#define MXT_IMRSLVDMSCR 0xFF872110 -#define MXT_VINSLVDMSCR 0xFF872114 -#define MXT_VPC0SLVDMSCR 0xFF872118 -#define MXT_VPC1SLVDMSCR 0xFF87211C -#define MXT_VSP0SLVDMSCR 0xFF872120 -#define MXT_VSP1SLVDMSCR 0xFF872124 -#define MXT_VSPD0SLVDMSCR 0xFF872128 -#define MXT_VSPD1SLVDMSCR 0xFF87212C -#define MXT_MAP1SLVDMSCR 0xFF872130 -#define MXT_MAP2SLVDMSCR 0xFF872134 - -#define CCI_AXI_MMUS0DMSCR 0xFF882000 -#define CCI_AXI_SYX2DMSCR 0xFF882004 -#define CCI_AXI_MMURDMSCR 0xFF882008 -#define CCI_AXI_MMUDSDMSCR 0xFF88200C -#define CCI_AXI_MMUMDMSCR 0xFF882010 -#define CCI_AXI_MXIDMSCR 0xFF882014 -#define CCI_AXI_MMUS1DMSCR 0xFF882018 -#define CCI_AXI_MMUMPDMSCR 0xFF88201C -#define CCI_AXI_DVMDMSCR 0xFF882020 -#define CCI_AXI_CCISLVDMSCR 0xFF882100 - -#define CCI_AXI_IPMMUIDVMCR 0xFF880400 -#define CCI_AXI_IPMMURDVMCR 0xFF880404 -#define CCI_AXI_IPMMUS0DVMCR 0xFF880408 -#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C -#define CCI_AXI_IPMMUMPDVMCR 0xFF880410 -#define CCI_AXI_IPMMUDSDVMCR 0xFF880414 -#define CCI_AXI_AX2ADDRMASK 0xFF88041C - -#ifndef __ASSEMBLY__ -#include <asm/types.h> - -/* RWDT */ -struct r8a7791_rwdt { - u32 rwtcnt; /* 0x00 */ - u32 rwtcsra; /* 0x04 */ - u16 rwtcsrb; /* 0x08 */ -}; - -/* SWDT */ -struct r8a7791_swdt { - u32 swtcnt; /* 0x00 */ - u32 swtcsra; /* 0x04 */ - u16 swtcsrb; /* 0x08 */ -}; - -/* LBSC */ -struct r8a7791_lbsc { - u32 cs0ctrl; - u32 cs1ctrl; - u32 ecs0ctrl; - u32 ecs1ctrl; - u32 ecs2ctrl; - u32 ecs3ctrl; - u32 ecs4ctrl; - u32 ecs5ctrl; - u32 dummy0[4]; /* 0x20 .. 0x2C */ - u32 cswcr0; - u32 cswcr1; - u32 ecswcr0; - u32 ecswcr1; - u32 ecswcr2; - u32 ecswcr3; - u32 ecswcr4; - u32 ecswcr5; - u32 exdmawcr0; - u32 exdmawcr1; - u32 exdmawcr2; - u32 dummy1[9]; /* 0x5C .. 0x7C */ - u32 cspwcr0; - u32 cspwcr1; - u32 ecspwcr0; - u32 ecspwcr1; - u32 ecspwcr2; - u32 ecspwcr3; - u32 ecspwcr4; - u32 ecspwcr5; - u32 exwtsync; - u32 dummy2[3]; /* 0xA4 .. 0xAC */ - u32 cs0bstctl; - u32 cs0btph; - u32 dummy3[2]; /* 0xB8 .. 0xBC */ - u32 cs1gdst; - u32 ecs0gdst; - u32 ecs1gdst; - u32 ecs2gdst; - u32 ecs3gdst; - u32 ecs4gdst; - u32 ecs5gdst; - u32 dummy4[5]; /* 0xDC .. 0xEC */ - u32 exdmaset0; - u32 exdmaset1; - u32 exdmaset2; - u32 dummy5[5]; /* 0xFC .. 0x10C */ - u32 exdmcr0; - u32 exdmcr1; - u32 exdmcr2; - u32 dummy6[5]; /* 0x11C .. 0x12C */ - u32 bcintsr; - u32 bcintcr; - u32 bcintmr; - u32 dummy7; /* 0x13C */ - u32 exbatlv; - u32 exwtsts; - u32 dummy8[14]; /* 0x148 .. 0x17C */ - u32 atacsctrl; - u32 dummy9[15]; /* 0x184 .. 0x1BC */ - u32 exbct; - u32 extct; -}; - -/* DBSC3 */ -struct r8a7791_dbsc3 { - u32 dummy0[3]; /* 0x00 .. 0x08 */ - u32 dbstate1; - u32 dbacen; - u32 dbrfen; - u32 dbcmd; - u32 dbwait; - u32 dbkind; - u32 dbconf0; - u32 dummy1[2]; /* 0x28 .. 0x2C */ - u32 dbphytype; - u32 dummy2[3]; /* 0x34 .. 0x3C */ - u32 dbtr0; - u32 dbtr1; - u32 dbtr2; - u32 dummy3; /* 0x4C */ - u32 dbtr3; - u32 dbtr4; - u32 dbtr5; - u32 dbtr6; - u32 dbtr7; - u32 dbtr8; - u32 dbtr9; - u32 dbtr10; - u32 dbtr11; - u32 dbtr12; - u32 dbtr13; - u32 dbtr14; - u32 dbtr15; - u32 dbtr16; - u32 dbtr17; - u32 dbtr18; - u32 dbtr19; - u32 dummy4[7]; /* 0x94 .. 0xAC */ - u32 dbbl; - u32 dummy5[3]; /* 0xB4 .. 0xBC */ - u32 dbadj0; - u32 dummy6; /* 0xC4 */ - u32 dbadj2; - u32 dummy7[5]; /* 0xCC .. 0xDC */ - u32 dbrfcnf0; - u32 dbrfcnf1; - u32 dbrfcnf2; - u32 dummy8[2]; /* 0xEC .. 0xF0 */ - u32 dbcalcnf; - u32 dbcaltr; - u32 dummy9; /* 0xFC */ - u32 dbrnk0; - u32 dummy10[31]; /* 0x104 .. 0x17C */ - u32 dbpdncnf; - u32 dummy11[47]; /* 0x184 ..0x23C */ - u32 dbdfistat; - u32 dbdficnt; - u32 dummy12[14]; /* 0x248 .. 0x27C */ - u32 dbpdlck; - u32 dummy13[3]; /* 0x284 .. 0x28C */ - u32 dbpdrga; - u32 dummy14[3]; /* 0x294 .. 0x29C */ - u32 dbpdrgd; - u32 dummy15[24]; /* 0x2A4 .. 0x300 */ - u32 dbbs0cnt1; - u32 dummy16[30]; /* 0x308 .. 0x37C */ - u32 dbwt0cnf0; - u32 dbwt0cnf1; - u32 dbwt0cnf2; - u32 dbwt0cnf3; - u32 dbwt0cnf4; -}; - -/* GPIO */ -struct r8a7791_gpio { - u32 iointsel; - u32 inoutsel; - u32 outdt; - u32 indt; - u32 intdt; - u32 intclr; - u32 intmsk; - u32 posneg; - u32 edglevel; - u32 filonoff; - u32 intmsks; - u32 mskclrs; - u32 outdtsel; - u32 outdth; - u32 outdtl; - u32 bothedge; -}; - -/* S3C(QoS) */ -struct r8a7791_s3c { - u32 s3cexcladdmsk; - u32 s3cexclidmsk; - u32 s3cadsplcr; - u32 s3cmaar; - u32 dummy0; /* 0x10 */ - u32 s3crorr; - u32 s3cworr; - u32 s3carcr22; - u32 dummy1[2]; /* 0x20 .. 0x24 */ - u32 s3cmctr; - u32 dummy2; /* 0x2C */ - u32 cconf0; - u32 cconf1; - u32 cconf2; - u32 cconf3; -}; - -struct r8a7791_s3c_qos { - u32 s3cqos0; - u32 s3cqos1; - u32 s3cqos2; - u32 s3cqos3; - u32 s3cqos4; - u32 s3cqos5; - u32 s3cqos6; - u32 s3cqos7; - u32 s3cqos8; -}; - -/* DBSC(QoS) */ -struct r8a7791_dbsc3_qos { - u32 dblgcnt; - u32 dbtmval0; - u32 dbtmval1; - u32 dbtmval2; - u32 dbtmval3; - u32 dbrqctr; - u32 dbthres0; - u32 dbthres1; - u32 dbthres2; - u32 dummy0; /* 0x24 */ - u32 dblgqon; -}; - -/* MXI(QoS) */ -struct r8a7791_mxi { - u32 mxsaar0; - u32 mxsaar1; - u32 dummy0[8]; /* 0x08 .. 0x24 */ - u32 mxs3cracr; - u32 dummy1[3]; /* 0x2C .. 0x34 */ - u32 mxs3cwacr; - u32 dummy2; /* 0x3C */ - u32 mxrtcr; - u32 mxwtcr; -}; - -struct r8a7791_mxi_qos { - u32 vspdu0; - u32 vspdu1; - u32 du0; - u32 du1; -}; - -/* AXI(QoS) */ -struct r8a7791_axi_qos { - u32 qosconf; - u32 qosctset0; - u32 qosctset1; - u32 qosctset2; - u32 qosctset3; - u32 qosreqctr; - u32 qosthres0; - u32 qosthres1; - u32 qosthres2; - u32 qosqon; -}; - -#endif +#define R8A7791_CUT_ES2X 2 +#define IS_R8A7791_ES2() \ + (rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X) #endif /* __ASM_ARCH_R8A7791_H */ diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h new file mode 100644 index 000000000..41240f332 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h @@ -0,0 +1,645 @@ +/* + * arch/arm/include/asm/arch-rmobile/rcar-base.h + * + * Copyright (C) 2013,2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_RCAR_BASE_H +#define __ASM_ARCH_RCAR_BASE_H + +/* + * R-Car (R8A7790/R8A7791) I/O Addresses + */ +#define RWDT_BASE 0xE6020000 +#define SWDT_BASE 0xE6030000 +#define LBSC_BASE 0xFEC00200 +#define DBSC3_0_BASE 0xE6790000 +#define DBSC3_1_BASE 0xE67A0000 +#define TMU_BASE 0xE61E0000 +#define GPIO5_BASE 0xE6055000 +#define SH_QSPI_BASE 0xE6B10000 + +/* SCIF */ +#define SCIF0_BASE 0xE6E60000 +#define SCIF1_BASE 0xE6E68000 +#define SCIF2_BASE 0xE6E58000 +#define SCIF3_BASE 0xE6EA8000 +#define SCIF4_BASE 0xE6EE0000 +#define SCIF5_BASE 0xE6EE8000 + +#define S3C_BASE 0xE6784000 +#define S3C_INT_BASE 0xE6784A00 +#define S3C_MEDIA_BASE 0xE6784B00 + +#define S3C_QOS_DCACHE_BASE 0xE6784BDC +#define S3C_QOS_CCI0_BASE 0xE6784C00 +#define S3C_QOS_CCI1_BASE 0xE6784C24 +#define S3C_QOS_MXI_BASE 0xE6784C48 +#define S3C_QOS_AXI_BASE 0xE6784C6C + +#define DBSC3_0_QOS_R0_BASE 0xE6791000 +#define DBSC3_0_QOS_R1_BASE 0xE6791100 +#define DBSC3_0_QOS_R2_BASE 0xE6791200 +#define DBSC3_0_QOS_R3_BASE 0xE6791300 +#define DBSC3_0_QOS_R4_BASE 0xE6791400 +#define DBSC3_0_QOS_R5_BASE 0xE6791500 +#define DBSC3_0_QOS_R6_BASE 0xE6791600 +#define DBSC3_0_QOS_R7_BASE 0xE6791700 +#define DBSC3_0_QOS_R8_BASE 0xE6791800 +#define DBSC3_0_QOS_R9_BASE 0xE6791900 +#define DBSC3_0_QOS_R10_BASE 0xE6791A00 +#define DBSC3_0_QOS_R11_BASE 0xE6791B00 +#define DBSC3_0_QOS_R12_BASE 0xE6791C00 +#define DBSC3_0_QOS_R13_BASE 0xE6791D00 +#define DBSC3_0_QOS_R14_BASE 0xE6791E00 +#define DBSC3_0_QOS_R15_BASE 0xE6791F00 +#define DBSC3_0_QOS_W0_BASE 0xE6792000 +#define DBSC3_0_QOS_W1_BASE 0xE6792100 +#define DBSC3_0_QOS_W2_BASE 0xE6792200 +#define DBSC3_0_QOS_W3_BASE 0xE6792300 +#define DBSC3_0_QOS_W4_BASE 0xE6792400 +#define DBSC3_0_QOS_W5_BASE 0xE6792500 +#define DBSC3_0_QOS_W6_BASE 0xE6792600 +#define DBSC3_0_QOS_W7_BASE 0xE6792700 +#define DBSC3_0_QOS_W8_BASE 0xE6792800 +#define DBSC3_0_QOS_W9_BASE 0xE6792900 +#define DBSC3_0_QOS_W10_BASE 0xE6792A00 +#define DBSC3_0_QOS_W11_BASE 0xE6792B00 +#define DBSC3_0_QOS_W12_BASE 0xE6792C00 +#define DBSC3_0_QOS_W13_BASE 0xE6792D00 +#define DBSC3_0_QOS_W14_BASE 0xE6792E00 +#define DBSC3_0_QOS_W15_BASE 0xE6792F00 +#define DBSC3_0_DBADJ2 0xE67900C8 + +#define CCI_400_MAXOT_1 0xF0091110 +#define CCI_400_MAXOT_2 0xF0092110 +#define CCI_400_QOSCNTL_1 0xF009110C +#define CCI_400_QOSCNTL_2 0xF009210C + +#define MXI_BASE 0xFE960000 +#define MXI_QOS_BASE 0xFE960300 + +#define SYS_AXI_SYX64TO128_BASE 0xFF800300 +#define SYS_AXI_AVB_BASE 0xFF800340 +#define SYS_AXI_G2D_BASE 0xFF800540 +#define SYS_AXI_IMP0_BASE 0xFF800580 +#define SYS_AXI_IMP1_BASE 0xFF8005C0 +#define SYS_AXI_IMUX0_BASE 0xFF800600 +#define SYS_AXI_IMUX1_BASE 0xFF800640 +#define SYS_AXI_IMUX2_BASE 0xFF800680 +#define SYS_AXI_LBS_BASE 0xFF8006C0 +#define SYS_AXI_MMUDS_BASE 0xFF800700 +#define SYS_AXI_MMUM_BASE 0xFF800740 +#define SYS_AXI_MMUR_BASE 0xFF800780 +#define SYS_AXI_MMUS0_BASE 0xFF8007C0 +#define SYS_AXI_MMUS1_BASE 0xFF800800 +#define SYS_AXI_MTSB0_BASE 0xFF800880 +#define SYS_AXI_MTSB1_BASE 0xFF8008C0 +#define SYS_AXI_PCI_BASE 0xFF800900 +#define SYS_AXI_RTX_BASE 0xFF800940 +#define SYS_AXI_SDS0_BASE 0xFF800A80 +#define SYS_AXI_SDS1_BASE 0xFF800AC0 +#define SYS_AXI_USB20_BASE 0xFF800C00 +#define SYS_AXI_USB21_BASE 0xFF800C40 +#define SYS_AXI_USB22_BASE 0xFF800C80 +#define SYS_AXI_USB30_BASE 0xFF800CC0 +#define SYS_AXI_AX2M_BASE 0xFF800380 +#define SYS_AXI_CC50_BASE 0xFF8003C0 +#define SYS_AXI_CCI_BASE 0xFF800440 +#define SYS_AXI_CS_BASE 0xFF800480 +#define SYS_AXI_DDM_BASE 0xFF8004C0 +#define SYS_AXI_ETH_BASE 0xFF800500 +#define SYS_AXI_MPXM_BASE 0xFF800840 +#define SYS_AXI_SAT0_BASE 0xFF800980 +#define SYS_AXI_SAT1_BASE 0xFF8009C0 +#define SYS_AXI_SDM0_BASE 0xFF800A00 +#define SYS_AXI_SDM1_BASE 0xFF800A40 +#define SYS_AXI_TRAB_BASE 0xFF800B00 +#define SYS_AXI_UDM0_BASE 0xFF800B80 +#define SYS_AXI_UDM1_BASE 0xFF800BC0 + +#define RT_AXI_SHX_BASE 0xFF810100 +#define RT_AXI_DBG_BASE 0xFF810140 /* R8A7791 only */ +#define RT_AXI_RDM_BASE 0xFF810180 /* R8A7791 only */ +#define RT_AXI_RDS_BASE 0xFF8101C0 +#define RT_AXI_RTX64TO128_BASE 0xFF810200 +#define RT_AXI_STPRO_BASE 0xFF810240 +#define RT_AXI_SY2RT_BASE 0xFF810280 /* R8A7791 only */ + +#define MP_AXI_ADSP_BASE 0xFF820100 +#define MP_AXI_ASDS0_BASE 0xFF8201C0 +#define MP_AXI_ASDS1_BASE 0xFF820200 +#define MP_AXI_MLP_BASE 0xFF820240 +#define MP_AXI_MMUMP_BASE 0xFF820280 +#define MP_AXI_SPU_BASE 0xFF8202C0 +#define MP_AXI_SPUC_BASE 0xFF820300 + +#define SYS_AXI256_AXI128TO256_BASE 0xFF860100 +#define SYS_AXI256_SYX_BASE 0xFF860140 +#define SYS_AXI256_MPX_BASE 0xFF860180 +#define SYS_AXI256_MXI_BASE 0xFF8601C0 + +#define CCI_AXI_MMUS0_BASE 0xFF880100 +#define CCI_AXI_SYX2_BASE 0xFF880140 +#define CCI_AXI_MMUR_BASE 0xFF880180 +#define CCI_AXI_MMUDS_BASE 0xFF8801C0 +#define CCI_AXI_MMUM_BASE 0xFF880200 +#define CCI_AXI_MXI_BASE 0xFF880240 +#define CCI_AXI_MMUS1_BASE 0xFF880280 +#define CCI_AXI_MMUMP_BASE 0xFF8802C0 + +#define MEDIA_AXI_MXR_BASE 0xFE960080 /* R8A7791 only */ +#define MEDIA_AXI_MXW_BASE 0xFE9600C0 /* R8A7791 only */ +#define MEDIA_AXI_JPR_BASE 0xFE964100 +#define MEDIA_AXI_JPW_BASE 0xFE966100 +#define MEDIA_AXI_GCU0R_BASE 0xFE964140 +#define MEDIA_AXI_GCU0W_BASE 0xFE966140 +#define MEDIA_AXI_GCU1R_BASE 0xFE964180 +#define MEDIA_AXI_GCU1W_BASE 0xFE966180 +#define MEDIA_AXI_TDMR_BASE 0xFE964500 +#define MEDIA_AXI_TDMW_BASE 0xFE966500 +#define MEDIA_AXI_VSP0CR_BASE 0xFE964540 +#define MEDIA_AXI_VSP0CW_BASE 0xFE966540 +#define MEDIA_AXI_VSP1CR_BASE 0xFE964580 +#define MEDIA_AXI_VSP1CW_BASE 0xFE966580 +#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0 +#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0 +#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600 +#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600 +#define MEDIA_AXI_VIN0W_BASE 0xFE966900 +#define MEDIA_AXI_VSP0R_BASE 0xFE964D00 +#define MEDIA_AXI_VSP0W_BASE 0xFE966D00 +#define MEDIA_AXI_FDP0R_BASE 0xFE964D40 +#define MEDIA_AXI_FDP0W_BASE 0xFE966D40 +#define MEDIA_AXI_IMSR_BASE 0xFE964D80 +#define MEDIA_AXI_IMSW_BASE 0xFE966D80 +#define MEDIA_AXI_VSP1R_BASE 0xFE965100 +#define MEDIA_AXI_VSP1W_BASE 0xFE967100 +#define MEDIA_AXI_FDP1R_BASE 0xFE965140 +#define MEDIA_AXI_FDP1W_BASE 0xFE967140 +#define MEDIA_AXI_IMRR_BASE 0xFE965180 +#define MEDIA_AXI_IMRW_BASE 0xFE967180 +#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0 +#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0 +#define MEDIA_AXI_VSPD0R_BASE 0xFE965500 +#define MEDIA_AXI_VSPD0W_BASE 0xFE967500 +#define MEDIA_AXI_VSPD1R_BASE 0xFE965540 +#define MEDIA_AXI_VSPD1W_BASE 0xFE967540 +#define MEDIA_AXI_DU0R_BASE 0xFE965580 +#define MEDIA_AXI_DU0W_BASE 0xFE967580 +#define MEDIA_AXI_DU1R_BASE 0xFE9655C0 +#define MEDIA_AXI_DU1W_BASE 0xFE9675C0 +#define MEDIA_AXI_VCP0CR_BASE 0xFE965900 +#define MEDIA_AXI_VCP0CW_BASE 0xFE967900 +#define MEDIA_AXI_VCP0VR_BASE 0xFE965940 +#define MEDIA_AXI_VCP0VW_BASE 0xFE967940 +#define MEDIA_AXI_VPC0R_BASE 0xFE965980 +#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00 +#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00 +#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40 +#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40 +#define MEDIA_AXI_VPC1R_BASE 0xFE965D80 + +#define SYS_AXI_AVBDMSCR 0xFF802000 +#define SYS_AXI_SYX2DMSCR 0xFF802004 +#define SYS_AXI_CC50DMSCR 0xFF802008 +#define SYS_AXI_CC51DMSCR 0xFF80200C +#define SYS_AXI_CCIDMSCR 0xFF802010 +#define SYS_AXI_CSDMSCR 0xFF802014 +#define SYS_AXI_DDMDMSCR 0xFF802018 +#define SYS_AXI_ETHDMSCR 0xFF80201C +#define SYS_AXI_G2DDMSCR 0xFF802020 +#define SYS_AXI_IMP0DMSCR 0xFF802024 +#define SYS_AXI_IMP1DMSCR 0xFF802028 +#define SYS_AXI_LBSDMSCR 0xFF80202C +#define SYS_AXI_MMUDSDMSCR 0xFF802030 +#define SYS_AXI_MMUMXDMSCR 0xFF802034 +#define SYS_AXI_MMURDDMSCR 0xFF802038 +#define SYS_AXI_MMUS0DMSCR 0xFF80203C +#define SYS_AXI_MMUS1DMSCR 0xFF802040 +#define SYS_AXI_MPXDMSCR 0xFF802044 +#define SYS_AXI_MTSB0DMSCR 0xFF802048 +#define SYS_AXI_MTSB1DMSCR 0xFF80204C +#define SYS_AXI_PCIDMSCR 0xFF802050 +#define SYS_AXI_RTXDMSCR 0xFF802054 +#define SYS_AXI_SAT0DMSCR 0xFF802058 +#define SYS_AXI_SAT1DMSCR 0xFF80205C +#define SYS_AXI_SDM0DMSCR 0xFF802060 +#define SYS_AXI_SDM1DMSCR 0xFF802064 +#define SYS_AXI_SDS0DMSCR 0xFF802068 +#define SYS_AXI_SDS1DMSCR 0xFF80206C +#define SYS_AXI_ETRABDMSCR 0xFF802070 +#define SYS_AXI_ETRKFDMSCR 0xFF802074 +#define SYS_AXI_UDM0DMSCR 0xFF802078 +#define SYS_AXI_UDM1DMSCR 0xFF80207C +#define SYS_AXI_USB20DMSCR 0xFF802080 +#define SYS_AXI_USB21DMSCR 0xFF802084 +#define SYS_AXI_USB22DMSCR 0xFF802088 +#define SYS_AXI_USB30DMSCR 0xFF80208C +#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100 +#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104 +#define SYS_AXI_AVBSLVDMSCR 0xFF802108 +#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C +#define SYS_AXI_ETHSLVDMSCR 0xFF802110 +#define SYS_AXI_GICSLVDMSCR 0xFF802114 +#define SYS_AXI_IMPSLVDMSCR 0xFF802118 +#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C +#define SYS_AXI_IMX1SLVDMSCR 0xFF802120 +#define SYS_AXI_IMX2SLVDMSCR 0xFF802124 +#define SYS_AXI_LBSSLVDMSCR 0xFF802128 +#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C +#define SYS_AXI_MMC1SLVDMSCR 0xFF802130 +#define SYS_AXI_MPXSLVDMSCR 0xFF802134 +#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138 +#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C +#define SYS_AXI_MXTSLVDMSCR 0xFF802140 +#define SYS_AXI_PCISLVDMSCR 0xFF802144 +#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148 +#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C +#define SYS_AXI_RTXSLVDMSCR 0xFF802150 +#define SYS_AXI_SAT0SLVDMSCR 0xFF802168 +#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C +#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170 +#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174 +#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178 +#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C +#define SYS_AXI_SGXSLVDMSCR 0xFF802180 +#define SYS_AXI_STBSLVDMSCR 0xFF802188 +#define SYS_AXI_STMSLVDMSCR 0xFF80218C +#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194 +#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198 +#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C +#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0 +#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4 +#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8 +#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC + +#define RT_AXI_CBMDMSCR 0xFF812000 +#define RT_AXI_DBDMSCR 0xFF812004 +#define RT_AXI_RDMDMSCR 0xFF812008 +#define RT_AXI_RDSDMSCR 0xFF81200C +#define RT_AXI_STRDMSCR 0xFF812010 +#define RT_AXI_SY2RTDMSCR 0xFF812014 +#define RT_AXI_CBSSLVDMSCR 0xFF812100 +#define RT_AXI_DBSSLVDMSCR 0xFF812104 +#define RT_AXI_RTAP1SLVDMSCR 0xFF812108 +#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C +#define RT_AXI_RTAP3SLVDMSCR 0xFF812110 +#define RT_AXI_RT2SYSLVDMSCR 0xFF812114 +#define RT_AXI_A128TO64SLVDMSCR 0xFF812118 +#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C +#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120 +#define RT_AXI_UTLBRSLVDMSCR 0xFF812128 + +#define MP_AXI_ADSPDMSCR 0xFF822000 +#define MP_AXI_ASDM0DMSCR 0xFF822004 +#define MP_AXI_ASDM1DMSCR 0xFF822008 +#define MP_AXI_ASDS0DMSCR 0xFF82200C +#define MP_AXI_ASDS1DMSCR 0xFF822010 +#define MP_AXI_MLPDMSCR 0xFF822014 +#define MP_AXI_MMUMPDMSCR 0xFF822018 +#define MP_AXI_SPUDMSCR 0xFF82201C +#define MP_AXI_SPUCDMSCR 0xFF822020 +#define MP_AXI_SY2MPDMSCR 0xFF822024 +#define MP_AXI_ADSPSLVDMSCR 0xFF822100 +#define MP_AXI_MLMSLVDMSCR 0xFF822104 +#define MP_AXI_MPAP4SLVDMSCR 0xFF822108 +#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C +#define MP_AXI_MPAP6SLVDMSCR 0xFF822110 +#define MP_AXI_MPAP7SLVDMSCR 0xFF822114 +#define MP_AXI_MP2SYSLVDMSCR 0xFF822118 +#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C +#define MP_AXI_MPXAPSLVDMSCR 0xFF822124 +#define MP_AXI_SPUSLVDMSCR 0xFF822128 +#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C + +#define ADM_AXI_ASDM0DMSCR 0xFF842000 +#define ADM_AXI_ASDM1DMSCR 0xFF842004 +#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104 +#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108 +#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C + +#define DM_AXI_RDMDMSCR 0xFF852000 +#define DM_AXI_SDM0DMSCR 0xFF852004 +#define DM_AXI_SDM1DMSCR 0xFF852008 +#define DM_AXI_MMAP0SLVDMSCR 0xFF852100 +#define DM_AXI_MMAP1SLVDMSCR 0xFF852104 +#define DM_AXI_QSPAPSLVDMSCR 0xFF852108 +#define DM_AXI_RAP4SLVDMSCR 0xFF85210C +#define DM_AXI_RAP5SLVDMSCR 0xFF852110 +#define DM_AXI_SAP4SLVDMSCR 0xFF852114 +#define DM_AXI_SAP5SLVDMSCR 0xFF852118 +#define DM_AXI_SAP6SLVDMSCR 0xFF85211C +#define DM_AXI_SAP65SLVDMSCR 0xFF852120 +#define DM_AXI_SDAP0SLVDMSCR 0xFF852124 +#define DM_AXI_SDAP1SLVDMSCR 0xFF852128 +#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C +#define DM_AXI_SDAP3SLVDMSCR 0xFF852130 + +#define SYS_AXI256_SYXDMSCR 0xFF862000 +#define SYS_AXI256_MPXDMSCR 0xFF862004 +#define SYS_AXI256_MXIDMSCR 0xFF862008 +#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100 +#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104 +#define SYS_AXI256_SYXSLVDMSCR 0xFF862108 +#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C +#define SYS_AXI256_S3CSLVDMSCR 0xFF862110 + +#define MXT_SYXDMSCR 0xFF872000 +#define MXT_CMM0SLVDMSCR 0xFF872100 +#define MXT_CMM1SLVDMSCR 0xFF872104 +#define MXT_CMM2SLVDMSCR 0xFF872108 +#define MXT_FDPSLVDMSCR 0xFF87210C +#define MXT_IMRSLVDMSCR 0xFF872110 +#define MXT_VINSLVDMSCR 0xFF872114 +#define MXT_VPC0SLVDMSCR 0xFF872118 +#define MXT_VPC1SLVDMSCR 0xFF87211C +#define MXT_VSP0SLVDMSCR 0xFF872120 +#define MXT_VSP1SLVDMSCR 0xFF872124 +#define MXT_VSPD0SLVDMSCR 0xFF872128 +#define MXT_VSPD1SLVDMSCR 0xFF87212C +#define MXT_MAP1SLVDMSCR 0xFF872130 +#define MXT_MAP2SLVDMSCR 0xFF872134 + +#define CCI_AXI_MMUS0DMSCR 0xFF882000 +#define CCI_AXI_SYX2DMSCR 0xFF882004 +#define CCI_AXI_MMURDMSCR 0xFF882008 +#define CCI_AXI_MMUDSDMSCR 0xFF88200C +#define CCI_AXI_MMUMDMSCR 0xFF882010 +#define CCI_AXI_MXIDMSCR 0xFF882014 +#define CCI_AXI_MMUS1DMSCR 0xFF882018 +#define CCI_AXI_MMUMPDMSCR 0xFF88201C +#define CCI_AXI_DVMDMSCR 0xFF882020 +#define CCI_AXI_CCISLVDMSCR 0xFF882100 + +#define CCI_AXI_IPMMUIDVMCR 0xFF880400 +#define CCI_AXI_IPMMURDVMCR 0xFF880404 +#define CCI_AXI_IPMMUS0DVMCR 0xFF880408 +#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C +#define CCI_AXI_IPMMUMPDVMCR 0xFF880410 +#define CCI_AXI_IPMMUDSDVMCR 0xFF880414 +#define CCI_AXI_AX2ADDRMASK 0xFF88041C + +#define PLL0CR 0xE61500D8 +#define PLL0_STC_MASK 0x7F000000 +#define PLL0_STC_BIT 24 + +#ifndef __ASSEMBLY__ +#include <asm/types.h> + +/* RWDT */ +struct rcar_rwdt { + u32 rwtcnt; /* 0x00 */ + u32 rwtcsra; /* 0x04 */ + u16 rwtcsrb; /* 0x08 */ +}; + +/* SWDT */ +struct rcar_swdt { + u32 swtcnt; /* 0x00 */ + u32 swtcsra; /* 0x04 */ + u16 swtcsrb; /* 0x08 */ +}; + +/* LBSC */ +struct rcar_lbsc { + u32 cs0ctrl; + u32 cs1ctrl; + u32 ecs0ctrl; + u32 ecs1ctrl; + u32 ecs2ctrl; + u32 ecs3ctrl; + u32 ecs4ctrl; + u32 ecs5ctrl; + u32 dummy0[4]; /* 0x20 .. 0x2C */ + u32 cswcr0; + u32 cswcr1; + u32 ecswcr0; + u32 ecswcr1; + u32 ecswcr2; + u32 ecswcr3; + u32 ecswcr4; + u32 ecswcr5; + u32 exdmawcr0; + u32 exdmawcr1; + u32 exdmawcr2; + u32 dummy1[9]; /* 0x5C .. 0x7C */ + u32 cspwcr0; + u32 cspwcr1; + u32 ecspwcr0; + u32 ecspwcr1; + u32 ecspwcr2; + u32 ecspwcr3; + u32 ecspwcr4; + u32 ecspwcr5; + u32 exwtsync; + u32 dummy2[3]; /* 0xA4 .. 0xAC */ + u32 cs0bstctl; + u32 cs0btph; + u32 dummy3[2]; /* 0xB8 .. 0xBC */ + u32 cs1gdst; + u32 ecs0gdst; + u32 ecs1gdst; + u32 ecs2gdst; + u32 ecs3gdst; + u32 ecs4gdst; + u32 ecs5gdst; + u32 dummy4[5]; /* 0xDC .. 0xEC */ + u32 exdmaset0; + u32 exdmaset1; + u32 exdmaset2; + u32 dummy5[5]; /* 0xFC .. 0x10C */ + u32 exdmcr0; + u32 exdmcr1; + u32 exdmcr2; + u32 dummy6[5]; /* 0x11C .. 0x12C */ + u32 bcintsr; + u32 bcintcr; + u32 bcintmr; + u32 dummy7; /* 0x13C */ + u32 exbatlv; + u32 exwtsts; + u32 dummy8[14]; /* 0x148 .. 0x17C */ + u32 atacsctrl; + u32 dummy9[15]; /* 0x184 .. 0x1BC */ + u32 exbct; + u32 extct; +}; + +/* DBSC3 */ +struct rcar_dbsc3 { + u32 dummy0[3]; /* 0x00 .. 0x08 */ + u32 dbstate1; + u32 dbacen; + u32 dbrfen; + u32 dbcmd; + u32 dbwait; + u32 dbkind; + u32 dbconf0; + u32 dummy1[2]; /* 0x28 .. 0x2C */ + u32 dbphytype; + u32 dummy2[3]; /* 0x34 .. 0x3C */ + u32 dbtr0; + u32 dbtr1; + u32 dbtr2; + u32 dummy3; /* 0x4C */ + u32 dbtr3; + u32 dbtr4; + u32 dbtr5; + u32 dbtr6; + u32 dbtr7; + u32 dbtr8; + u32 dbtr9; + u32 dbtr10; + u32 dbtr11; + u32 dbtr12; + u32 dbtr13; + u32 dbtr14; + u32 dbtr15; + u32 dbtr16; + u32 dbtr17; + u32 dbtr18; + u32 dbtr19; + u32 dummy4[7]; /* 0x94 .. 0xAC */ + u32 dbbl; + u32 dummy5[3]; /* 0xB4 .. 0xBC */ + u32 dbadj0; + u32 dummy6; /* 0xC4 */ + u32 dbadj2; + u32 dummy7[5]; /* 0xCC .. 0xDC */ + u32 dbrfcnf0; + u32 dbrfcnf1; + u32 dbrfcnf2; + u32 dummy8[2]; /* 0xEC .. 0xF0 */ + u32 dbcalcnf; + u32 dbcaltr; + u32 dummy9; /* 0xFC */ + u32 dbrnk0; + u32 dummy10[31]; /* 0x104 .. 0x17C */ + u32 dbpdncnf; + u32 dummy11[47]; /* 0x184 ..0x23C */ + u32 dbdfistat; + u32 dbdficnt; + u32 dummy12[14]; /* 0x248 .. 0x27C */ + u32 dbpdlck; + u32 dummy13[3]; /* 0x284 .. 0x28C */ + u32 dbpdrga; + u32 dummy14[3]; /* 0x294 .. 0x29C */ + u32 dbpdrgd; + u32 dummy15[24]; /* 0x2A4 .. 0x300 */ + u32 dbbs0cnt1; + u32 dummy16[30]; /* 0x308 .. 0x37C */ + u32 dbwt0cnf0; + u32 dbwt0cnf1; + u32 dbwt0cnf2; + u32 dbwt0cnf3; + u32 dbwt0cnf4; +}; + +/* GPIO */ +struct rcar_gpio { + u32 iointsel; + u32 inoutsel; + u32 outdt; + u32 indt; + u32 intdt; + u32 intclr; + u32 intmsk; + u32 posneg; + u32 edglevel; + u32 filonoff; + u32 intmsks; + u32 mskclrs; + u32 outdtsel; + u32 outdth; + u32 outdtl; + u32 bothedge; +}; + +/* S3C(QoS) */ +struct rcar_s3c { + u32 s3cexcladdmsk; + u32 s3cexclidmsk; + u32 s3cadsplcr; + u32 s3cmaar; + u32 s3carcr11; + u32 s3crorr; + u32 s3cworr; + u32 s3carcr22; + u32 dummy1[2]; /* 0x20 .. 0x24 */ + u32 s3cmctr; + u32 dummy2; /* 0x2C */ + u32 cconf0; + u32 cconf1; + u32 cconf2; + u32 cconf3; +}; + +struct rcar_s3c_qos { + u32 s3cqos0; + u32 s3cqos1; + u32 s3cqos2; + u32 s3cqos3; + u32 s3cqos4; + u32 s3cqos5; + u32 s3cqos6; + u32 s3cqos7; + u32 s3cqos8; +}; + +/* DBSC(QoS) */ +struct rcar_dbsc3_qos { + u32 dblgcnt; + u32 dbtmval0; + u32 dbtmval1; + u32 dbtmval2; + u32 dbtmval3; + u32 dbrqctr; + u32 dbthres0; + u32 dbthres1; + u32 dbthres2; + u32 dummy0; /* 0x24 */ + u32 dblgqon; +}; + +/* MXI(QoS) */ +struct rcar_mxi { + u32 mxsaar0; + u32 mxsaar1; + u32 dummy0[7]; /* 0x08 .. 0x20 */ + u32 mxaxiracr; /* R8a7790 only */ + u32 mxs3cracr; + u32 dummy1[2]; /* 0x2C .. 0x30 */ + u32 mxaxiwacr; /* R8a7790 only */ + u32 mxs3cwacr; + u32 dummy2; /* 0x3C */ + u32 mxrtcr; + u32 mxwtcr; +}; + +struct rcar_mxi_qos { + u32 vspdu0; + u32 vspdu1; + u32 du0; + u32 du1; +}; + +/* AXI(QoS) */ +struct rcar_axi_qos { + u32 qosconf; + u32 qosctset0; + u32 qosctset1; + u32 qosctset2; + u32 qosctset3; + u32 qosreqctr; + u32 qosthres0; + u32 qosthres1; + u32 qosthres2; + u32 qosqon; +}; + +#endif + +#endif /* __ASM_ARCH_RCAR_BASE_H */ diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/include/asm/arch-rmobile/rmobile.h index 238256502..ebddd7a8f 100644 --- a/arch/arm/include/asm/arch-rmobile/rmobile.h +++ b/arch/arm/include/asm/arch-rmobile/rmobile.h @@ -15,4 +15,10 @@ #endif #endif /* CONFIG_RMOBILE */ +#ifndef __ASSEMBLY__ +u32 rmobile_get_cpu_type(void); +u32 rmobile_get_cpu_rev_integer(void); +u32 rmobile_get_cpu_rev_fraction(void); +#endif /* __ASSEMBLY__ */ + #endif /* __ASM_ARCH_RMOBILE_H */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h index da8df74a1..d5dbc22c1 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h @@ -19,170 +19,830 @@ struct s5p_gpio_bank { unsigned char res1[8]; }; -struct s5pc100_gpio { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c; - struct s5p_gpio_bank d; - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; - struct s5p_gpio_bank g0; - struct s5p_gpio_bank g1; - struct s5p_gpio_bank g2; - struct s5p_gpio_bank g3; - struct s5p_gpio_bank i; - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; - struct s5p_gpio_bank j2; - struct s5p_gpio_bank j3; - struct s5p_gpio_bank j4; - struct s5p_gpio_bank k0; - struct s5p_gpio_bank k1; - struct s5p_gpio_bank k2; - struct s5p_gpio_bank k3; - struct s5p_gpio_bank l0; - struct s5p_gpio_bank l1; - struct s5p_gpio_bank l2; - struct s5p_gpio_bank l3; - struct s5p_gpio_bank l4; - struct s5p_gpio_bank h0; - struct s5p_gpio_bank h1; - struct s5p_gpio_bank h2; - struct s5p_gpio_bank h3; +/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */ +enum s5pc100_gpio_pin { + S5PC100_GPIO_A00, + S5PC100_GPIO_A01, + S5PC100_GPIO_A02, + S5PC100_GPIO_A03, + S5PC100_GPIO_A04, + S5PC100_GPIO_A05, + S5PC100_GPIO_A06, + S5PC100_GPIO_A07, + S5PC100_GPIO_A10, + S5PC100_GPIO_A11, + S5PC100_GPIO_A12, + S5PC100_GPIO_A13, + S5PC100_GPIO_A14, + S5PC100_GPIO_A15, + S5PC100_GPIO_A16, + S5PC100_GPIO_A17, + S5PC100_GPIO_B0, + S5PC100_GPIO_B1, + S5PC100_GPIO_B2, + S5PC100_GPIO_B3, + S5PC100_GPIO_B4, + S5PC100_GPIO_B5, + S5PC100_GPIO_B6, + S5PC100_GPIO_B7, + S5PC100_GPIO_C0, + S5PC100_GPIO_C1, + S5PC100_GPIO_C2, + S5PC100_GPIO_C3, + S5PC100_GPIO_C4, + S5PC100_GPIO_C5, + S5PC100_GPIO_C6, + S5PC100_GPIO_C7, + S5PC100_GPIO_D0, + S5PC100_GPIO_D1, + S5PC100_GPIO_D2, + S5PC100_GPIO_D3, + S5PC100_GPIO_D4, + S5PC100_GPIO_D5, + S5PC100_GPIO_D6, + S5PC100_GPIO_D7, + S5PC100_GPIO_E00, + S5PC100_GPIO_E01, + S5PC100_GPIO_E02, + S5PC100_GPIO_E03, + S5PC100_GPIO_E04, + S5PC100_GPIO_E05, + S5PC100_GPIO_E06, + S5PC100_GPIO_E07, + S5PC100_GPIO_E10, + S5PC100_GPIO_E11, + S5PC100_GPIO_E12, + S5PC100_GPIO_E13, + S5PC100_GPIO_E14, + S5PC100_GPIO_E15, + S5PC100_GPIO_E16, + S5PC100_GPIO_E17, + S5PC100_GPIO_F00, + S5PC100_GPIO_F01, + S5PC100_GPIO_F02, + S5PC100_GPIO_F03, + S5PC100_GPIO_F04, + S5PC100_GPIO_F05, + S5PC100_GPIO_F06, + S5PC100_GPIO_F07, + S5PC100_GPIO_F10, + S5PC100_GPIO_F11, + S5PC100_GPIO_F12, + S5PC100_GPIO_F13, + S5PC100_GPIO_F14, + S5PC100_GPIO_F15, + S5PC100_GPIO_F16, + S5PC100_GPIO_F17, + S5PC100_GPIO_F20, + S5PC100_GPIO_F21, + S5PC100_GPIO_F22, + S5PC100_GPIO_F23, + S5PC100_GPIO_F24, + S5PC100_GPIO_F25, + S5PC100_GPIO_F26, + S5PC100_GPIO_F27, + S5PC100_GPIO_F30, + S5PC100_GPIO_F31, + S5PC100_GPIO_F32, + S5PC100_GPIO_F33, + S5PC100_GPIO_F34, + S5PC100_GPIO_F35, + S5PC100_GPIO_F36, + S5PC100_GPIO_F37, + S5PC100_GPIO_G00, + S5PC100_GPIO_G01, + S5PC100_GPIO_G02, + S5PC100_GPIO_G03, + S5PC100_GPIO_G04, + S5PC100_GPIO_G05, + S5PC100_GPIO_G06, + S5PC100_GPIO_G07, + S5PC100_GPIO_G10, + S5PC100_GPIO_G11, + S5PC100_GPIO_G12, + S5PC100_GPIO_G13, + S5PC100_GPIO_G14, + S5PC100_GPIO_G15, + S5PC100_GPIO_G16, + S5PC100_GPIO_G17, + S5PC100_GPIO_G20, + S5PC100_GPIO_G21, + S5PC100_GPIO_G22, + S5PC100_GPIO_G23, + S5PC100_GPIO_G24, + S5PC100_GPIO_G25, + S5PC100_GPIO_G26, + S5PC100_GPIO_G27, + S5PC100_GPIO_G30, + S5PC100_GPIO_G31, + S5PC100_GPIO_G32, + S5PC100_GPIO_G33, + S5PC100_GPIO_G34, + S5PC100_GPIO_G35, + S5PC100_GPIO_G36, + S5PC100_GPIO_G37, + S5PC100_GPIO_I0, + S5PC100_GPIO_I1, + S5PC100_GPIO_I2, + S5PC100_GPIO_I3, + S5PC100_GPIO_I4, + S5PC100_GPIO_I5, + S5PC100_GPIO_I6, + S5PC100_GPIO_I7, + S5PC100_GPIO_J00, + S5PC100_GPIO_J01, + S5PC100_GPIO_J02, + S5PC100_GPIO_J03, + S5PC100_GPIO_J04, + S5PC100_GPIO_J05, + S5PC100_GPIO_J06, + S5PC100_GPIO_J07, + S5PC100_GPIO_J10, + S5PC100_GPIO_J11, + S5PC100_GPIO_J12, + S5PC100_GPIO_J13, + S5PC100_GPIO_J14, + S5PC100_GPIO_J15, + S5PC100_GPIO_J16, + S5PC100_GPIO_J17, + S5PC100_GPIO_J20, + S5PC100_GPIO_J21, + S5PC100_GPIO_J22, + S5PC100_GPIO_J23, + S5PC100_GPIO_J24, + S5PC100_GPIO_J25, + S5PC100_GPIO_J26, + S5PC100_GPIO_J27, + S5PC100_GPIO_J30, + S5PC100_GPIO_J31, + S5PC100_GPIO_J32, + S5PC100_GPIO_J33, + S5PC100_GPIO_J34, + S5PC100_GPIO_J35, + S5PC100_GPIO_J36, + S5PC100_GPIO_J37, + S5PC100_GPIO_J40, + S5PC100_GPIO_J41, + S5PC100_GPIO_J42, + S5PC100_GPIO_J43, + S5PC100_GPIO_J44, + S5PC100_GPIO_J45, + S5PC100_GPIO_J46, + S5PC100_GPIO_J47, + S5PC100_GPIO_K00, + S5PC100_GPIO_K01, + S5PC100_GPIO_K02, + S5PC100_GPIO_K03, + S5PC100_GPIO_K04, + S5PC100_GPIO_K05, + S5PC100_GPIO_K06, + S5PC100_GPIO_K07, + S5PC100_GPIO_K10, + S5PC100_GPIO_K11, + S5PC100_GPIO_K12, + S5PC100_GPIO_K13, + S5PC100_GPIO_K14, + S5PC100_GPIO_K15, + S5PC100_GPIO_K16, + S5PC100_GPIO_K17, + S5PC100_GPIO_K20, + S5PC100_GPIO_K21, + S5PC100_GPIO_K22, + S5PC100_GPIO_K23, + S5PC100_GPIO_K24, + S5PC100_GPIO_K25, + S5PC100_GPIO_K26, + S5PC100_GPIO_K27, + S5PC100_GPIO_K30, + S5PC100_GPIO_K31, + S5PC100_GPIO_K32, + S5PC100_GPIO_K33, + S5PC100_GPIO_K34, + S5PC100_GPIO_K35, + S5PC100_GPIO_K36, + S5PC100_GPIO_K37, + S5PC100_GPIO_L00, + S5PC100_GPIO_L01, + S5PC100_GPIO_L02, + S5PC100_GPIO_L03, + S5PC100_GPIO_L04, + S5PC100_GPIO_L05, + S5PC100_GPIO_L06, + S5PC100_GPIO_L07, + S5PC100_GPIO_L10, + S5PC100_GPIO_L11, + S5PC100_GPIO_L12, + S5PC100_GPIO_L13, + S5PC100_GPIO_L14, + S5PC100_GPIO_L15, + S5PC100_GPIO_L16, + S5PC100_GPIO_L17, + S5PC100_GPIO_L20, + S5PC100_GPIO_L21, + S5PC100_GPIO_L22, + S5PC100_GPIO_L23, + S5PC100_GPIO_L24, + S5PC100_GPIO_L25, + S5PC100_GPIO_L26, + S5PC100_GPIO_L27, + S5PC100_GPIO_L30, + S5PC100_GPIO_L31, + S5PC100_GPIO_L32, + S5PC100_GPIO_L33, + S5PC100_GPIO_L34, + S5PC100_GPIO_L35, + S5PC100_GPIO_L36, + S5PC100_GPIO_L37, + S5PC100_GPIO_L40, + S5PC100_GPIO_L41, + S5PC100_GPIO_L42, + S5PC100_GPIO_L43, + S5PC100_GPIO_L44, + S5PC100_GPIO_L45, + S5PC100_GPIO_L46, + S5PC100_GPIO_L47, + S5PC100_GPIO_H00, + S5PC100_GPIO_H01, + S5PC100_GPIO_H02, + S5PC100_GPIO_H03, + S5PC100_GPIO_H04, + S5PC100_GPIO_H05, + S5PC100_GPIO_H06, + S5PC100_GPIO_H07, + S5PC100_GPIO_H10, + S5PC100_GPIO_H11, + S5PC100_GPIO_H12, + S5PC100_GPIO_H13, + S5PC100_GPIO_H14, + S5PC100_GPIO_H15, + S5PC100_GPIO_H16, + S5PC100_GPIO_H17, + S5PC100_GPIO_H20, + S5PC100_GPIO_H21, + S5PC100_GPIO_H22, + S5PC100_GPIO_H23, + S5PC100_GPIO_H24, + S5PC100_GPIO_H25, + S5PC100_GPIO_H26, + S5PC100_GPIO_H27, + S5PC100_GPIO_H30, + S5PC100_GPIO_H31, + S5PC100_GPIO_H32, + S5PC100_GPIO_H33, + S5PC100_GPIO_H34, + S5PC100_GPIO_H35, + S5PC100_GPIO_H36, + S5PC100_GPIO_H37, + + S5PC100_GPIO_MAX_PORT }; -struct s5pc110_gpio { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; - struct s5p_gpio_bank g0; - struct s5p_gpio_bank g1; - struct s5p_gpio_bank g2; - struct s5p_gpio_bank g3; - struct s5p_gpio_bank i; - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; - struct s5p_gpio_bank j2; - struct s5p_gpio_bank j3; - struct s5p_gpio_bank j4; - struct s5p_gpio_bank mp0_1; - struct s5p_gpio_bank mp0_2; - struct s5p_gpio_bank mp0_3; - struct s5p_gpio_bank mp0_4; - struct s5p_gpio_bank mp0_5; - struct s5p_gpio_bank mp0_6; - struct s5p_gpio_bank mp0_7; - struct s5p_gpio_bank mp1_0; - struct s5p_gpio_bank mp1_1; - struct s5p_gpio_bank mp1_2; - struct s5p_gpio_bank mp1_3; - struct s5p_gpio_bank mp1_4; - struct s5p_gpio_bank mp1_5; - struct s5p_gpio_bank mp1_6; - struct s5p_gpio_bank mp1_7; - struct s5p_gpio_bank mp1_8; - struct s5p_gpio_bank mp2_0; - struct s5p_gpio_bank mp2_1; - struct s5p_gpio_bank mp2_2; - struct s5p_gpio_bank mp2_3; - struct s5p_gpio_bank mp2_4; - struct s5p_gpio_bank mp2_5; - struct s5p_gpio_bank mp2_6; - struct s5p_gpio_bank mp2_7; - struct s5p_gpio_bank mp2_8; - struct s5p_gpio_bank res1[48]; - struct s5p_gpio_bank h0; - struct s5p_gpio_bank h1; - struct s5p_gpio_bank h2; - struct s5p_gpio_bank h3; +enum s5pc110_gpio_pin { + S5PC110_GPIO_A00, + S5PC110_GPIO_A01, + S5PC110_GPIO_A02, + S5PC110_GPIO_A03, + S5PC110_GPIO_A04, + S5PC110_GPIO_A05, + S5PC110_GPIO_A06, + S5PC110_GPIO_A07, + S5PC110_GPIO_A10, + S5PC110_GPIO_A11, + S5PC110_GPIO_A12, + S5PC110_GPIO_A13, + S5PC110_GPIO_A14, + S5PC110_GPIO_A15, + S5PC110_GPIO_A16, + S5PC110_GPIO_A17, + S5PC110_GPIO_B0, + S5PC110_GPIO_B1, + S5PC110_GPIO_B2, + S5PC110_GPIO_B3, + S5PC110_GPIO_B4, + S5PC110_GPIO_B5, + S5PC110_GPIO_B6, + S5PC110_GPIO_B7, + S5PC110_GPIO_C00, + S5PC110_GPIO_C01, + S5PC110_GPIO_C02, + S5PC110_GPIO_C03, + S5PC110_GPIO_C04, + S5PC110_GPIO_C05, + S5PC110_GPIO_C06, + S5PC110_GPIO_C07, + S5PC110_GPIO_C10, + S5PC110_GPIO_C11, + S5PC110_GPIO_C12, + S5PC110_GPIO_C13, + S5PC110_GPIO_C14, + S5PC110_GPIO_C15, + S5PC110_GPIO_C16, + S5PC110_GPIO_C17, + S5PC110_GPIO_D00, + S5PC110_GPIO_D01, + S5PC110_GPIO_D02, + S5PC110_GPIO_D03, + S5PC110_GPIO_D04, + S5PC110_GPIO_D05, + S5PC110_GPIO_D06, + S5PC110_GPIO_D07, + S5PC110_GPIO_D10, + S5PC110_GPIO_D11, + S5PC110_GPIO_D12, + S5PC110_GPIO_D13, + S5PC110_GPIO_D14, + S5PC110_GPIO_D15, + S5PC110_GPIO_D16, + S5PC110_GPIO_D17, + S5PC110_GPIO_E00, + S5PC110_GPIO_E01, + S5PC110_GPIO_E02, + S5PC110_GPIO_E03, + S5PC110_GPIO_E04, + S5PC110_GPIO_E05, + S5PC110_GPIO_E06, + S5PC110_GPIO_E07, + S5PC110_GPIO_E10, + S5PC110_GPIO_E11, + S5PC110_GPIO_E12, + S5PC110_GPIO_E13, + S5PC110_GPIO_E14, + S5PC110_GPIO_E15, + S5PC110_GPIO_E16, + S5PC110_GPIO_E17, + S5PC110_GPIO_F00, + S5PC110_GPIO_F01, + S5PC110_GPIO_F02, + S5PC110_GPIO_F03, + S5PC110_GPIO_F04, + S5PC110_GPIO_F05, + S5PC110_GPIO_F06, + S5PC110_GPIO_F07, + S5PC110_GPIO_F10, + S5PC110_GPIO_F11, + S5PC110_GPIO_F12, + S5PC110_GPIO_F13, + S5PC110_GPIO_F14, + S5PC110_GPIO_F15, + S5PC110_GPIO_F16, + S5PC110_GPIO_F17, + S5PC110_GPIO_F20, + S5PC110_GPIO_F21, + S5PC110_GPIO_F22, + S5PC110_GPIO_F23, + S5PC110_GPIO_F24, + S5PC110_GPIO_F25, + S5PC110_GPIO_F26, + S5PC110_GPIO_F27, + S5PC110_GPIO_F30, + S5PC110_GPIO_F31, + S5PC110_GPIO_F32, + S5PC110_GPIO_F33, + S5PC110_GPIO_F34, + S5PC110_GPIO_F35, + S5PC110_GPIO_F36, + S5PC110_GPIO_F37, + S5PC110_GPIO_G00, + S5PC110_GPIO_G01, + S5PC110_GPIO_G02, + S5PC110_GPIO_G03, + S5PC110_GPIO_G04, + S5PC110_GPIO_G05, + S5PC110_GPIO_G06, + S5PC110_GPIO_G07, + S5PC110_GPIO_G10, + S5PC110_GPIO_G11, + S5PC110_GPIO_G12, + S5PC110_GPIO_G13, + S5PC110_GPIO_G14, + S5PC110_GPIO_G15, + S5PC110_GPIO_G16, + S5PC110_GPIO_G17, + S5PC110_GPIO_G20, + S5PC110_GPIO_G21, + S5PC110_GPIO_G22, + S5PC110_GPIO_G23, + S5PC110_GPIO_G24, + S5PC110_GPIO_G25, + S5PC110_GPIO_G26, + S5PC110_GPIO_G27, + S5PC110_GPIO_G30, + S5PC110_GPIO_G31, + S5PC110_GPIO_G32, + S5PC110_GPIO_G33, + S5PC110_GPIO_G34, + S5PC110_GPIO_G35, + S5PC110_GPIO_G36, + S5PC110_GPIO_G37, + S5PC110_GPIO_I0, + S5PC110_GPIO_I1, + S5PC110_GPIO_I2, + S5PC110_GPIO_I3, + S5PC110_GPIO_I4, + S5PC110_GPIO_I5, + S5PC110_GPIO_I6, + S5PC110_GPIO_I7, + S5PC110_GPIO_J00, + S5PC110_GPIO_J01, + S5PC110_GPIO_J02, + S5PC110_GPIO_J03, + S5PC110_GPIO_J04, + S5PC110_GPIO_J05, + S5PC110_GPIO_J06, + S5PC110_GPIO_J07, + S5PC110_GPIO_J10, + S5PC110_GPIO_J11, + S5PC110_GPIO_J12, + S5PC110_GPIO_J13, + S5PC110_GPIO_J14, + S5PC110_GPIO_J15, + S5PC110_GPIO_J16, + S5PC110_GPIO_J17, + S5PC110_GPIO_J20, + S5PC110_GPIO_J21, + S5PC110_GPIO_J22, + S5PC110_GPIO_J23, + S5PC110_GPIO_J24, + S5PC110_GPIO_J25, + S5PC110_GPIO_J26, + S5PC110_GPIO_J27, + S5PC110_GPIO_J30, + S5PC110_GPIO_J31, + S5PC110_GPIO_J32, + S5PC110_GPIO_J33, + S5PC110_GPIO_J34, + S5PC110_GPIO_J35, + S5PC110_GPIO_J36, + S5PC110_GPIO_J37, + S5PC110_GPIO_J40, + S5PC110_GPIO_J41, + S5PC110_GPIO_J42, + S5PC110_GPIO_J43, + S5PC110_GPIO_J44, + S5PC110_GPIO_J45, + S5PC110_GPIO_J46, + S5PC110_GPIO_J47, + S5PC110_GPIO_MP010, + S5PC110_GPIO_MP011, + S5PC110_GPIO_MP012, + S5PC110_GPIO_MP013, + S5PC110_GPIO_MP014, + S5PC110_GPIO_MP015, + S5PC110_GPIO_MP016, + S5PC110_GPIO_MP017, + S5PC110_GPIO_MP020, + S5PC110_GPIO_MP021, + S5PC110_GPIO_MP022, + S5PC110_GPIO_MP023, + S5PC110_GPIO_MP024, + S5PC110_GPIO_MP025, + S5PC110_GPIO_MP026, + S5PC110_GPIO_MP027, + S5PC110_GPIO_MP030, + S5PC110_GPIO_MP031, + S5PC110_GPIO_MP032, + S5PC110_GPIO_MP033, + S5PC110_GPIO_MP034, + S5PC110_GPIO_MP035, + S5PC110_GPIO_MP036, + S5PC110_GPIO_MP037, + S5PC110_GPIO_MP040, + S5PC110_GPIO_MP041, + S5PC110_GPIO_MP042, + S5PC110_GPIO_MP043, + S5PC110_GPIO_MP044, + S5PC110_GPIO_MP045, + S5PC110_GPIO_MP046, + S5PC110_GPIO_MP047, + S5PC110_GPIO_MP050, + S5PC110_GPIO_MP051, + S5PC110_GPIO_MP052, + S5PC110_GPIO_MP053, + S5PC110_GPIO_MP054, + S5PC110_GPIO_MP055, + S5PC110_GPIO_MP056, + S5PC110_GPIO_MP057, + S5PC110_GPIO_MP060, + S5PC110_GPIO_MP061, + S5PC110_GPIO_MP062, + S5PC110_GPIO_MP063, + S5PC110_GPIO_MP064, + S5PC110_GPIO_MP065, + S5PC110_GPIO_MP066, + S5PC110_GPIO_MP067, + S5PC110_GPIO_MP070, + S5PC110_GPIO_MP071, + S5PC110_GPIO_MP072, + S5PC110_GPIO_MP073, + S5PC110_GPIO_MP074, + S5PC110_GPIO_MP075, + S5PC110_GPIO_MP076, + S5PC110_GPIO_MP077, + S5PC110_GPIO_MP100, + S5PC110_GPIO_MP101, + S5PC110_GPIO_MP102, + S5PC110_GPIO_MP103, + S5PC110_GPIO_MP104, + S5PC110_GPIO_MP105, + S5PC110_GPIO_MP106, + S5PC110_GPIO_MP107, + S5PC110_GPIO_MP110, + S5PC110_GPIO_MP111, + S5PC110_GPIO_MP112, + S5PC110_GPIO_MP113, + S5PC110_GPIO_MP114, + S5PC110_GPIO_MP115, + S5PC110_GPIO_MP116, + S5PC110_GPIO_MP117, + S5PC110_GPIO_MP120, + S5PC110_GPIO_MP121, + S5PC110_GPIO_MP122, + S5PC110_GPIO_MP123, + S5PC110_GPIO_MP124, + S5PC110_GPIO_MP125, + S5PC110_GPIO_MP126, + S5PC110_GPIO_MP127, + S5PC110_GPIO_MP130, + S5PC110_GPIO_MP131, + S5PC110_GPIO_MP132, + S5PC110_GPIO_MP133, + S5PC110_GPIO_MP134, + S5PC110_GPIO_MP135, + S5PC110_GPIO_MP136, + S5PC110_GPIO_MP137, + S5PC110_GPIO_MP140, + S5PC110_GPIO_MP141, + S5PC110_GPIO_MP142, + S5PC110_GPIO_MP143, + S5PC110_GPIO_MP144, + S5PC110_GPIO_MP145, + S5PC110_GPIO_MP146, + S5PC110_GPIO_MP147, + S5PC110_GPIO_MP150, + S5PC110_GPIO_MP151, + S5PC110_GPIO_MP152, + S5PC110_GPIO_MP153, + S5PC110_GPIO_MP154, + S5PC110_GPIO_MP155, + S5PC110_GPIO_MP156, + S5PC110_GPIO_MP157, + S5PC110_GPIO_MP160, + S5PC110_GPIO_MP161, + S5PC110_GPIO_MP162, + S5PC110_GPIO_MP163, + S5PC110_GPIO_MP164, + S5PC110_GPIO_MP165, + S5PC110_GPIO_MP166, + S5PC110_GPIO_MP167, + S5PC110_GPIO_MP170, + S5PC110_GPIO_MP171, + S5PC110_GPIO_MP172, + S5PC110_GPIO_MP173, + S5PC110_GPIO_MP174, + S5PC110_GPIO_MP175, + S5PC110_GPIO_MP176, + S5PC110_GPIO_MP177, + S5PC110_GPIO_MP180, + S5PC110_GPIO_MP181, + S5PC110_GPIO_MP182, + S5PC110_GPIO_MP183, + S5PC110_GPIO_MP184, + S5PC110_GPIO_MP185, + S5PC110_GPIO_MP186, + S5PC110_GPIO_MP187, + S5PC110_GPIO_MP200, + S5PC110_GPIO_MP201, + S5PC110_GPIO_MP202, + S5PC110_GPIO_MP203, + S5PC110_GPIO_MP204, + S5PC110_GPIO_MP205, + S5PC110_GPIO_MP206, + S5PC110_GPIO_MP207, + S5PC110_GPIO_MP210, + S5PC110_GPIO_MP211, + S5PC110_GPIO_MP212, + S5PC110_GPIO_MP213, + S5PC110_GPIO_MP214, + S5PC110_GPIO_MP215, + S5PC110_GPIO_MP216, + S5PC110_GPIO_MP217, + S5PC110_GPIO_MP220, + S5PC110_GPIO_MP221, + S5PC110_GPIO_MP222, + S5PC110_GPIO_MP223, + S5PC110_GPIO_MP224, + S5PC110_GPIO_MP225, + S5PC110_GPIO_MP226, + S5PC110_GPIO_MP227, + S5PC110_GPIO_MP230, + S5PC110_GPIO_MP231, + S5PC110_GPIO_MP232, + S5PC110_GPIO_MP233, + S5PC110_GPIO_MP234, + S5PC110_GPIO_MP235, + S5PC110_GPIO_MP236, + S5PC110_GPIO_MP237, + S5PC110_GPIO_MP240, + S5PC110_GPIO_MP241, + S5PC110_GPIO_MP242, + S5PC110_GPIO_MP243, + S5PC110_GPIO_MP244, + S5PC110_GPIO_MP245, + S5PC110_GPIO_MP246, + S5PC110_GPIO_MP247, + S5PC110_GPIO_MP250, + S5PC110_GPIO_MP251, + S5PC110_GPIO_MP252, + S5PC110_GPIO_MP253, + S5PC110_GPIO_MP254, + S5PC110_GPIO_MP255, + S5PC110_GPIO_MP256, + S5PC110_GPIO_MP257, + S5PC110_GPIO_MP260, + S5PC110_GPIO_MP261, + S5PC110_GPIO_MP262, + S5PC110_GPIO_MP263, + S5PC110_GPIO_MP264, + S5PC110_GPIO_MP265, + S5PC110_GPIO_MP266, + S5PC110_GPIO_MP267, + S5PC110_GPIO_MP270, + S5PC110_GPIO_MP271, + S5PC110_GPIO_MP272, + S5PC110_GPIO_MP273, + S5PC110_GPIO_MP274, + S5PC110_GPIO_MP275, + S5PC110_GPIO_MP276, + S5PC110_GPIO_MP277, + S5PC110_GPIO_MP280, + S5PC110_GPIO_MP281, + S5PC110_GPIO_MP282, + S5PC110_GPIO_MP283, + S5PC110_GPIO_MP284, + S5PC110_GPIO_MP285, + S5PC110_GPIO_MP286, + S5PC110_GPIO_MP287, + S5PC110_GPIO_RES, + S5PC110_GPIO_H00 = (S5PC110_GPIO_RES + (48 * 8)), + S5PC110_GPIO_H01, + S5PC110_GPIO_H02, + S5PC110_GPIO_H03, + S5PC110_GPIO_H04, + S5PC110_GPIO_H05, + S5PC110_GPIO_H06, + S5PC110_GPIO_H07, + S5PC110_GPIO_H10, + S5PC110_GPIO_H11, + S5PC110_GPIO_H12, + S5PC110_GPIO_H13, + S5PC110_GPIO_H14, + S5PC110_GPIO_H15, + S5PC110_GPIO_H16, + S5PC110_GPIO_H17, + S5PC110_GPIO_H20, + S5PC110_GPIO_H21, + S5PC110_GPIO_H22, + S5PC110_GPIO_H23, + S5PC110_GPIO_H24, + S5PC110_GPIO_H25, + S5PC110_GPIO_H26, + S5PC110_GPIO_H27, + S5PC110_GPIO_H30, + S5PC110_GPIO_H31, + S5PC110_GPIO_H32, + S5PC110_GPIO_H33, + S5PC110_GPIO_H34, + S5PC110_GPIO_H35, + S5PC110_GPIO_H36, + S5PC110_GPIO_H37, + + S5PC110_GPIO_MAX_PORT }; -/* functions */ -void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg); -void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en); -void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en); -unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); +struct gpio_info { + unsigned int reg_addr; /* Address of register for this part */ + unsigned int max_gpio; /* Maximum GPIO in this part */ +}; -/* GPIO pins per bank */ -#define GPIO_PER_BANK 8 +#define S5PC100_GPIO_NUM_PARTS 1 +static struct gpio_info s5pc100_gpio_data[S5PC100_GPIO_NUM_PARTS] = { + { S5PC100_GPIO_BASE, S5PC100_GPIO_MAX_PORT }, +}; -#define S5P_GPIO_PART_SHIFT (24) -#define S5P_GPIO_PART_MASK (0xff) -#define S5P_GPIO_BANK_SHIFT (8) -#define S5P_GPIO_BANK_MASK (0xffff) -#define S5P_GPIO_PIN_MASK (0xff) +#define S5PC110_GPIO_NUM_PARTS 1 +static struct gpio_info s5pc110_gpio_data[S5PC110_GPIO_NUM_PARTS] = { + { S5PC110_GPIO_BASE, S5PC110_GPIO_MAX_PORT }, +}; -#define S5P_GPIO_SET_PART(x) \ - (((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT) +static inline struct gpio_info *get_gpio_data(void) +{ + if (cpu_is_s5pc100()) + return s5pc100_gpio_data; + else if (cpu_is_s5pc110()) + return s5pc110_gpio_data; -#define S5P_GPIO_GET_PART(x) \ - (((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK) + return NULL; +} -#define S5P_GPIO_SET_PIN(x) \ - ((x) & S5P_GPIO_PIN_MASK) +static inline unsigned int get_bank_num(void) +{ + if (cpu_is_s5pc100()) + return S5PC100_GPIO_NUM_PARTS; + else if (cpu_is_s5pc110()) + return S5PC110_GPIO_NUM_PARTS; -#define S5PC100_SET_BANK(bank) \ - (((unsigned)&(((struct s5pc100_gpio *) \ - S5PC100_GPIO_BASE)->bank) - S5PC100_GPIO_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) + return 0; +} -#define S5PC110_SET_BANK(bank) \ - ((((unsigned)&(((struct s5pc110_gpio *) \ - S5PC110_GPIO_BASE)->bank) - S5PC110_GPIO_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) +/* + * This structure helps mapping symbolic GPIO names into indices from + * exynos5_gpio_pin/exynos5420_gpio_pin enums. + * + * By convention, symbolic GPIO name is defined as follows: + * + * g[p]<bank><set><bit>, where + * p is optional + * <bank> - a single character bank name, as defined by the SOC + * <set> - a single digit set number + * <bit> - bit number within the set (in 0..7 range). + * + * <set><bit> essentially form an octal number of the GPIO pin within the bank + * space. On the 5420 architecture some banks' sets do not start not from zero + * ('d' starts from 1 and 'j' starts from 4). To compensate for that and + * maintain flat number space withoout holes, those banks use offsets to be + * deducted from the pin number. + */ +struct gpio_name_num_table { + char bank; /* bank name symbol */ + u8 bank_size; /* total number of pins in the bank */ + char bank_offset; /* offset of the first bank's pin */ + unsigned int base; /* index of the first bank's pin in the enum */ +}; -#define s5pc100_gpio_get(bank, pin) \ - (S5P_GPIO_SET_PART(0) | \ - S5PC100_SET_BANK(bank) | \ - S5P_GPIO_SET_PIN(pin)) +#define GPIO_PER_BANK 8 +#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base } +static const struct gpio_name_num_table s5pc100_gpio_table[] = { + GPIO_ENTRY('a', S5PC100_GPIO_A00, S5PC100_GPIO_B0, 0), + GPIO_ENTRY('b', S5PC100_GPIO_B0, S5PC100_GPIO_C0, 0), + GPIO_ENTRY('c', S5PC100_GPIO_C0, S5PC100_GPIO_D0, 0), + GPIO_ENTRY('d', S5PC100_GPIO_D0, S5PC100_GPIO_E00, 0), + GPIO_ENTRY('e', S5PC100_GPIO_E00, S5PC100_GPIO_F00, 0), + GPIO_ENTRY('f', S5PC100_GPIO_F00, S5PC100_GPIO_G00, 0), + GPIO_ENTRY('g', S5PC100_GPIO_G00, S5PC100_GPIO_I0, 0), + GPIO_ENTRY('i', S5PC100_GPIO_I0, S5PC100_GPIO_J00, 0), + GPIO_ENTRY('j', S5PC100_GPIO_J00, S5PC100_GPIO_K00, 0), + GPIO_ENTRY('k', S5PC100_GPIO_K00, S5PC100_GPIO_L00, 0), + GPIO_ENTRY('l', S5PC100_GPIO_L00, S5PC100_GPIO_H00, 0), + GPIO_ENTRY('h', S5PC100_GPIO_H00, S5PC100_GPIO_MAX_PORT, 0), + { 0 } +}; -#define s5pc110_gpio_get(bank, pin) \ - (S5P_GPIO_SET_PART(0) | \ - S5PC110_SET_BANK(bank) | \ - S5P_GPIO_SET_PIN(pin)) +static const struct gpio_name_num_table s5pc110_gpio_table[] = { + GPIO_ENTRY('a', S5PC110_GPIO_A00, S5PC110_GPIO_B0, 0), + GPIO_ENTRY('b', S5PC110_GPIO_B0, S5PC110_GPIO_C00, 0), + GPIO_ENTRY('c', S5PC110_GPIO_C00, S5PC110_GPIO_D00, 0), + GPIO_ENTRY('d', S5PC110_GPIO_D00, S5PC110_GPIO_E00, 0), + GPIO_ENTRY('e', S5PC110_GPIO_E00, S5PC110_GPIO_F00, 0), + GPIO_ENTRY('f', S5PC110_GPIO_F00, S5PC110_GPIO_G00, 0), + GPIO_ENTRY('g', S5PC110_GPIO_G00, S5PC110_GPIO_I0, 0), + GPIO_ENTRY('i', S5PC110_GPIO_I0, S5PC110_GPIO_J00, 0), + GPIO_ENTRY('j', S5PC110_GPIO_J00, S5PC110_GPIO_MP010, 0), + GPIO_ENTRY('h', S5PC110_GPIO_H00, S5PC110_GPIO_MAX_PORT, 0), + { 0 } +}; -static inline unsigned int s5p_gpio_base(int nr) -{ - return samsung_get_base_gpio(); -} +/* functions */ +void gpio_cfg_pin(int gpio, int cfg); +void gpio_set_pull(int gpio, int mode); +void gpio_set_drv(int gpio, int mode); +int gpio_direction_output(unsigned gpio, int value); +int gpio_set_value(unsigned gpio, int value); +int gpio_get_value(unsigned gpio); +void gpio_set_rate(int gpio, int mode); +struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio); +int s5p_gpio_get_pin(unsigned gpio); + +/* GPIO pins per bank */ +#define GPIO_PER_BANK 8 #endif /* Pin configurations */ -#define GPIO_INPUT 0x0 -#define GPIO_OUTPUT 0x1 -#define GPIO_IRQ 0xf -#define GPIO_FUNC(x) (x) +#define S5P_GPIO_INPUT 0x0 +#define S5P_GPIO_OUTPUT 0x1 +#define S5P_GPIO_IRQ 0xf +#define S5P_GPIO_FUNC(x) (x) /* Pull mode */ -#define GPIO_PULL_NONE 0x0 -#define GPIO_PULL_DOWN 0x1 -#define GPIO_PULL_UP 0x2 +#define S5P_GPIO_PULL_NONE 0x0 +#define S5P_GPIO_PULL_DOWN 0x1 +#define S5P_GPIO_PULL_UP 0x2 /* Drive Strength level */ -#define GPIO_DRV_1X 0x0 -#define GPIO_DRV_3X 0x1 -#define GPIO_DRV_2X 0x2 -#define GPIO_DRV_4X 0x3 -#define GPIO_DRV_FAST 0x0 -#define GPIO_DRV_SLOW 0x1 +#define S5P_GPIO_DRV_1X 0x0 +#define S5P_GPIO_DRV_3X 0x1 +#define S5P_GPIO_DRV_2X 0x2 +#define S5P_GPIO_DRV_4X 0x3 +#define S5P_GPIO_DRV_FAST 0x0 +#define S5P_GPIO_DRV_SLOW 0x1 #endif diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h new file mode 100644 index 000000000..5669f392f --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CLOCK_H +#define _SUNXI_CLOCK_H + +#include <linux/types.h> + +#define CLK_GATE_OPEN 0x1 +#define CLK_GATE_CLOSE 0x0 + +/* clock control module regs definition */ +#include <asm/arch/clock_sun4i.h> + +#ifndef __ASSEMBLY__ +int clock_init(void); +int clock_twi_onoff(int port, int state); +void clock_set_pll1(unsigned int hz); +unsigned int clock_get_pll6(void); +void clock_init_safe(void); +void clock_init_uart(void); +#endif + +#endif /* _SUNXI_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h new file mode 100644 index 000000000..928f3f267 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -0,0 +1,256 @@ +/* + * sun4i, sun5i and sun7i clock register definitions + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CLOCK_SUN4I_H +#define _SUNXI_CLOCK_SUN4I_H + +struct sunxi_ccm_reg { + u32 pll1_cfg; /* 0x00 pll1 control */ + u32 pll1_tun; /* 0x04 pll1 tuning */ + u32 pll2_cfg; /* 0x08 pll2 control */ + u32 pll2_tun; /* 0x0c pll2 tuning */ + u32 pll3_cfg; /* 0x10 pll3 control */ + u8 res0[0x4]; + u32 pll4_cfg; /* 0x18 pll4 control */ + u8 res1[0x4]; + u32 pll5_cfg; /* 0x20 pll5 control */ + u32 pll5_tun; /* 0x24 pll5 tuning */ + u32 pll6_cfg; /* 0x28 pll6 control */ + u32 pll6_tun; /* 0x2c pll6 tuning */ + u32 pll7_cfg; /* 0x30 pll7 control */ + u32 pll1_tun2; /* 0x34 pll5 tuning2 */ + u8 res2[0x4]; + u32 pll5_tun2; /* 0x3c pll5 tuning2 */ + u8 res3[0xc]; + u32 pll_lock_dbg; /* 0x4c pll lock time debug */ + u32 osc24m_cfg; /* 0x50 osc24m control */ + u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */ + u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */ + u32 axi_gate; /* 0x5c axi module clock gating */ + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ + u32 apb0_gate; /* 0x68 apb0 module clock gating */ + u32 apb1_gate; /* 0x6c apb1 module clock gating */ + u8 res4[0x10]; + u32 nand_sclk_cfg; /* 0x80 nand sub clock control */ + u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */ + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ + u32 ts_clk_cfg; /* 0x98 transport stream clock control */ + u32 ss_clk_cfg; /* 0x9c */ + u32 spi0_clk_cfg; /* 0xa0 */ + u32 spi1_clk_cfg; /* 0xa4 */ + u32 spi2_clk_cfg; /* 0xa8 */ + u32 pata_clk_cfg; /* 0xac */ + u32 ir0_clk_cfg; /* 0xb0 */ + u32 ir1_clk_cfg; /* 0xb4 */ + u32 iis_clk_cfg; /* 0xb8 */ + u32 ac97_clk_cfg; /* 0xbc */ + u32 spdif_clk_cfg; /* 0xc0 */ + u32 keypad_clk_cfg; /* 0xc4 */ + u32 sata_clk_cfg; /* 0xc8 */ + u32 usb_clk_cfg; /* 0xcc */ + u32 gps_clk_cfg; /* 0xd0 */ + u32 spi3_clk_cfg; /* 0xd4 */ + u8 res5[0x28]; + u32 dram_clk_cfg; /* 0x100 */ + u32 be0_clk_cfg; /* 0x104 */ + u32 be1_clk_cfg; /* 0x108 */ + u32 fe0_clk_cfg; /* 0x10c */ + u32 fe1_clk_cfg; /* 0x110 */ + u32 mp_clk_cfg; /* 0x114 */ + u32 lcd0_ch0_clk_cfg; /* 0x118 */ + u32 lcd1_ch0_clk_cfg; /* 0x11c */ + u32 csi_isp_clk_cfg; /* 0x120 */ + u8 res6[0x4]; + u32 tvd_clk_reg; /* 0x128 */ + u32 lcd0_ch1_clk_cfg; /* 0x12c */ + u32 lcd1_ch1_clk_cfg; /* 0x130 */ + u32 csi0_clk_cfg; /* 0x134 */ + u32 csi1_clk_cfg; /* 0x138 */ + u32 ve_clk_cfg; /* 0x13c */ + u32 audio_codec_clk_cfg; /* 0x140 */ + u32 avs_clk_cfg; /* 0x144 */ + u32 ace_clk_cfg; /* 0x148 */ + u32 lvds_clk_cfg; /* 0x14c */ + u32 hdmi_clk_cfg; /* 0x150 */ + u32 mali_clk_cfg; /* 0x154 */ + u8 res7[0x4]; + u32 mbus_clk_cfg; /* 0x15c */ + u8 res8[0x4]; + u32 gmac_clk_cfg; /* 0x164 */ +}; + +/* apb1 bit field */ +#define APB1_CLK_SRC_OSC24M (0x0 << 24) +#define APB1_CLK_SRC_PLL6 (0x1 << 24) +#define APB1_CLK_SRC_LOSC (0x2 << 24) +#define APB1_CLK_SRC_MASK (0x3 << 24) +#define APB1_CLK_RATE_N_1 (0x0 << 16) +#define APB1_CLK_RATE_N_2 (0x1 << 16) +#define APB1_CLK_RATE_N_4 (0x2 << 16) +#define APB1_CLK_RATE_N_8 (0x3 << 16) +#define APB1_CLK_RATE_N_MASK (3 << 16) +#define APB1_CLK_RATE_M(m) (((m)-1) << 0) +#define APB1_CLK_RATE_M_MASK (0x1f << 0) + +/* apb1 gate field */ +#define APB1_GATE_UART_SHIFT (16) +#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT) +#define APB1_GATE_TWI_SHIFT (0) +#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT) + +/* clock divide */ +#define AXI_DIV_SHIFT (0) +#define AXI_DIV_1 0 +#define AXI_DIV_2 1 +#define AXI_DIV_3 2 +#define AXI_DIV_4 3 +#define AHB_DIV_SHIFT (4) +#define AHB_DIV_1 0 +#define AHB_DIV_2 1 +#define AHB_DIV_4 2 +#define AHB_DIV_8 3 +#define APB0_DIV_SHIFT (8) +#define APB0_DIV_1 0 +#define APB0_DIV_2 1 +#define APB0_DIV_4 2 +#define APB0_DIV_8 3 +#define CPU_CLK_SRC_SHIFT (16) +#define CPU_CLK_SRC_OSC24M 1 +#define CPU_CLK_SRC_PLL1 2 + +#define CCM_PLL1_CFG_ENABLE_SHIFT 31 +#define CCM_PLL1_CFG_VCO_RST_SHIFT 30 +#define CCM_PLL1_CFG_VCO_BIAS_SHIFT 26 +#define CCM_PLL1_CFG_PLL4_EXCH_SHIFT 25 +#define CCM_PLL1_CFG_BIAS_CUR_SHIFT 20 +#define CCM_PLL1_CFG_DIVP_SHIFT 16 +#define CCM_PLL1_CFG_LCK_TMR_SHIFT 13 +#define CCM_PLL1_CFG_FACTOR_N_SHIFT 8 +#define CCM_PLL1_CFG_FACTOR_K_SHIFT 4 +#define CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT 3 +#define CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT 2 +#define CCM_PLL1_CFG_FACTOR_M_SHIFT 0 + +#define PLL1_CFG_DEFAULT 0xa1005000 + +#define PLL6_CFG_DEFAULT 0xa1009911 + +/* nand clock */ +#define NAND_CLK_SRC_OSC24 0 +#define NAND_CLK_DIV_N 0 +#define NAND_CLK_DIV_M 0 + +/* gps clock */ +#define GPS_SCLK_GATING_OFF 0 +#define GPS_RESET 0 + +/* ahb clock gate bit offset */ +#define AHB_GATE_OFFSET_GPS 26 +#define AHB_GATE_OFFSET_SATA 25 +#define AHB_GATE_OFFSET_PATA 24 +#define AHB_GATE_OFFSET_SPI3 23 +#define AHB_GATE_OFFSET_SPI2 22 +#define AHB_GATE_OFFSET_SPI1 21 +#define AHB_GATE_OFFSET_SPI0 20 +#define AHB_GATE_OFFSET_TS0 18 +#define AHB_GATE_OFFSET_EMAC 17 +#define AHB_GATE_OFFSET_ACE 16 +#define AHB_GATE_OFFSET_DLL 15 +#define AHB_GATE_OFFSET_SDRAM 14 +#define AHB_GATE_OFFSET_NAND 13 +#define AHB_GATE_OFFSET_MS 12 +#define AHB_GATE_OFFSET_MMC3 11 +#define AHB_GATE_OFFSET_MMC2 10 +#define AHB_GATE_OFFSET_MMC1 9 +#define AHB_GATE_OFFSET_MMC0 8 +#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) +#define AHB_GATE_OFFSET_BIST 7 +#define AHB_GATE_OFFSET_DMA 6 +#define AHB_GATE_OFFSET_SS 5 +#define AHB_GATE_OFFSET_USB_OHCI1 4 +#define AHB_GATE_OFFSET_USB_EHCI1 3 +#define AHB_GATE_OFFSET_USB_OHCI0 2 +#define AHB_GATE_OFFSET_USB_EHCI0 1 +#define AHB_GATE_OFFSET_USB 0 + +/* ahb clock gate bit offset (second register) */ +#define AHB_GATE_OFFSET_GMAC 17 + +#define CCM_AHB_GATE_GPS (0x1 << 26) +#define CCM_AHB_GATE_SDRAM (0x1 << 14) +#define CCM_AHB_GATE_DLL (0x1 << 15) +#define CCM_AHB_GATE_ACE (0x1 << 16) + +#define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0) +#define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3) +#define CCM_PLL5_CTRL_M_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_M1(n) (((n) & 0x3) << 2) +#define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3) +#define CCM_PLL5_CTRL_M1_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4) +#define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3) +#define CCM_PLL5_CTRL_K_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_LDO (0x1 << 7) +#define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8) +#define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f) +#define CCM_PLL5_CTRL_N_X(n) (n) +#define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16) +#define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3) +#define CCM_PLL5_CTRL_P_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_BW (0x1 << 18) +#define CCM_PLL5_CTRL_VCO_GAIN (0x1 << 19) +#define CCM_PLL5_CTRL_BIAS(n) (((n) & 0x1f) << 20) +#define CCM_PLL5_CTRL_BIAS_MASK CCM_PLL5_CTRL_BIAS(0x1f) +#define CCM_PLL5_CTRL_BIAS_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_VCO_BIAS (0x1 << 25) +#define CCM_PLL5_CTRL_DDR_CLK (0x1 << 29) +#define CCM_PLL5_CTRL_BYPASS (0x1 << 30) +#define CCM_PLL5_CTRL_EN (0x1 << 31) + +#define CCM_PLL6_CTRL_N_SHIFT 8 +#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) +#define CCM_PLL6_CTRL_K_SHIFT 4 +#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) + +#define CCM_GPS_CTRL_RESET (0x1 << 0) +#define CCM_GPS_CTRL_GATE (0x1 << 1) + +#define CCM_DRAM_CTRL_DCLK_OUT (0x1 << 15) + +#define CCM_MBUS_CTRL_M(n) (((n) & 0xf) << 0) +#define CCM_MBUS_CTRL_M_MASK CCM_MBUS_CTRL_M(0xf) +#define CCM_MBUS_CTRL_M_X(n) ((n) - 1) +#define CCM_MBUS_CTRL_N(n) (((n) & 0xf) << 16) +#define CCM_MBUS_CTRL_N_MASK CCM_MBUS_CTRL_N(0xf) +#define CCM_MBUS_CTRL_N_X(n) (((n) >> 3) ? 3 : (((n) >> 2) ? 2 : (((n) >> 1) ? 1 : 0))) +#define CCM_MBUS_CTRL_CLK_SRC(n) (((n) & 0x3) << 24) +#define CCM_MBUS_CTRL_CLK_SRC_MASK CCM_MBUS_CTRL_CLK_SRC(0x3) +#define CCM_MBUS_CTRL_CLK_SRC_HOSC 0x0 +#define CCM_MBUS_CTRL_CLK_SRC_PLL6 0x1 +#define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2 +#define CCM_MBUS_CTRL_GATE (0x1 << 31) + +#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) +#define CCM_MMC_CTRL_PLL6 (0x1 << 24) +#define CCM_MMC_CTRL_PLL5 (0x2 << 24) + +#define CCM_MMC_CTRL_ENABLE (0x1 << 31) + +#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 +#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 +#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 +#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) +#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) + +#endif /* _SUNXI_CLOCK_SUN4I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h new file mode 100644 index 000000000..a987e51d5 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CPU_H +#define _SUNXI_CPU_H + +#define SUNXI_SRAM_A1_BASE 0x00000000 +#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ + +#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */ +#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */ +#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ +#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ +#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ + +#define SUNXI_SRAMC_BASE 0x01c00000 +#define SUNXI_DRAMC_BASE 0x01c01000 +#define SUNXI_DMA_BASE 0x01c02000 +#define SUNXI_NFC_BASE 0x01c03000 +#define SUNXI_TS_BASE 0x01c04000 +#define SUNXI_SPI0_BASE 0x01c05000 +#define SUNXI_SPI1_BASE 0x01c06000 +#define SUNXI_MS_BASE 0x01c07000 +#define SUNXI_TVD_BASE 0x01c08000 +#define SUNXI_CSI0_BASE 0x01c09000 +#define SUNXI_TVE0_BASE 0x01c0a000 +#define SUNXI_EMAC_BASE 0x01c0b000 +#define SUNXI_LCD0_BASE 0x01c0C000 +#define SUNXI_LCD1_BASE 0x01c0d000 +#define SUNXI_VE_BASE 0x01c0e000 +#define SUNXI_MMC0_BASE 0x01c0f000 +#define SUNXI_MMC1_BASE 0x01c10000 +#define SUNXI_MMC2_BASE 0x01c11000 +#define SUNXI_MMC3_BASE 0x01c12000 +#define SUNXI_USB0_BASE 0x01c13000 +#define SUNXI_USB1_BASE 0x01c14000 +#define SUNXI_SS_BASE 0x01c15000 +#define SUNXI_HDMI_BASE 0x01c16000 +#define SUNXI_SPI2_BASE 0x01c17000 +#define SUNXI_SATA_BASE 0x01c18000 +#define SUNXI_PATA_BASE 0x01c19000 +#define SUNXI_ACE_BASE 0x01c1a000 +#define SUNXI_TVE1_BASE 0x01c1b000 +#define SUNXI_USB2_BASE 0x01c1c000 +#define SUNXI_CSI1_BASE 0x01c1d000 +#define SUNXI_TZASC_BASE 0x01c1e000 +#define SUNXI_SPI3_BASE 0x01c1f000 + +#define SUNXI_CCM_BASE 0x01c20000 +#define SUNXI_INTC_BASE 0x01c20400 +#define SUNXI_PIO_BASE 0x01c20800 +#define SUNXI_TIMER_BASE 0x01c20c00 +#define SUNXI_SPDIF_BASE 0x01c21000 +#define SUNXI_AC97_BASE 0x01c21400 +#define SUNXI_IR0_BASE 0x01c21800 +#define SUNXI_IR1_BASE 0x01c21c00 + +#define SUNXI_IIS_BASE 0x01c22400 +#define SUNXI_LRADC_BASE 0x01c22800 +#define SUNXI_AD_DA_BASE 0x01c22c00 +#define SUNXI_KEYPAD_BASE 0x01c23000 +#define SUNXI_TZPC_BASE 0x01c23400 +#define SUNXI_SID_BASE 0x01c23800 +#define SUNXI_SJTAG_BASE 0x01c23c00 + +#define SUNXI_TP_BASE 0x01c25000 +#define SUNXI_PMU_BASE 0x01c25400 +#define SUNXI_CPUCFG_BASE 0x01c25c00 + +#define SUNXI_UART0_BASE 0x01c28000 +#define SUNXI_UART1_BASE 0x01c28400 +#define SUNXI_UART2_BASE 0x01c28800 +#define SUNXI_UART3_BASE 0x01c28c00 +#define SUNXI_UART4_BASE 0x01c29000 +#define SUNXI_UART5_BASE 0x01c29400 +#define SUNXI_UART6_BASE 0x01c29800 +#define SUNXI_UART7_BASE 0x01c29c00 +#define SUNXI_PS2_0_BASE 0x01c2a000 +#define SUNXI_PS2_1_BASE 0x01c2a400 + +#define SUNXI_TWI0_BASE 0x01c2ac00 +#define SUNXI_TWI1_BASE 0x01c2b000 +#define SUNXI_TWI2_BASE 0x01c2b400 + +#define SUNXI_CAN_BASE 0x01c2bc00 + +#define SUNXI_SCR_BASE 0x01c2c400 + +#define SUNXI_GPS_BASE 0x01c30000 +#define SUNXI_MALI400_BASE 0x01c40000 +#define SUNXI_GMAC_BASE 0x01c50000 + +/* module sram */ +#define SUNXI_SRAM_C_BASE 0x01d00000 + +#define SUNXI_DE_FE0_BASE 0x01e00000 +#define SUNXI_DE_FE1_BASE 0x01e20000 +#define SUNXI_DE_BE0_BASE 0x01e60000 +#define SUNXI_DE_BE1_BASE 0x01e40000 +#define SUNXI_MP_BASE 0x01e80000 +#define SUNXI_AVG_BASE 0x01ea0000 + +/* CoreSight Debug Module */ +#define SUNXI_CSDM_BASE 0x3f500000 + +#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */ + +#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */ + +#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) + +#ifndef __ASSEMBLY__ +void sunxi_board_init(void); +void sunxi_reset(void); +#endif /* __ASSEMBLY__ */ + +#endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h new file mode 100644 index 000000000..67fbfad07 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -0,0 +1,179 @@ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Berg Xing <bergxing@allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * Sunxi platform dram register definition. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DRAM_H +#define _SUNXI_DRAM_H + +#include <linux/types.h> + +struct sunxi_dram_reg { + u32 ccr; /* 0x00 controller configuration register */ + u32 dcr; /* 0x04 dram configuration register */ + u32 iocr; /* 0x08 i/o configuration register */ + u32 csr; /* 0x0c controller status register */ + u32 drr; /* 0x10 dram refresh register */ + u32 tpr0; /* 0x14 dram timing parameters register 0 */ + u32 tpr1; /* 0x18 dram timing parameters register 1 */ + u32 tpr2; /* 0x1c dram timing parameters register 2 */ + u32 gdllcr; /* 0x20 global dll control register */ + u8 res0[0x28]; + u32 rslr0; /* 0x4c rank system latency register */ + u32 rslr1; /* 0x50 rank system latency register */ + u8 res1[0x8]; + u32 rdgr0; /* 0x5c rank dqs gating register */ + u32 rdgr1; /* 0x60 rank dqs gating register */ + u8 res2[0x34]; + u32 odtcr; /* 0x98 odt configuration register */ + u32 dtr0; /* 0x9c data training register 0 */ + u32 dtr1; /* 0xa0 data training register 1 */ + u32 dtar; /* 0xa4 data training address register */ + u32 zqcr0; /* 0xa8 zq control register 0 */ + u32 zqcr1; /* 0xac zq control register 1 */ + u32 zqsr; /* 0xb0 zq status register */ + u32 idcr; /* 0xb4 initializaton delay configure reg */ + u8 res3[0x138]; + u32 mr; /* 0x1f0 mode register */ + u32 emr; /* 0x1f4 extended mode register */ + u32 emr2; /* 0x1f8 extended mode register */ + u32 emr3; /* 0x1fc extended mode register */ + u32 dllctr; /* 0x200 dll control register */ + u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */ + /* 0x208 dll control register 1(byte 1) */ + /* 0x20c dll control register 2(byte 2) */ + /* 0x210 dll control register 3(byte 3) */ + /* 0x214 dll control register 4(byte 4) */ + u32 dqtr0; /* 0x218 dq timing register */ + u32 dqtr1; /* 0x21c dq timing register */ + u32 dqtr2; /* 0x220 dq timing register */ + u32 dqtr3; /* 0x224 dq timing register */ + u32 dqstr; /* 0x228 dqs timing register */ + u32 dqsbtr; /* 0x22c dqsb timing register */ + u32 mcr; /* 0x230 mode configure register */ + u8 res[0x8]; + u32 ppwrsctl; /* 0x23c pad power save control */ + u32 apr; /* 0x240 arbiter period register */ + u32 pldtr; /* 0x244 priority level data threshold reg */ + u8 res5[0x8]; + u32 hpcr[32]; /* 0x250 host port configure register */ + u8 res6[0x10]; + u32 csel; /* 0x2e0 controller select register */ +}; + +struct dram_para { + u32 clock; + u32 type; + u32 rank_num; + u32 density; + u32 io_width; + u32 bus_width; + u32 cas; + u32 zq; + u32 odt_en; + u32 size; + u32 tpr0; + u32 tpr1; + u32 tpr2; + u32 tpr3; + u32 tpr4; + u32 tpr5; + u32 emr1; + u32 emr2; + u32 emr3; +}; + +#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5) +#define DRAM_CCR_DQS_GATE (0x1 << 14) +#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17) +#define DRAM_CCR_ITM_OFF (0x1 << 28) +#define DRAM_CCR_DATA_TRAINING (0x1 << 30) +#define DRAM_CCR_INIT (0x1 << 31) + +#define DRAM_MEMORY_TYPE_DDR1 1 +#define DRAM_MEMORY_TYPE_DDR2 2 +#define DRAM_MEMORY_TYPE_DDR3 3 +#define DRAM_MEMORY_TYPE_LPDDR2 4 +#define DRAM_MEMORY_TYPE_LPDDR 5 +#define DRAM_DCR_TYPE (0x1 << 0) +#define DRAM_DCR_TYPE_DDR2 0x0 +#define DRAM_DCR_TYPE_DDR3 0x1 +#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1) +#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3) +#define DRAM_DCR_IO_WIDTH_8BIT 0x0 +#define DRAM_DCR_IO_WIDTH_16BIT 0x1 +#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3) +#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7) +#define DRAM_DCR_CHIP_DENSITY_256M 0x0 +#define DRAM_DCR_CHIP_DENSITY_512M 0x1 +#define DRAM_DCR_CHIP_DENSITY_1024M 0x2 +#define DRAM_DCR_CHIP_DENSITY_2048M 0x3 +#define DRAM_DCR_CHIP_DENSITY_4096M 0x4 +#define DRAM_DCR_CHIP_DENSITY_8192M 0x5 +#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6) +#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7) +#define DRAM_DCR_BUS_WIDTH_32BIT 0x3 +#define DRAM_DCR_BUS_WIDTH_16BIT 0x1 +#define DRAM_DCR_BUS_WIDTH_8BIT 0x0 +#define DRAM_DCR_NR_DLLCR_32BIT 5 +#define DRAM_DCR_NR_DLLCR_16BIT 3 +#define DRAM_DCR_NR_DLLCR_8BIT 2 +#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10) +#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3) +#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12) +#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13) +#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3) +#define DRAM_DCR_MODE_SEQ 0x0 +#define DRAM_DCR_MODE_INTERLEAVE 0x1 + +#define DRAM_CSR_FAILED (0x1 << 20) + +#define DRAM_DRR_TRFC(n) ((n) & 0xff) +#define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8) +#define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24) + +#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0) +#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3) +#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2) +#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3) +#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4) +#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3) +#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6) +#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3) +#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8) +#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7) +#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11) +#define DRAM_MCR_RESET (0x1 << 12) +#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13) +#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3) +#define DRAM_MCR_DCLK_OUT (0x1 << 16) + +#define DRAM_DLLCR_NRESET (0x1 << 30) +#define DRAM_DLLCR_DISABLE (0x1 << 31) + +#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20) +#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff) + +#define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0) +#define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3) + +#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0) +#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7) +#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4) +#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7) +#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9) +#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7) +#define DRAM_MR_POWER_DOWN (0x1 << 12) + +#define DRAM_CSEL_MAGIC 0x16237495 + +unsigned long sunxi_dram_init(void); +unsigned long dramc_init(struct dram_para *para); + +#endif /* _SUNXI_DRAM_H */ diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h new file mode 100644 index 000000000..892479c18 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -0,0 +1,147 @@ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_GPIO_H +#define _SUNXI_GPIO_H + +#include <linux/types.h> + +/* + * sunxi has 9 banks of gpio, they are: + * PA0 - PA17 | PB0 - PB23 | PC0 - PC24 + * PD0 - PD27 | PE0 - PE31 | PF0 - PF5 + * PG0 - PG9 | PH0 - PH27 | PI0 - PI12 + */ + +#define SUNXI_GPIO_A 0 +#define SUNXI_GPIO_B 1 +#define SUNXI_GPIO_C 2 +#define SUNXI_GPIO_D 3 +#define SUNXI_GPIO_E 4 +#define SUNXI_GPIO_F 5 +#define SUNXI_GPIO_G 6 +#define SUNXI_GPIO_H 7 +#define SUNXI_GPIO_I 8 +#define SUNXI_GPIO_BANKS 9 + +struct sunxi_gpio { + u32 cfg[4]; + u32 dat; + u32 drv[2]; + u32 pull[2]; +}; + +/* gpio interrupt control */ +struct sunxi_gpio_int { + u32 cfg[3]; + u32 ctl; + u32 sta; + u32 deb; /* interrupt debounce */ +}; + +struct sunxi_gpio_reg { + struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS]; + u8 res[0xbc]; + struct sunxi_gpio_int gpio_int; +}; + +#define BANK_TO_GPIO(bank) \ + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] + +#define GPIO_BANK(pin) ((pin) >> 5) +#define GPIO_NUM(pin) ((pin) & 0x1f) + +#define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3) +#define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2) + +#define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4) +#define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) + +#define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4) +#define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) + +/* GPIO bank sizes */ +#define SUNXI_GPIO_A_NR 32 +#define SUNXI_GPIO_B_NR 32 +#define SUNXI_GPIO_C_NR 32 +#define SUNXI_GPIO_D_NR 32 +#define SUNXI_GPIO_E_NR 32 +#define SUNXI_GPIO_F_NR 32 +#define SUNXI_GPIO_G_NR 32 +#define SUNXI_GPIO_H_NR 32 +#define SUNXI_GPIO_I_NR 32 + +#define SUNXI_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + (__gpio##_NR) + 0) + +enum sunxi_gpio_number { + SUNXI_GPIO_A_START = 0, + SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A), + SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B), + SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C), + SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D), + SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E), + SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), + SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), + SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), +}; + +/* SUNXI GPIO number definitions */ +#define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr)) +#define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr)) +#define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr)) +#define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr)) +#define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr)) +#define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr)) +#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) +#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) +#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) + +/* GPIO pin function config */ +#define SUNXI_GPIO_INPUT 0 +#define SUNXI_GPIO_OUTPUT 1 + +#define SUNXI_GPA0_EMAC 2 +#define SUN7I_GPA0_GMAC 5 + +#define SUNXI_GPB0_TWI0 2 + +#define SUN4I_GPB22_UART0_TX 2 +#define SUN4I_GPB23_UART0_RX 2 + +#define SUN5I_GPB19_UART0_TX 2 +#define SUN5I_GPB20_UART0_RX 2 + +#define SUN5I_GPG3_UART1_TX 4 +#define SUN5I_GPG4_UART1_RX 4 + +#define SUNXI_GPC6_SDC2 3 + +#define SUNXI_GPF0_SDC0 2 + +#define SUNXI_GPF2_SDC0 2 +#define SUNXI_GPF2_UART0_TX 4 +#define SUNXI_GPF4_UART0_RX 4 + +#define SUN4I_GPG0_SDC1 4 + +#define SUN4I_GPH22_SDC1 5 + +#define SUN4I_GPI4_SDC3 2 + +/* GPIO pin pull-up/down config */ +#define SUNXI_GPIO_PULL_DISABLE 0 +#define SUNXI_GPIO_PULL_UP 1 +#define SUNXI_GPIO_PULL_DOWN 2 + +int sunxi_gpio_set_cfgpin(u32 pin, u32 val); +int sunxi_gpio_get_cfgpin(u32 pin); +int sunxi_gpio_set_drv(u32 pin, u32 val); +int sunxi_gpio_set_pull(u32 pin, u32 val); + +#endif /* _SUNXI_GPIO_H */ diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h new file mode 100644 index 000000000..53196e3b0 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Aaron <leafy.myeh@allwinnertech.com> + * + * MMC register definition for allwinner sunxi platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_MMC_H +#define _SUNXI_MMC_H + +#include <linux/types.h> + +struct sunxi_mmc { + u32 gctrl; /* 0x00 global control */ + u32 clkcr; /* 0x04 clock control */ + u32 timeout; /* 0x08 time out */ + u32 width; /* 0x0c bus width */ + u32 blksz; /* 0x10 block size */ + u32 bytecnt; /* 0x14 byte count */ + u32 cmd; /* 0x18 command */ + u32 arg; /* 0x1c argument */ + u32 resp0; /* 0x20 response 0 */ + u32 resp1; /* 0x24 response 1 */ + u32 resp2; /* 0x28 response 2 */ + u32 resp3; /* 0x2c response 3 */ + u32 imask; /* 0x30 interrupt mask */ + u32 mint; /* 0x34 masked interrupt status */ + u32 rint; /* 0x38 raw interrupt status */ + u32 status; /* 0x3c status */ + u32 ftrglevel; /* 0x40 FIFO threshold watermark*/ + u32 funcsel; /* 0x44 function select */ + u32 cbcr; /* 0x48 CIU byte count */ + u32 bbcr; /* 0x4c BIU byte count */ + u32 dbgc; /* 0x50 debug enable */ + u32 res0[11]; + u32 dmac; /* 0x80 internal DMA control */ + u32 dlba; /* 0x84 internal DMA descr list base address */ + u32 idst; /* 0x88 internal DMA status */ + u32 idie; /* 0x8c internal DMA interrupt enable */ + u32 chda; /* 0x90 */ + u32 cbda; /* 0x94 */ + u32 res1[26]; + u32 fifo; /* 0x100 FIFO access address */ +}; + +#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17) +#define SUNXI_MMC_CLK_ENABLE (0x1 << 16) +#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff) + +#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0) +#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1) +#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2) +#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\ + SUNXI_MMC_GCTRL_FIFO_RESET|\ + SUNXI_MMC_GCTRL_DMA_RESET) +#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5) +#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31) + +#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6) +#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7) +#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8) +#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9) +#define SUNXI_MMC_CMD_WRITE (0x1 << 10) +#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12) +#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13) +#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15) +#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21) +#define SUNXI_MMC_CMD_START (0x1 << 31) + +#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1) +#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2) +#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3) +#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4) +#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5) +#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6) +#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7) +#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8) +#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9) +#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10) +#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11) +#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12) +#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13) +#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14) +#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15) +#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16) +#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30) +#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31) +#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \ + (SUNXI_MMC_RINT_RESP_ERROR | \ + SUNXI_MMC_RINT_RESP_CRC_ERROR | \ + SUNXI_MMC_RINT_DATA_CRC_ERROR | \ + SUNXI_MMC_RINT_RESP_TIMEOUT | \ + SUNXI_MMC_RINT_DATA_TIMEOUT | \ + SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \ + SUNXI_MMC_RINT_FIFO_RUN_ERROR | \ + SUNXI_MMC_RINT_HARD_WARE_LOCKED | \ + SUNXI_MMC_RINT_START_BIT_ERROR | \ + SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */ +#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \ + (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \ + SUNXI_MMC_RINT_DATA_OVER | \ + SUNXI_MMC_RINT_COMMAND_DONE | \ + SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE) + +#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0) +#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1) +#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2) +#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3) +#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8) +#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9) +#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10) + +#define SUNXI_MMC_IDMAC_RESET (0x1 << 0) +#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1) +#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7) + +#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0) +#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1) + +int sunxi_mmc_init(int sdc_no); +#endif /* _SUNXI_MMC_H */ diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h new file mode 100644 index 000000000..ff871bcae --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/spl.h @@ -0,0 +1,20 @@ +/* + * This is a copy of omap3/spl.h: + * + * (C) Copyright 2012 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_SPL_H_ + +#define BOOT_DEVICE_NONE 0 +#define BOOT_DEVICE_XIP 1 +#define BOOT_DEVICE_NAND 2 +#define BOOT_DEVICE_ONE_NAND 3 +#define BOOT_DEVICE_MMC2 5 /*emmc*/ +#define BOOT_DEVICE_MMC1 6 +#define BOOT_DEVICE_XIPWAIT 7 +#define BOOT_DEVICE_MMC2_2 0xff +#endif diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h new file mode 100644 index 000000000..c3e636e1d --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +#include <linux/types.h> + +void sdelay(unsigned long); + +#endif diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h new file mode 100644 index 000000000..6aacfd7b3 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/timer.h @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * Configuration settings for the Allwinner A10-evb board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_TIMER_H_ +#define _SUNXI_TIMER_H_ + +#ifndef __ASSEMBLY__ + +#include <linux/types.h> + +/* General purpose timer */ +struct sunxi_timer { + u32 ctl; + u32 inter; + u32 val; + u8 res[4]; +}; + +/* Audio video sync*/ +struct sunxi_avs { + u32 ctl; /* 0x80 */ + u32 cnt0; /* 0x84 */ + u32 cnt1; /* 0x88 */ + u32 div; /* 0x8c */ +}; + +/* 64 bit counter */ +struct sunxi_64cnt { + u32 ctl; /* 0xa0 */ + u32 lo; /* 0xa4 */ + u32 hi; /* 0xa8 */ +}; + +/* Watchdog */ +struct sunxi_wdog { + u32 ctl; /* 0x90 */ + u32 mode; /* 0x94 */ +}; + +/* Rtc */ +struct sunxi_rtc { + u32 ctl; /* 0x100 */ + u32 yymmdd; /* 0x104 */ + u32 hhmmss; /* 0x108 */ +}; + +/* Alarm */ +struct sunxi_alarm { + u32 ddhhmmss; /* 0x10c */ + u32 hhmmss; /* 0x110 */ + u32 en; /* 0x114 */ + u32 irqen; /* 0x118 */ + u32 irqsta; /* 0x11c */ +}; + +/* Timer general purpose register */ +struct sunxi_tgp { + u32 tgpd; +}; + +struct sunxi_timer_reg { + u32 tirqen; /* 0x00 */ + u32 tirqsta; /* 0x04 */ + u8 res1[8]; + struct sunxi_timer timer[6]; /* We have 6 timers */ + u8 res2[16]; + struct sunxi_avs avs; + struct sunxi_wdog wdog; + u8 res3[8]; + struct sunxi_64cnt cnt64; + u8 res4[0x58]; + struct sunxi_rtc rtc; + struct sunxi_alarm alarm; + struct sunxi_tgp tgp[4]; + u8 res5[8]; + u32 cpu_cfg; +}; + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h index d97190dd7..44cd45569 100644 --- a/arch/arm/include/asm/arch-tegra/gpio.h +++ b/arch/arm/include/asm/arch-tegra/gpio.h @@ -14,11 +14,31 @@ #define GPIO_FULLPORT(x) ((x) >> 3) #define GPIO_BIT(x) ((x) & 0x7) +enum tegra_gpio_init { + TEGRA_GPIO_INIT_IN, + TEGRA_GPIO_INIT_OUT0, + TEGRA_GPIO_INIT_OUT1, +}; + +struct tegra_gpio_config { + u32 gpio:16; + u32 init:2; +}; + /* * Tegra-specific GPIO API */ +/** + * Configure a list of GPIOs + * + * @param config List of GPIO configurations + * @param len Number of config items in list + */ +void gpio_config_table(const struct tegra_gpio_config *config, int len); + void gpio_info(void); #define gpio_status() gpio_info() + #endif /* TEGRA_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index 035159d66..da477697b 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -80,6 +80,11 @@ struct pmux_pingrp_config { #endif }; +#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30) +/* Set the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */ +void pinmux_set_tristate_input_clamping(void); +#endif + /* Set the mux function for a pin group */ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index 310bbd7df..84e7b5553 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -14,8 +14,6 @@ /* for mmc_config definition */ #include <mmc.h> -#define MAX_HOSTS 4 /* Max number of 'hosts'/controllers */ - #ifndef __ASSEMBLY__ struct tegra_mmc { unsigned int sysad; /* _SYSTEM_ADDRESS_0 */ diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h index ceb7bcd9c..c817088fa 100644 --- a/arch/arm/include/asm/arch-tegra/usb.h +++ b/arch/arm/include/asm/arch-tegra/usb.h @@ -349,6 +349,8 @@ struct usb_ctlr { /* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ #define VBUS_VLD_STS (1 << 26) +#define VBUS_B_SESS_VLD_SW_VALUE (1 << 12) +#define VBUS_B_SESS_VLD_SW_EN (1 << 11) /* Setup USB on the board */ int usb_process_devicetree(const void *blob); diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h index c1cb3ef16..b86562ac6 100644 --- a/arch/arm/include/asm/arch-tegra114/pinmux.h +++ b/arch/arm/include/asm/arch-tegra114/pinmux.h @@ -231,6 +231,7 @@ enum pmux_drvgrp { }; enum pmux_func { + PMUX_FUNC_DEFAULT, PMUX_FUNC_BLINK, PMUX_FUNC_CEC, PMUX_FUNC_CLDVFS, diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h index c49801c21..1884935a5 100644 --- a/arch/arm/include/asm/arch-tegra124/pinmux.h +++ b/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -247,6 +247,7 @@ enum pmux_drvgrp { }; enum pmux_func { + PMUX_FUNC_DEFAULT, PMUX_FUNC_BLINK, PMUX_FUNC_CCLA, PMUX_FUNC_CEC, diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h index 11c0104ff..f7bc97fe5 100644 --- a/arch/arm/include/asm/arch-tegra20/pinmux.h +++ b/arch/arm/include/asm/arch-tegra20/pinmux.h @@ -166,6 +166,7 @@ enum pmux_pingrp { * purely a convenience. The translation is done through a table search. */ enum pmux_func { + PMUX_FUNC_DEFAULT, PMUX_FUNC_AHB_CLK, PMUX_FUNC_APB_CLK, PMUX_FUNC_AUDIO_SYNC, diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h index 6d83061dc..a42e00990 100644 --- a/arch/arm/include/asm/arch-tegra30/pinmux.h +++ b/arch/arm/include/asm/arch-tegra30/pinmux.h @@ -306,6 +306,7 @@ enum pmux_drvgrp { }; enum pmux_func { + PMUX_FUNC_DEFAULT, PMUX_FUNC_BLINK, PMUX_FUNC_CEC, PMUX_FUNC_CLK_12M_OUT, diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index c2f976184..0c28e1b84 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -215,6 +215,7 @@ #define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff) #define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27) #define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21) +#define DDRMC_CR154_DDR_SEL_PAD_CONTR(v) (((v) & 0x3) << 18) #define DDRMC_CR155_AXI0_AWCACHE (1 << 10) #define DDRMC_CR155_PAD_ODT_BYTE1(v) ((v) & 0x7) #define DDRMC_CR158_TWR(v) ((v) & 0x3f) diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 39184da40..2aede0c55 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -22,9 +22,12 @@ #define ZYNQ_SPI_BASEADDR0 0xE0006000 #define ZYNQ_SPI_BASEADDR1 0xE0007000 #define ZYNQ_DDRC_BASEADDR 0xF8006000 +#define ZYNQ_EFUSE_BASEADDR 0xF800D000 +#define ZYNQ_USB_BASEADDR0 0xE0002000 +#define ZYNQ_USB_BASEADDR1 0xE0003000 /* Bootmode setting values */ -#define ZYNQ_BM_MASK 0xF +#define ZYNQ_BM_MASK 0x7 #define ZYNQ_BM_NOR 0x2 #define ZYNQ_BM_SD 0x5 #define ZYNQ_BM_JTAG 0x0 @@ -130,4 +133,12 @@ struct ddrc_regs { }; #define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR) +struct efuse_reg { + u32 reserved1[4]; + u32 status; + u32 reserved2[3]; +}; + +#define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR) + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index a68e1b3d2..53c30ec6c 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -15,7 +15,9 @@ extern void zynq_slcr_devcfg_disable(void); extern void zynq_slcr_devcfg_enable(void); extern u32 zynq_slcr_get_boot_mode(void); extern u32 zynq_slcr_get_idcode(void); +extern int zynq_slcr_get_mio_pin_status(const char *periph); extern void zynq_ddrc_init(void); +extern unsigned int zynq_get_silicon_version(void); /* Driver extern functions */ extern int zynq_sdhci_init(u32 regbase); diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index dec11a133..cca920b28 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -111,6 +111,11 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_DSE_40ohm (6 << 3) #define PAD_CTL_DSE_34ohm (7 << 3) +#if defined CONFIG_MX6SL +#define PAD_CTL_LVE (1 << 1) +#define PAD_CTL_LVE_BIT (1 << 22) +#endif + #elif defined(CONFIG_VF610) #define PAD_MUX_MODE_SHIFT 20 diff --git a/arch/arm/include/asm/imx-common/video.h b/arch/arm/include/asm/imx-common/video.h new file mode 100644 index 000000000..2d948508d --- /dev/null +++ b/arch/arm/include/asm/imx-common/video.h @@ -0,0 +1,24 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX_VIDEO_H_ +#define __IMX_VIDEO_H_ + +#include <linux/fb.h> +#include <ipu_pixfmt.h> + +struct display_info_t { + int bus; + int addr; + int pixfmt; + int (*detect)(struct display_info_t const *dev); + void (*enable)(struct display_info_t const *dev); + struct fb_videomode mode; +}; + +#ifdef CONFIG_IMX_HDMI +extern int detect_hdmi(struct display_info_t const *dev); +#endif + +#endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 729723afe..d1344ee94 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -576,12 +576,6 @@ s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb); void usb_fake_mac_from_die_id(u32 *id); -/* HW Init Context */ -#define OMAP_INIT_CONTEXT_SPL 0 -#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1 -#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2 -#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3 - /* ABB */ #define OMAP_ABB_NOMINAL_OPP 0 #define OMAP_ABB_FAST_OPP 1 @@ -645,6 +639,7 @@ static inline u8 is_dra7xx(void) /* DRA7XX */ #define DRA752_ES1_0 0x07520100 #define DRA752_ES1_1 0x07520110 +#define DRA722_ES1_0 0x07220100 /* * SRAM scratch space entries diff --git a/arch/arm/include/asm/ti-common/sys_proto.h b/arch/arm/include/asm/ti-common/sys_proto.h new file mode 100644 index 000000000..d3ab75fa3 --- /dev/null +++ b/arch/arm/include/asm/ti-common/sys_proto.h @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2014 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _TI_COMMON_SYS_PROTO_H_ +#define _TI_COMMON_SYS_PROTO_H_ + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_OMAP_COMMON +#define TI_ARMV7_DRAM_ADDR_SPACE_START 0x80000000 +#define TI_ARMV7_DRAM_ADDR_SPACE_END 0xFFFFFFFF + +#define OMAP_INIT_CONTEXT_SPL 0 +#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1 +#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2 +#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3 + +static inline u32 running_from_sdram(void) +{ + u32 pc; + asm volatile ("mov %0, pc" : "=r" (pc)); + return ((pc >= TI_ARMV7_DRAM_ADDR_SPACE_START) && + (pc < TI_ARMV7_DRAM_ADDR_SPACE_END)); +} + +static inline u8 uboot_loaded_by_spl(void) +{ + /* + * u-boot can be running from sdram either because of configuration + * Header or by SPL. If because of CH, then the romcode sets the + * CHSETTINGS executed bit to true in the boot parameter structure that + * it passes to the bootloader.This parameter is stored in the ch_flags + * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a + * mandatory section if CH is present. + */ + if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) + return 0; + else + return running_from_sdram(); +} + +/* + * The basic hardware init of OMAP(s_init()) can happen in 4 + * different contexts: + * 1. SPL running from SRAM + * 2. U-Boot running from FLASH + * 3. Non-XIP U-Boot loaded to SDRAM by SPL + * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the + * Configuration Header feature + * + * This function finds this context. + * Defining as inline may help in compiling out unused functions in SPL + */ +static inline u32 omap_hw_init_context(void) +{ +#ifdef CONFIG_SPL_BUILD + return OMAP_INIT_CONTEXT_SPL; +#else + if (uboot_loaded_by_spl()) + return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL; + else if (running_from_sdram()) + return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH; + else + return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR; +#endif +} +#endif + +#endif diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index e035d6acc..585f1f781 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -11,7 +11,7 @@ lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \ ifdef CONFIG_ARM64 obj-y += crt0_64.o else -obj-y += crt0.o +obj-y += vectors.o crt0.o endif ifndef CONFIG_SPL_BUILD diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 6cc136aa3..4f6b9f01c 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -12,16 +12,23 @@ void __flush_cache(unsigned long start, unsigned long size) { #if defined(CONFIG_ARM1136) - void arm1136_cache_flush(void); - arm1136_cache_flush(); +#if !defined(CONFIG_SYS_ICACHE_OFF) + asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */ #endif + +#if !defined(CONFIG_SYS_DCACHE_OFF) + asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */ +#endif + +#endif /* CONFIG_ARM1136 */ + #ifdef CONFIG_ARM926EJS /* test and clean, page 2-23 of arm926ejs manual */ asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); -#endif +#endif /* CONFIG_ARM926EJS */ return; } void flush_cache(unsigned long start, unsigned long size) diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S new file mode 100644 index 000000000..d68cc477d --- /dev/null +++ b/arch/arm/lib/vectors.S @@ -0,0 +1,291 @@ +/* + * vectors - Generic ARM exception table code + * + * Copyright (c) 1998 Dan Malek <dmalek@jlc.net> + * Copyright (c) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> + * Copyright (c) 2000 Wolfgang Denk <wd@denx.de> + * Copyright (c) 2001 Alex Züpke <azu@sysgo.de> + * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> + * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> + * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> + * Copyright (c) 2002 Kyle Harris <kharris@nexus-tech.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + ************************************************************************* + * + * Symbol _start is referenced elsewhere, so make it global + * + ************************************************************************* + */ + +.globl _start + +/* + ************************************************************************* + * + * Vectors have their own section so linker script can map them easily + * + ************************************************************************* + */ + + .section ".vectors", "x" + +/* + ************************************************************************* + * + * Exception vectors as described in ARM reference manuals + * + * Uses indirect branch to allow reaching handlers anywhere in memory. + * + ************************************************************************* + */ + +_start: + +#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG + .word CONFIG_SYS_DV_NOR_BOOT_CFG +#endif + +_start: + ldr pc, _reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +/* + ************************************************************************* + * + * Indirect vectors table + * + * Symbols referenced here must be defined somewhere else + * + ************************************************************************* + */ + + .globl _undefined_instruction + .globl _software_interrupt + .globl _prefetch_abort + .globl _data_abort + .globl _not_used + .globl _irq + .globl _fiq + +_reset: .word reset +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq + + .balignl 16,0xdeadbeef + +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ + +/* SPL interrupt handling: just hang */ + +#ifdef CONFIG_SPL_BUILD + + .align 5 +undefined_instruction: +software_interrupt: +prefetch_abort: +data_abort: +not_used: +irq: +fiq: + +1: + bl 1b /* hang and never return */ + +#else /* !CONFIG_SPL_BUILD */ + +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de + +#endif /* CONFIG_USE_IRQ */ + +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + @ carve out a frame on current user stack + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 + ldr r2, IRQ_STACK_START_IN + @ get values for "aborted" pc and cpsr (into parm regs) + ldmia r2, {r2 - r3} + add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp @ save current stack into r0 (param register) + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, IRQ_STACK_START_IN @ setup our mode stack + + str lr, [r13] @ save caller lr in position 0 of saved stack + mrs lr, spsr @ get the spsr + str lr, [r13, #4] @ save spsr in position 1 of saved stack + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 @ switch modes, make sure moves will execute + mov lr, pc @ capture return pc + movs pc, lr @ jump to next instruction & switch modes. + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif /* CONFIG_USE_IRQ */ + +#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c index 318ca01ea..6de920eb4 100644 --- a/arch/m68k/lib/board.c +++ b/arch/m68k/lib/board.c @@ -628,13 +628,6 @@ void board_init_r (gd_t *id, ulong dest_addr) } #endif -#ifdef CONFIG_MODEM_SUPPORT - { - extern int do_mdm_init; - do_mdm_init = gd->do_mdm_init; - } -#endif - #ifdef CONFIG_WATCHDOG /* disable watchdog if environment is set */ if ((s = getenv ("watchdog")) != NULL) { diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 57b4a09b0..300ab12a3 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -991,14 +991,6 @@ void board_init_r(gd_t *id, ulong dest_addr) kbd_init(); #endif -#ifdef CONFIG_MODEM_SUPPORT - { - extern int do_mdm_init; - - do_mdm_init = gd->do_mdm_init; - } -#endif - /* Initialization complete - start the monitor */ /* main_loop() can return to retry autoboot, if so just run it again. */ diff --git a/arch/sandbox/include/asm/gpio.h b/arch/sandbox/include/asm/gpio.h index 95b59da6b..8317db1ad 100644 --- a/arch/sandbox/include/asm/gpio.h +++ b/arch/sandbox/include/asm/gpio.h @@ -29,7 +29,7 @@ * @param gp GPIO number * @return -1 on error, 0 if GPIO is low, >0 if high */ -int sandbox_gpio_get_value(struct device *dev, unsigned int offset); +int sandbox_gpio_get_value(struct udevice *dev, unsigned int offset); /** * Set the simulated value of a GPIO (used only in sandbox test code) @@ -38,7 +38,7 @@ int sandbox_gpio_get_value(struct device *dev, unsigned int offset); * @param value value to set (0 for low, non-zero for high) * @return -1 on error, 0 if ok */ -int sandbox_gpio_set_value(struct device *dev, unsigned int offset, int value); +int sandbox_gpio_set_value(struct udevice *dev, unsigned int offset, int value); /** * Return the simulated direction of a GPIO (used only in sandbox test code) @@ -46,7 +46,7 @@ int sandbox_gpio_set_value(struct device *dev, unsigned int offset, int value); * @param gp GPIO number * @return -1 on error, 0 if GPIO is input, >0 if output */ -int sandbox_gpio_get_direction(struct device *dev, unsigned int offset); +int sandbox_gpio_get_direction(struct udevice *dev, unsigned int offset); /** * Set the simulated direction of a GPIO (used only in sandbox test code) @@ -55,7 +55,7 @@ int sandbox_gpio_get_direction(struct device *dev, unsigned int offset); * @param output 0 to set as input, 1 to set as output * @return -1 on error, 0 if ok */ -int sandbox_gpio_set_direction(struct device *dev, unsigned int offset, +int sandbox_gpio_set_direction(struct udevice *dev, unsigned int offset, int output); #endif diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 4c926ce70..25cbe62b1 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -19,6 +19,7 @@ #include <asm/arch/clock.h> #include <asm/arch/gpio.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> #include <asm/io.h> #include <asm/gpio.h> #include <i2c.h> @@ -214,3 +215,9 @@ int board_eth_init(bd_t *bis) return rv; } #endif /* CONFIG_DRIVER_TI_CPSW */ +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(1, 0, 0, -1, -1); +} +#endif diff --git a/board/abilis/tb100/Makefile b/board/abilis/tb100/Makefile new file mode 100644 index 000000000..4f273b322 --- /dev/null +++ b/board/abilis/tb100/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2014 Pierrick Hascoet, Abilis Systems +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += tb100.o diff --git a/board/abilis/tb100/tb100.c b/board/abilis/tb100/tb100.c new file mode 100644 index 000000000..ff3632f6c --- /dev/null +++ b/board/abilis/tb100/tb100.c @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2014 Pierrick Hascoet, Abilis Systems + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> + +void reset_cpu(ulong addr) +{ +#define CRM_SWRESET 0xff101044 + writel(0x1, (void *)CRM_SWRESET); +} + +int board_eth_init(bd_t *bis) +{ + if (designware_initialize(ETH0_BASE_ADDRESS, 0) >= 0) + return 1; + + return 0; +} diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c index 7e1b16ac4..9aa1d7aec 100644 --- a/board/ait/cam_enc_4xx/cam_enc_4xx.c +++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c @@ -8,8 +8,8 @@ */ #include <common.h> +#include <cli.h> #include <errno.h> -#include <hush.h> #include <linux/mtd/nand.h> #include <nand.h> #include <miiphy.h> @@ -777,7 +777,7 @@ static void ait_menu_read_env(char *name) sprintf(output, "%s old: %s value: ", name, getenv(name)); memset(cbuf, 0, CONFIG_SYS_CBSIZE); - readret = readline_into_buffer(output, cbuf, 0); + readret = cli_readline_into_buffer(output, cbuf, 0); if (readret >= 0) { ret = setenv(name, cbuf); diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c index dc78b7373..c1724bf03 100644 --- a/board/amcc/yucca/cmd_yucca.c +++ b/board/amcc/yucca/cmd_yucca.c @@ -8,6 +8,7 @@ */ #include <common.h> +#include <cli.h> #include <command.h> #include "yucca.h" #include <i2c.h> @@ -51,7 +52,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, do { printf("enter sys clock frequency 33 or 66 MHz or quit to abort\n"); - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "quit") == 0) return 0; @@ -74,7 +75,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n"); #endif } - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "quit") == 0) return 0; @@ -118,7 +119,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, printf("enter plb clock frequency 133, 166 MHz or quit to abort\n"); #endif - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "quit") == 0) return 0; @@ -142,7 +143,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, do { printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n"); - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "quit") == 0) return 0; @@ -163,13 +164,13 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, printf("Pci-X clk = %s MHz\n", pcixClock); do { - printf("\npress [y] to write I2C bootstrap \n"); - printf("or [n] to abort. \n"); - printf("Don't forget to set board switches \n"); - printf("according to your choice before re-starting \n"); - printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n"); + printf("\npress [y] to write I2C bootstrap\n"); + printf("or [n] to abort.\n"); + printf("Don't forget to set board switches\n"); + printf("according to your choice before re-starting\n"); + printf("(refer to 440spe_uboot_kit_um_1_01.pdf)\n"); - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (strcmp(console_buffer, "n") == 0) return 0; diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index b7e2efd2f..57881164c 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -16,6 +16,7 @@ #include <asm/arch/clk.h> #include <lcd.h> #include <atmel_lcdc.h> +#include <atmel_mci.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) #include <net.h> #endif @@ -217,6 +218,15 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bis) +{ + at91_mci_hw_init(); + + return atmel_mci_init((void *)ATMEL_BASE_MCI0); +} +#endif + int board_early_init_f(void) { at91_seriald_hw_init(); diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index 39f2dc647..92ed4e81d 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -17,6 +17,9 @@ #include <atmel_mci.h> #include <net.h> #include <netdev.h> +#include <spl.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/at91_wdt.h> DECLARE_GLOBAL_DATA_PTR; @@ -128,3 +131,87 @@ int board_mmc_init(bd_t *bis) return 0; } #endif + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +#ifdef CONFIG_SYS_USE_MMC + sama5d3_xplained_mci0_hw_init(); +#elif CONFIG_SYS_USE_NANDFLASH + sama5d3_xplained_nand_hw_init(); +#endif +} + +static void ddr2_conf(struct atmel_mpddr *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_ENRDM_ON | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_NDQS_DISABLED | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + /* + * As the DDR2-SDRAm device requires a refresh time is 7.8125us + * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks + */ + ddr2->rtr = 0x411; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddr ddr2; + + ddr2_conf(&ddr2); + + /* enable MPDDR clock */ + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(0x4, &pmc->scer); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_DDRCS, &ddr2); +} + +void at91_pmc_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(43) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + writel(0x3 << 8, &pmc->pllicpr); + + tmp = AT91_PMC_MCKR_MDIV_4 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index d9c05b07b..84294db85 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -19,13 +19,12 @@ #include <asm/imx-common/mxc_i2c.h> #include <asm/imx-common/sata.h> #include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/video.h> #include <mmc.h> #include <fsl_esdhc.h> #include <micrel.h> #include <miiphy.h> #include <netdev.h> -#include <linux/fb.h> -#include <ipu_pixfmt.h> #include <asm/arch/crm_regs.h> #include <asm/arch/mxc_hdmi.h> #include <i2c.h> @@ -331,7 +330,7 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_MXC_SPI iomux_v3_cfg_t const ecspi1_pads[] = { /* SS1 */ - MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -446,22 +445,6 @@ static iomux_v3_cfg_t const rgb_pads[] = { MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, }; -struct display_info_t { - int bus; - int addr; - int pixfmt; - int (*detect)(struct display_info_t const *dev); - void (*enable)(struct display_info_t const *dev); - struct fb_videomode mode; -}; - - -static int detect_hdmi(struct display_info_t const *dev) -{ - struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; - return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT; -} - static void do_enable_hdmi(struct display_info_t const *dev) { imx_enable_hdmi_phy(); @@ -492,7 +475,7 @@ static void enable_rgb(struct display_info_t const *dev) gpio_direction_output(RGB_BACKLIGHT_GP, 1); } -static struct display_info_t const displays[] = {{ +struct display_info_t const displays[] = {{ .bus = -1, .addr = 0, .pixfmt = IPU_PIX_FMT_RGB24, @@ -573,51 +556,7 @@ static struct display_info_t const displays[] = {{ .sync = 0, .vmode = FB_VMODE_NONINTERLACED } } }; - -int board_video_skip(void) -{ - int i; - int ret; - char const *panel = getenv("panel"); - if (!panel) { - for (i = 0; i < ARRAY_SIZE(displays); i++) { - struct display_info_t const *dev = displays+i; - if (dev->detect(dev)) { - panel = dev->mode.name; - printf("auto-detected panel %s\n", panel); - break; - } - } - if (!panel) { - panel = displays[0].mode.name; - printf("No panel detected: default to %s\n", panel); - i = 0; - } - } else { - for (i = 0; i < ARRAY_SIZE(displays); i++) { - if (!strcmp(panel, displays[i].mode.name)) - break; - } - } - if (i < ARRAY_SIZE(displays)) { - ret = ipuv3_fb_init(&displays[i].mode, 0, - displays[i].pixfmt); - if (!ret) { - displays[i].enable(displays+i); - printf("Display: %s (%ux%u)\n", - displays[i].mode.name, - displays[i].mode.xres, - displays[i].mode.yres); - } else { - printf("LCD %s cannot be configured: %d\n", - displays[i].mode.name, ret); - } - } else { - printf("unsupported panel %s\n", panel); - ret = -EINVAL; - } - return (0 != ret); -} +size_t display_count = ARRAY_SIZE(displays); static void setup_display(void) { diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds index 0984dfe6e..c8ab716ce 100644 --- a/board/compulab/cm_t335/u-boot.lds +++ b/board/compulab/cm_t335/u-boot.lds @@ -18,6 +18,7 @@ SECTIONS .text : { *(.__image_copy_start) + *(.vectors) CPUDIR/start.o (.text*) board/compulab/cm_t335/built-in.o (.text*) *(.text*) diff --git a/board/compulab/cm_t54/Makefile b/board/compulab/cm_t54/Makefile new file mode 100644 index 000000000..298ddd2d1 --- /dev/null +++ b/board/compulab/cm_t54/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2014 Compulab Ltd - http://compulab.co.il/ +# +# Author: Dmitry Lifshitz <lifshitz@compulab.co.il> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cm_t54.o +obj-$(CONFIG_SPL_BUILD) += mux.o spl.o diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c new file mode 100644 index 000000000..fadfddc07 --- /dev/null +++ b/board/compulab/cm_t54/cm_t54.c @@ -0,0 +1,262 @@ +/* + * Board functions for Compulab CM-T54 board + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Dmitry Lifshitz <lifshitz@compulab.co.il> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdt_support.h> +#include <usb.h> +#include <mmc.h> +#include <palmas.h> +#include <spl.h> + +#include <asm/gpio.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/clock.h> +#include <asm/arch/ehci.h> +#include <asm/ehci-omap.h> + +#include "../common/eeprom.h" + +#define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000) +#define DIE_ID_REG_OFFSET 0x200 + +DECLARE_GLOBAL_DATA_PTR; + +#if !defined(CONFIG_SPL_BUILD) +inline void set_muxconf_regs_essential(void){}; +#endif + +const struct omap_sysinfo sysinfo = { + "Board: CM-T54\n" +}; + +/* + * Routine: board_init + * Description: hardware init. + */ +int board_init(void) +{ + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); /* boot param addr */ + + return 0; +} + +/* + * Routine: cm_t54_palmas_regulator_set + * Description: select voltage and turn on/off Palmas PMIC regulator. + */ +static int cm_t54_palmas_regulator_set(u8 vreg, u8 vval, u8 creg, u8 cval) +{ + int err; + + /* Setup voltage */ + err = palmas_i2c_write_u8(TWL603X_CHIP_P1, vreg, vval); + if (err) { + printf("cm_t54: could not set regulator 0x%02x voltage : %d\n", + vreg, err); + return err; + } + + /* Turn on/off regulator */ + err = palmas_i2c_write_u8(TWL603X_CHIP_P1, creg, cval); + if (err) { + printf("cm_t54: could not turn on/off regulator 0x%02x : %d\n", + creg, err); + return err; + } + + return 0; +} + +/* + * Routine: mmc_get_env_part + * Description: setup environment storage device partition. + */ +#ifdef CONFIG_SYS_MMC_ENV_PART +uint mmc_get_env_part(struct mmc *mmc) +{ + u32 bootmode = gd->arch.omap_boot_params.omap_bootmode; + uint bootpart = CONFIG_SYS_MMC_ENV_PART; + + /* + * If booted from eMMC boot partition then force eMMC + * FIRST boot partition to be env storage + */ + if (bootmode == BOOT_DEVICE_MMC2_2) + bootpart = 1; + + return bootpart; +} +#endif + +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) +#define SB_T54_CD_GPIO 228 +#define SB_T54_WP_GPIO 229 + +int board_mmc_getcd(struct mmc *mmc) +{ + return !gpio_get_value(SB_T54_CD_GPIO); +} + +int board_mmc_init(bd_t *bis) +{ + int ret0, ret1; + + ret0 = omap_mmc_init(0, 0, 0, -1, SB_T54_WP_GPIO); + if (ret0) + printf("cm_t54: failed to initialize mmc0\n"); + + ret1 = omap_mmc_init(1, 0, 0, -1, -1); + if (ret1) + printf("cm_t54: failed to initialize mmc1\n"); + + if (ret0 && ret1) + return -1; + + return 0; +} +#endif + +#ifdef CONFIG_USB_HOST_ETHER + +void ft_board_setup(void *blob, bd_t *bd) +{ + uint8_t enetaddr[6]; + + /* MAC addr */ + if (eth_getenv_enetaddr("usbethaddr", enetaddr)) { + fdt_find_and_setprop(blob, "/smsc95xx@0", "mac-address", + enetaddr, 6, 1); + } +} + +static void generate_mac_addr(uint8_t *enetaddr) +{ + int reg; + + reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET; + + /* + * create a fake MAC address from the processor ID code. + * first byte is 0x02 to signify locally administered. + */ + enetaddr[0] = 0x02; + enetaddr[1] = readl(reg + 0x10) & 0xff; + enetaddr[2] = readl(reg + 0xC) & 0xff; + enetaddr[3] = readl(reg + 0x8) & 0xff; + enetaddr[4] = readl(reg) & 0xff; + enetaddr[5] = (readl(reg) >> 8) & 0xff; +} + +/* + * Routine: handle_mac_address + * Description: prepare MAC address for on-board Ethernet. + */ +static int handle_mac_address(void) +{ + uint8_t enetaddr[6]; + int ret; + + ret = eth_getenv_enetaddr("usbethaddr", enetaddr); + if (ret) + return 0; + + ret = cl_eeprom_read_mac_addr(enetaddr); + if (!ret || !is_valid_ether_addr(enetaddr)) + generate_mac_addr(enetaddr); + + if (!is_valid_ether_addr(enetaddr)) + return -1; + + return eth_setenv_enetaddr("usbethaddr", enetaddr); +} + +int board_eth_init(bd_t *bis) +{ + return handle_mac_address(); +} +#endif + +#ifdef CONFIG_USB_EHCI +static struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC, + .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC, +}; + +static void setup_host_clocks(bool enable) +{ + int usbhost_clk = OPTFCLKEN_HSIC60M_P3_CLK | + OPTFCLKEN_HSIC480M_P3_CLK | + OPTFCLKEN_HSIC60M_P2_CLK | + OPTFCLKEN_HSIC480M_P2_CLK | + OPTFCLKEN_UTMI_P3_CLK | + OPTFCLKEN_UTMI_P2_CLK; + + int usbtll_clk = OPTFCLKEN_USB_CH1_CLK_ENABLE | + OPTFCLKEN_USB_CH2_CLK_ENABLE; + + int usbhub_clk = CKOBUFFER_CLK_ENABLE_MASK; + + if (enable) { + /* Enable port 2 and 3 clocks*/ + setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, usbhost_clk); + /* Enable port 2 and 3 usb host ports tll clocks*/ + setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, usbtll_clk); + /* Request FREF_XTAL_CLK clock for HSIC USB Hub */ + setbits_le32((*ctrl)->control_ckobuffer, usbhub_clk); + } else { + clrbits_le32((*ctrl)->control_ckobuffer, usbhub_clk); + clrbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, usbtll_clk); + clrbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, usbhost_clk); + } +} + +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + int ret; + + /* VCC_3V3_ETH */ + cm_t54_palmas_regulator_set(SMPS9_VOLTAGE, SMPS_VOLT_3V3, SMPS9_CTRL, + SMPS_MODE_SLP_AUTO | SMPS_MODE_ACT_AUTO); + + setup_host_clocks(true); + + ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); + if (ret < 0) + printf("cm_t54: Failed to initialize ehci : %d\n", ret); + + return ret; +} + +int ehci_hcd_stop(void) +{ + int ret = omap_ehci_hcd_stop(); + + setup_host_clocks(false); + + cm_t54_palmas_regulator_set(SMPS9_VOLTAGE, SMPS_VOLT_OFF, + SMPS9_CTRL, SMPS_MODE_SLP_AUTO); + + return ret; +} + +void usb_hub_reset_devices(int port) +{ + /* The LAN9730 needs to be reset after the port power has been set. */ + if (port == 3) { + gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0); + udelay(10); + gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1); + } +} +#endif + diff --git a/board/compulab/cm_t54/mux.c b/board/compulab/cm_t54/mux.c new file mode 100644 index 000000000..da353831c --- /dev/null +++ b/board/compulab/cm_t54/mux.c @@ -0,0 +1,94 @@ +/* + * Pinmux configuration for Compulab CM-T54 board + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Dmitry Lifshitz <lifshitz@compulab.co.il> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CM_T54_MUX_DATA_H +#define _CM_T54_MUX_DATA_H + +#include <asm/arch/mux_omap5.h> +#include <asm/arch/sys_proto.h> + +const struct pad_conf_entry core_padconf_array_essential[] = { + /* MMC1 - SD CARD */ + {SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */ + {SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */ + {SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0 */ + {SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1 */ + {SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2 */ + {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3 */ + + /* SD CARD CD and WP GPIOs*/ + {TIMER5_PWM_EVT, (PTU | IEN | M6)}, /* GPIO8_228 */ + {TIMER6_PWM_EVT, (PTU | IEN | M6)}, /* GPIO8_229 */ + + /* MMC2 - eMMC */ + {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */ + {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */ + {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */ + {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */ + {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */ + {EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */ + {EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */ + {EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */ + {EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */ + {EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */ + + /* UART4 */ + {I2C5_SCL, (PTU | IEN | M2)}, /* UART4_RX */ + {I2C5_SDA, (M2)}, /* UART4_TX */ + + /* Led */ + {HSI2_CAFLAG, (PTU | M6)}, /* GPIO3_80 */ + + /* I2C1 */ + {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */ + {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */ + + /* USBB2, USBB3 */ + {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */ + {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */ + {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE */ + {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */ + + /* USB Hub and USB Eth reset GPIOs */ + {HSI2_CAREADY, (PTD | M6)}, /* GPIO3_76 */ + {HSI2_ACDATA, (PTD | M6)}, /* GPIO3_83 */ + + /* I2C4 */ + {I2C4_SCL, (PTU | IEN | M0)}, /* I2C4_SCL */ + {I2C4_SDA, (PTU | IEN | M0)}, /* I2C4_SDA */ +}; + +const struct pad_conf_entry wkup_padconf_array_essential[] = { + {SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */ + {SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */ + {SYS_32K, (IEN | M0)}, /* SYS_32K */ + + /* USB Hub clock */ + {FREF_CLK1_OUT, (PTD | IEN | M0)}, /* FREF_CLK1_OUT */ +}; + +/* + * Routine: set_muxconf_regs_essential + * Description: setup board pinmux configuration. + */ +void set_muxconf_regs_essential(void) +{ + do_set_mux((*ctrl)->control_padconf_core_base, + core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux((*ctrl)->control_padconf_wkup_base, + wkup_padconf_array_essential, + sizeof(wkup_padconf_array_essential) / + sizeof(struct pad_conf_entry)); +} + +#endif /* _CM_T54_MUX_DATA_H */ diff --git a/board/compulab/cm_t54/spl.c b/board/compulab/cm_t54/spl.c new file mode 100644 index 000000000..5c7b2c8e9 --- /dev/null +++ b/board/compulab/cm_t54/spl.c @@ -0,0 +1,66 @@ +/* + * SPL specific code for Compulab CM-T54 board + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Dmitry Lifshitz <lifshitz@compulab.co.il> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/emif.h> + +const struct emif_regs emif_regs_ddr3_532_mhz_cm_t54 = { +#if defined(CONFIG_DRAM_1G) || defined(CONFIG_DRAM_512M) + .sdram_config_init = 0x618522B2, + .sdram_config = 0x618522B2, +#elif defined(CONFIG_DRAM_2G) + .sdram_config_init = 0x618522BA, + .sdram_config = 0x618522BA, +#endif + .sdram_config2 = 0x0, + .ref_ctrl = 0x00001040, + .sdram_tim1 = 0xEEEF36F3, + .sdram_tim2 = 0x348F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x1007190B, + .temp_alert_config = 0x00000000, + + .emif_ddr_phy_ctlr_1_init = 0x0030400B, + .emif_ddr_phy_ctlr_1 = 0x0034400B, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00000000, + .emif_ddr_ext_phy_ctrl_3 = 0x00000000, + .emif_ddr_ext_phy_ctrl_4 = 0x00000000, + .emif_ddr_ext_phy_ctrl_5 = 0x4350D435, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x40000305, +}; + +const struct dmm_lisa_map_regs lisa_map_cm_t54 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + +#ifdef CONFIG_DRAM_2G + .dmm_lisa_map_2 = 0x80740300, +#elif defined(CONFIG_DRAM_1G) + .dmm_lisa_map_2 = 0x80640300, +#elif defined(CONFIG_DRAM_512M) + .dmm_lisa_map_2 = 0x80500100, +#endif + .dmm_lisa_map_3 = 0x00000000, + .is_ma_present = 0x1, +}; + +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) +{ + *regs = &emif_regs_ddr3_532_mhz_cm_t54; +} + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{ + *dmm_lisa_regs = &lisa_map_cm_t54; +} diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile index 6d7d06815..4044ac9d6 100644 --- a/board/compulab/common/Makefile +++ b/board/compulab/common/Makefile @@ -6,5 +6,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_SYS_I2C_OMAP34XX) += eeprom.o +obj-$(CONFIG_SYS_I2C) += eeprom.o obj-$(CONFIG_LCD) += omap3_display.o diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c index 5aa3dbd29..20fe3e196 100644 --- a/board/compulab/common/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -10,6 +10,11 @@ #include <common.h> #include <i2c.h> +#ifndef CONFIG_SYS_I2C_EEPROM_ADDR +# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#endif + #define EEPROM_LAYOUT_VER_OFFSET 44 #define BOARD_SERIAL_OFFSET 20 #define BOARD_SERIAL_OFFSET_LEGACY 8 diff --git a/board/compulab/common/eeprom.h b/board/compulab/common/eeprom.h index e87162930..85d5bf03d 100644 --- a/board/compulab/common/eeprom.h +++ b/board/compulab/common/eeprom.h @@ -10,7 +10,7 @@ #ifndef _EEPROM_ #define _EEPROM_ -#ifdef CONFIG_SYS_I2C_OMAP34XX +#ifdef CONFIG_SYS_I2C int cl_eeprom_read_mac_addr(uchar *buf); u32 cl_eeprom_get_board_rev(void); #else diff --git a/board/eltec/elppc/misc.c b/board/eltec/elppc/misc.c index d80eaba2d..2acf80047 100644 --- a/board/eltec/elppc/misc.c +++ b/board/eltec/elppc/misc.c @@ -7,6 +7,7 @@ /* includes */ #include <common.h> +#include <cli.h> #include <linux/ctype.h> #include <pci.h> #include <net.h> @@ -113,7 +114,7 @@ int misc_init_r (void) printf ("Press key:\n <c> to copy current revision info to nvram.\n"); printf (" <r> to reenter revision info.\n"); printf ("=> "); - if (0 != readline (NULL)) { + if (0 != cli_readline(NULL)) { switch ((char) toupper (console_buffer[0])) { case 'C': copyNv = 1; @@ -130,7 +131,7 @@ int misc_init_r (void) memcpy (buf, &eerev.revision[0][0], 14); /* save all revision info */ printf ("Enter revision number (0-9): %c ", eerev.revision[0][0]); - if (0 != readline (NULL)) { + if (0 != cli_readline(NULL)) { eerev.revision[0][0] = (char) toupper (console_buffer[0]); memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */ @@ -138,14 +139,14 @@ int misc_init_r (void) printf ("Enter revision character (A-Z): %c ", eerev.revision[0][1]); - if (1 == readline (NULL)) { + if (1 == cli_readline(NULL)) { eerev.revision[0][1] = (char) toupper (console_buffer[0]); } printf ("Enter board name (V-XXXX-XXXX): %s ", (char *) &eerev.board); - if (11 == readline (NULL)) { + if (11 == cli_readline(NULL)) { for (i = 0; i < 11; i++) eerev.board[i] = (char) toupper (console_buffer[i]); @@ -153,14 +154,14 @@ int misc_init_r (void) } printf ("Enter serial number: %s ", (char *) &eerev.serial); - if (6 == readline (NULL)) { + if (6 == cli_readline(NULL)) { for (i = 0; i < 6; i++) eerev.serial[i] = console_buffer[i]; eerev.serial[6] = '\0'; } printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", eerev.etheraddr[0], eerev.etheraddr[1], eerev.etheraddr[2], eerev.etheraddr[3], eerev.etheraddr[4], eerev.etheraddr[5]); - if (12 == readline (NULL)) { + if (12 == cli_readline(NULL)) { for (i = 0; i < 12; i += 2) eerev.etheraddr[i >> 1] = (char) (16 * @@ -175,7 +176,7 @@ int misc_init_r (void) l = strlen ((char *) &eerev.text); printf ("Add to text section (max 64 chr): %s ", (char *) &eerev.text); - if (0 != readline (NULL)) { + if (0 != cli_readline(NULL)) { for (i = l; i < 63; i++) eerev.text[i] = console_buffer[i - l]; eerev.text[63] = '\0'; diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c index f3f564ffe..5781b2a54 100644 --- a/board/eltec/mhpc/mhpc.c +++ b/board/eltec/mhpc/mhpc.c @@ -14,6 +14,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <cli.h> #include <linux/ctype.h> #include <commproc.h> #include "mpc8xx.h" @@ -146,21 +147,21 @@ int misc_init_r (void) if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) { printf ("Enter revision number (0-9): %c ", mhpcRevInfo.revision[0]); - if (0 != readline (NULL)) { + if (0 != cli_readline(NULL)) { mhpcRevInfo.revision[0] = (char) toupper (console_buffer[0]); } printf ("Enter revision character (A-Z): %c ", mhpcRevInfo.revision[1]); - if (1 == readline (NULL)) { + if (1 == cli_readline(NULL)) { mhpcRevInfo.revision[1] = (char) toupper (console_buffer[0]); } printf ("Enter board name (V-XXXX-XXXX): %s ", (char *) &mhpcRevInfo.board); - if (11 == readline (NULL)) { + if (11 == cli_readline(NULL)) { for (i = 0; i < 11; i++) { mhpcRevInfo.board[i] = (char) toupper (console_buffer[i]); @@ -177,7 +178,7 @@ int misc_init_r (void) do { printf ("\nEnter sensor number (0-255): %d ", (int) mhpcRevInfo.sensor); - if (0 != readline (NULL)) { + if (0 != cli_readline(NULL)) { mhpcRevInfo.sensor = (unsigned char) simple_strtoul (console_buffer, NULL, @@ -187,7 +188,7 @@ int misc_init_r (void) printf ("Enter serial number: %s ", (char *) &mhpcRevInfo.serial); - if (6 == readline (NULL)) { + if (6 == cli_readline(NULL)) { for (i = 0; i < 6; i++) { mhpcRevInfo.serial[i] = console_buffer[i]; } @@ -195,7 +196,7 @@ int misc_init_r (void) } printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]); - if (12 == readline (NULL)) { + if (12 == cli_readline(NULL)) { for (i = 0; i < 12; i += 2) { mhpcRevInfo.etheraddr[i >> 1] = (char) (16 * diff --git a/board/embest/mx6boards/Makefile b/board/embest/mx6boards/Makefile new file mode 100644 index 000000000..467fb5000 --- /dev/null +++ b/board/embest/mx6boards/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6boards.o diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c new file mode 100644 index 000000000..d06b57d1e --- /dev/null +++ b/board/embest/mx6boards/mx6boards.c @@ -0,0 +1,601 @@ +/* + * Copyright (C) 2014 Eukréa Electromatique + * Author: Eric Bénard <eric@eukrea.com> + * Fabio Estevam <fabio.estevam@freescale.com> + * Jon Nettleton <jon.nettleton@gmail.com> + * + * based on sabresd.c which is : + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * and on hummingboard.c which is : + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/video.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/crm_regs.h> +#include <linux/fb.h> +#include <ipu_pixfmt.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +static int board_type = -1; +#define BOARD_IS_MARSBOARD 0 +#define BOARD_IS_RIOTBOARD 1 + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* GPIO16 -> AR8035 25MHz */ + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + /* AR8035 PHY Reset */ + MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + /* AR8035 PHY Interrupt */ + MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + /* Reset AR8035 PHY */ + gpio_direction_output(IMX_GPIO_NR(3, 31) , 0); + mdelay(2); + gpio_set_value(IMX_GPIO_NR(3, 31), 1); +} + +int mx6_rgmii_rework(struct phy_device *phydev) +{ + /* from linux/arch/arm/mach-imx/mach-imx6q.c : + * Ar803x phy SmartEEE feature cause link status generates glitch, + * which cause ethernet link down/up issue, so disable SmartEEE + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +iomux_v3_cfg_t const riotboard_usdhc3_pads[] = { + MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ + MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* eMMC RST */ + MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) +#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + if (board_type == BOARD_IS_RIOTBOARD) + ret = !gpio_get_value(USDHC3_CD_GPIO); + else if (board_type == BOARD_IS_MARSBOARD) + ret = 1; /* eMMC/uSDHC3 is always present */ + break; + case USDHC4_BASE_ADDR: + ret = 1; /* eMMC/uSDHC4 is always present */ + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + s32 status = 0; + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * ** RiOTboard : + * mmc0 SDCard slot (bottom) + * mmc1 uSDCard slot (top) + * mmc2 eMMC + * ** MarSBoard : + * mmc0 uSDCard slot (bottom) + * mmc1 eMMC + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + usdhc_cfg[0].max_bus_width = 4; + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + if (board_type == BOARD_IS_RIOTBOARD) { + imx_iomux_v3_setup_multiple_pads( + riotboard_usdhc3_pads, + ARRAY_SIZE(riotboard_usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + gpio_direction_output(IMX_GPIO_NR(7, 8) , 0); + udelay(250); + gpio_set_value(IMX_GPIO_NR(7, 8), 1); + } + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + usdhc_cfg[2].max_bus_width = 4; + gpio_direction_output(IMX_GPIO_NR(6, 8) , 0); + udelay(250); + gpio_set_value(IMX_GPIO_NR(6, 8), 1); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + i + 1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } + + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + } + + return status; +} +#endif + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); +} +#endif + +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(5, 26) + } +}; + +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 13) + } +}; + +struct i2c_pads_info i2c_pad_info3 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(1, 6) + } +}; + +iomux_v3_cfg_t const tft_pads_riot[] = { + /* LCD_PWR_EN */ + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* TOUCH_INT */ + MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED_PWR_EN */ + MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* BL LEVEL */ + MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const tft_pads_mars[] = { + /* LCD_PWR_EN */ + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* TOUCH_INT */ + MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED_PWR_EN */ + MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* BL LEVEL (PWM4) */ + MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#if defined(CONFIG_VIDEO_IPUV3) + +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) + IOMUXC_BASE_ADDR; + setbits_le32(&iomux->gpr[2], + IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT); + /* set backlight level to ON */ + if (board_type == BOARD_IS_RIOTBOARD) + gpio_direction_output(IMX_GPIO_NR(1, 18) , 1); + else if (board_type == BOARD_IS_MARSBOARD) + gpio_direction_output(IMX_GPIO_NR(2, 10) , 1); +} + +static void disable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* set backlight level to OFF */ + if (board_type == BOARD_IS_RIOTBOARD) + gpio_direction_output(IMX_GPIO_NR(1, 18) , 0); + else if (board_type == BOARD_IS_MARSBOARD) + gpio_direction_output(IMX_GPIO_NR(2, 10) , 0); + + clrbits_le32(&iomux->gpr[2], + IOMUXC_GPR2_LVDS_CH0_MODE_MASK); +} + +static void do_enable_hdmi(struct display_info_t const *dev) +{ + disable_lvds(dev); + imx_enable_hdmi_phy(); +} + +static int detect_i2c(struct display_info_t const *dev) +{ + return (0 == i2c_set_bus_num(dev->bus)) && + (0 == i2c_probe(dev->addr)); +} + +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 2, + .addr = 0x1, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "LCD8000-97C", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 100, + .right_margin = 200, + .upper_margin = 10, + .lower_margin = 20, + .hsync_len = 20, + .vsync_len = 8, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + enable_ipu_clock(); + imx_setup_hdmi(); + + /* Turn on LDB0, IPU,IPU DI0 clocks */ + setbits_le32(&mxc_ccm->CCGR3, + MXC_CCM_CCGR3_LDB_DI0_MASK); + + /* set LDB0 clk select to 011/011 */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK, + (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)); + + setbits_le32(&mxc_ccm->cscmr2, + MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); + + setbits_le32(&mxc_ccm->chsccdr, + (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + clrsetbits_le32(&iomux->gpr[3], + IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | + IOMUXC_GPR3_HDMI_MUX_CTL_MASK, + IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); + + return cpu_eth_init(bis); +} + +int board_early_init_f(void) +{ + u32 cputype = cpu_type(get_cpu_rev()); + + switch (cputype) { + case MXC_CPU_MX6SOLO: + board_type = BOARD_IS_RIOTBOARD; + break; + case MXC_CPU_MX6D: + board_type = BOARD_IS_MARSBOARD; + break; + } + + setup_iomux_uart(); + + if (board_type == BOARD_IS_RIOTBOARD) + imx_iomux_v3_setup_multiple_pads( + tft_pads_riot, ARRAY_SIZE(tft_pads_riot)); + else if (board_type == BOARD_IS_MARSBOARD) + imx_iomux_v3_setup_multiple_pads( + tft_pads_mars, ARRAY_SIZE(tft_pads_mars)); +#if defined(CONFIG_VIDEO_IPUV3) + /* power ON LCD */ + gpio_direction_output(IMX_GPIO_NR(1, 29) , 1); + /* touch interrupt is an input */ + gpio_direction_input(IMX_GPIO_NR(6, 14)); + /* power ON backlight */ + gpio_direction_output(IMX_GPIO_NR(6, 15) , 1); + /* set backlight level to off */ + if (board_type == BOARD_IS_RIOTBOARD) + gpio_direction_output(IMX_GPIO_NR(1, 18) , 0); + else if (board_type == BOARD_IS_MARSBOARD) + gpio_direction_output(IMX_GPIO_NR(2, 10) , 0); + setup_display(); +#endif + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + /* i2c2 : HDMI EDID */ + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + /* i2c3 : LVDS, Expansion connector */ + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode riotboard_boot_modes[] = { + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {NULL, 0}, +}; +static const struct boot_mode marsboard_boot_modes[] = { + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + if (board_type == BOARD_IS_RIOTBOARD) + add_board_boot_modes(riotboard_boot_modes); + else if (board_type == BOARD_IS_RIOTBOARD) + add_board_boot_modes(marsboard_boot_modes); +#endif + + return 0; +} + +int checkboard(void) +{ + puts("Board: "); + if (board_type == BOARD_IS_MARSBOARD) + puts("MarSBoard\n"); + else if (board_type == BOARD_IS_RIOTBOARD) + puts("RIoTboard\n"); + else + printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev())); + + return 0; +} diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds index 6da1d4b5f..61b83bfc6 100644 --- a/board/freescale/mx31ads/u-boot.lds +++ b/board/freescale/mx31ads/u-boot.lds @@ -22,6 +22,7 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ + * (.vectors) arch/arm/cpu/arm1136/start.o (.text*) board/freescale/mx31ads/built-in.o (.text*) arch/arm/lib/built-in.o (.text*) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index d7d932eeb..3e314daec 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -14,14 +14,13 @@ #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> #include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/video.h> #include <mmc.h> #include <fsl_esdhc.h> #include <miiphy.h> #include <netdev.h> #include <asm/arch/mxc_hdmi.h> #include <asm/arch/crm_regs.h> -#include <linux/fb.h> -#include <ipu_pixfmt.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -265,22 +264,6 @@ int board_phy_config(struct phy_device *phydev) } #if defined(CONFIG_VIDEO_IPUV3) -struct display_info_t { - int bus; - int addr; - int pixfmt; - int (*detect)(struct display_info_t const *dev); - void (*enable)(struct display_info_t const *dev); - struct fb_videomode mode; -}; - -static int detect_hdmi(struct display_info_t const *dev) -{ - struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; - return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT; -} - - static void disable_lvds(struct display_info_t const *dev) { struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -309,7 +292,7 @@ static void enable_lvds(struct display_info_t const *dev) writel(reg, &iomux->gpr[2]); } -static struct display_info_t const displays[] = {{ +struct display_info_t const displays[] = {{ .bus = -1, .addr = 0, .pixfmt = IPU_PIX_FMT_RGB666, @@ -350,51 +333,7 @@ static struct display_info_t const displays[] = {{ .sync = FB_SYNC_EXT, .vmode = FB_VMODE_NONINTERLACED } } }; - -int board_video_skip(void) -{ - int i; - int ret; - char const *panel = getenv("panel"); - if (!panel) { - for (i = 0; i < ARRAY_SIZE(displays); i++) { - struct display_info_t const *dev = displays+i; - if (dev->detect && dev->detect(dev)) { - panel = dev->mode.name; - printf("auto-detected panel %s\n", panel); - break; - } - } - if (!panel) { - panel = displays[0].mode.name; - printf("No panel detected: default to %s\n", panel); - i = 0; - } - } else { - for (i = 0; i < ARRAY_SIZE(displays); i++) { - if (!strcmp(panel, displays[i].mode.name)) - break; - } - } - if (i < ARRAY_SIZE(displays)) { - ret = ipuv3_fb_init(&displays[i].mode, 0, - displays[i].pixfmt); - if (!ret) { - displays[i].enable(displays+i); - printf("Display: %s (%ux%u)\n", - displays[i].mode.name, - displays[i].mode.xres, - displays[i].mode.yres); - } else - printf("LCD %s cannot be configured: %d\n", - displays[i].mode.name, ret); - } else { - printf("unsupported panel %s\n", panel); - return -EINVAL; - } - - return 0; -} +size_t display_count = ARRAY_SIZE(displays); static void setup_display(void) { diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index aadad3266..d2b64cc35 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -34,6 +34,9 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + #define ETH_PHY_RESET IMX_GPIO_NR(4, 21) int dram_init(void) @@ -71,6 +74,20 @@ static iomux_v3_cfg_t const fec_pads[] = { MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +#ifdef CONFIG_MXC_SPI +static iomux_v3_cfg_t ecspi1_pads[] = { + MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); +} +#endif + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); @@ -132,6 +149,9 @@ static int setup_fec(void) int board_early_init_f(void) { setup_iomux_uart(); +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif return 0; } diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 4ee74c019..d64d3aa87 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -217,7 +217,8 @@ void ddr_ctrl_init(void) &ddrmr->cr[139]); writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | - DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]); + DDRMC_CR154_PAD_ZQ_MODE(1) | + DDRMC_CR154_DDR_SEL_PAD_CONTR(3), &ddrmr->cr[154]); writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2), &ddrmr->cr[155]); writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]); diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index c130e2c1e..031367d97 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -12,6 +12,7 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/iomux.h> #include <asm/arch/mx6-pins.h> +#include <asm/arch/mxc_hdmi.h> #include <asm/arch/crm_regs.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> @@ -19,6 +20,7 @@ #include <asm/imx-common/mxc_i2c.h> #include <asm/imx-common/boot_mode.h> #include <asm/imx-common/sata.h> +#include <asm/imx-common/video.h> #include <jffs2/load_kernel.h> #include <hwconfig.h> #include <i2c.h> @@ -30,8 +32,8 @@ #include <mtd_node.h> #include <netdev.h> #include <power/pmic.h> +#include <power/ltc3676_pmic.h> #include <power/pfuze100_pmic.h> -#include <i2c.h> #include <fdt_support.h> #include <jffs2/load_kernel.h> #include <spi_flash.h> @@ -369,6 +371,134 @@ int board_eth_init(bd_t *bis) return 0; } +#if defined(CONFIG_VIDEO_IPUV3) + +static void enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +static int detect_i2c(struct display_info_t const *dev) +{ + return i2c_set_bus_num(dev->bus) == 0 && + i2c_probe(dev->addr) == 0; +} + +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) + IOMUXC_BASE_ADDR; + + /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */ + u32 reg = readl(&iomux->gpr[2]); + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; + writel(reg, &iomux->gpr[2]); + + /* Enable Backlight */ + imx_iomux_v3_setup_pad(MX6_PAD_SD1_CMD__GPIO1_IO18 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 18), 1); +} + +struct display_info_t const displays[] = {{ + /* HDMI Output */ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */ + .bus = 2, + .addr = 0x4, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "Hannstar-XGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + enable_ipu_clock(); + imx_setup_hdmi(); + /* Turn on LDB0,IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); + + /* Backlight CABEN on LVDS connector */ + imx_iomux_v3_setup_pad(MX6_PAD_SD2_CLK__GPIO1_IO10 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 10), 0); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + /* read ventana EEPROM, check for validity, and return baseboard type */ static int read_eeprom(void) @@ -733,6 +863,62 @@ struct ventana gpio_cfg[] = { }, }; +/* setup board specific PMIC */ +int power_init_board(void) +{ + struct pmic *p; + u32 reg; + + /* configure PFUZE100 PMIC */ + if (board_type == GW54xx || board_type == GW54proto) { + power_pfuze100_init(I2C_PMIC); + p = pmic_get("PFUZE100_PMIC"); + if (p && !pmic_probe(p)) { + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Set VGEN1 to 1.5V and enable */ + pmic_reg_read(p, PFUZE100_VGEN1VOL, ®); + reg &= ~(LDO_VOL_MASK); + reg |= (LDOA_1_50V | LDO_EN); + pmic_reg_write(p, PFUZE100_VGEN1VOL, reg); + + /* Set SWBST to 5.0V and enable */ + pmic_reg_read(p, PFUZE100_SWBSTCON1, ®); + reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); + reg |= (SWBST_5_00V | SWBST_MODE_AUTO); + pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); + } + } + + /* configure LTC3676 PMIC */ + else { + power_ltc3676_init(I2C_PMIC); + p = pmic_get("LTC3676_PMIC"); + if (p && !pmic_probe(p)) { + puts("PMIC: LTC3676\n"); + /* set board-specific scalar to 1225mV for IMX6Q@1GHz */ + if (is_cpu_type(MXC_CPU_MX6Q)) { + /* mask PGOOD during SW1 transition */ + reg = 0x1d | LTC3676_PGOOD_MASK; + pmic_reg_write(p, LTC3676_DVB1B, reg); + /* set SW1 (VDD_SOC) to 1259mV */ + reg = 0x1d; + pmic_reg_write(p, LTC3676_DVB1A, reg); + + /* mask PGOOD during SW3 transition */ + reg = 0x1d | LTC3676_PGOOD_MASK; + pmic_reg_write(p, LTC3676_DVB3B, reg); + /*set SW3 (VDD_ARM) to 1259mV */ + reg = 0x1d; + pmic_reg_write(p, LTC3676_DVB3A, reg); + } + } + } + + return 0; +} + /* setup GPIO pinmux and default configuration per baseboard */ static void setup_board_gpio(int board) { @@ -888,6 +1074,9 @@ int board_early_init_f(void) setup_iomux_uart(); gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */ +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif return 0; } @@ -1076,28 +1265,6 @@ int misc_init_r(void) setenv("serial#", str); } - /* configure PFUZE100 PMIC (not used on all Ventana baseboards) */ - if ((board_type == GW54xx || board_type == GW54proto) && - !pmic_init(I2C_PMIC)) { - struct pmic *p = pmic_get("PFUZE100_PMIC"); - u32 reg; - if (p && !pmic_probe(p)) { - pmic_reg_read(p, PFUZE100_DEVICEID, ®); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); - - /* Set VGEN1 to 1.5V and enable */ - pmic_reg_read(p, PFUZE100_VGEN1VOL, ®); - reg &= ~(LDO_VOL_MASK); - reg |= (LDOA_1_50V | LDO_EN); - pmic_reg_write(p, PFUZE100_VGEN1VOL, reg); - - /* Set SWBST to 5.0V and enable */ - pmic_reg_read(p, PFUZE100_SWBSTCON1, ®); - reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); - reg |= (SWBST_5_00V | SWBST_MODE_AUTO); - pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); - } - } /* setup baseboard specific GPIO pinmux and config */ setup_board_gpio(board_type); @@ -1243,7 +1410,7 @@ void ft_board_setup(void *blob, bd_t *bd) /* board serial number */ fdt_setprop(blob, 0, "system-serial", getenv("serial#"), - strlen(getenv("serial#") + 1)); + strlen(getenv("serial#")) + 1); /* board (model contains model from device-tree) */ fdt_setprop(blob, 0, "board", info->model, diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h index d310bfd99..434b60454 100644 --- a/board/gateworks/gw_ventana/ventana_eeprom.h +++ b/board/gateworks/gw_ventana/ventana_eeprom.h @@ -16,16 +16,16 @@ struct ventana_board_info { u8 mfgdate[4]; /* 0x20: MFG date (read only) */ u8 res2[7]; /* 0x24 */ /* sdram config */ - u8 sdram_size; /* 0x2B: enum (512,1024,2048) MB */ - u8 sdram_speed; /* 0x2C: enum (100,133,166,200,267,333,400) MHz */ - u8 sdram_width; /* 0x2D: enum (32,64) bit */ + u8 sdram_size; /* 0x2B: (16 << n) MB */ + u8 sdram_speed; /* 0x2C: (33.333 * n) MHz */ + u8 sdram_width; /* 0x2D: (8 << n) bit */ /* cpu config */ - u8 cpu_speed; /* 0x2E: enum (800,1000,1200) MHz */ - u8 cpu_type; /* 0x2F: enum (imx6q,imx6d,imx6dl,imx6s) */ + u8 cpu_speed; /* 0x2E: (33.333 * n) MHz */ + u8 cpu_type; /* 0x2F: 7=imx6q, 8=imx6dl */ u8 model[16]; /* 0x30: model string */ /* FLASH config */ - u8 nand_flash_size; /* 0x40: enum (4,8,16,32,64,128) MB */ - u8 spi_flash_size; /* 0x41: enum (4,8,16,32,64,128) MB */ + u8 nand_flash_size; /* 0x40: (8 << (n-1)) MB */ + u8 spi_flash_size; /* 0x41: (4 << (n-1)) MB */ /* Config1: SoC Peripherals */ u8 config[8]; /* 0x42: loading options */ diff --git a/board/gumstix/duovero/Makefile b/board/gumstix/duovero/Makefile new file mode 100644 index 000000000..f738c58d0 --- /dev/null +++ b/board/gumstix/duovero/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := duovero.o diff --git a/board/gumstix/duovero/duovero.c b/board/gumstix/duovero/duovero.c new file mode 100644 index 000000000..81d6c8221 --- /dev/null +++ b/board/gumstix/duovero/duovero.c @@ -0,0 +1,264 @@ +/* + * (C) Copyright 2013 + * Gumstix Inc. <www.gumstix.com> + * Maintainer: Ash Charles <ash@gumstix.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <netdev.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> +#include <twl6030.h> +#include <asm/emif.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/gpio.h> + +#include "duovero_mux_data.h" + +#define WIFI_EN 43 + +#if defined(CONFIG_CMD_NET) +#define SMSC_NRESET 45 +static void setup_net_chip(void); +#endif + +#ifdef CONFIG_USB_EHCI +#include <usb.h> +#include <asm/arch/ehci.h> +#include <asm/ehci-omap.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +const struct omap_sysinfo sysinfo = { + "Board: duovero\n" +}; + +struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000; + +/** + * @brief board_init + * + * @return 0 + */ +int board_init(void) +{ + gpmc_init(); + + gd->bd->bi_arch_number = MACH_TYPE_OMAP4_DUOVERO; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +/** + * @brief misc_init_r - Configure board specific configurations + * such as power configurations, ethernet initialization as phase2 of + * boot sequence + * + * @return 0 + */ +int misc_init_r(void) +{ + int ret = 0; + u8 val; + + /* wifi setup: first enable 32Khz clock from 6030 pmic */ + val = 0xe1; + ret = i2c_write(TWL6030_CHIP_PM, 0xbe, 1, &val, 1); + if (ret) + printf("Failed to enable 32Khz clock to wifi module\n"); + + /* then setup WIFI_EN as an output pin and send reset pulse */ + if (!gpio_request(WIFI_EN, "")) { + gpio_direction_output(WIFI_EN, 0); + gpio_set_value(WIFI_EN, 1); + udelay(1); + gpio_set_value(WIFI_EN, 0); + udelay(1); + gpio_set_value(WIFI_EN, 1); + } + +#if defined(CONFIG_CMD_NET) + setup_net_chip(); +#endif + return 0; +} + +void set_muxconf_regs_essential(void) +{ + do_set_mux((*ctrl)->control_padconf_core_base, + core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux((*ctrl)->control_padconf_wkup_base, + wkup_padconf_array_essential, + sizeof(wkup_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux((*ctrl)->control_padconf_core_base, + core_padconf_array_non_essential, + sizeof(core_padconf_array_non_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux((*ctrl)->control_padconf_wkup_base, + wkup_padconf_array_non_essential, + sizeof(wkup_padconf_array_non_essential) / + sizeof(struct pad_conf_entry)); +} + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0, 0, 0, -1, -1); +} +#endif + + +#if defined(CONFIG_CMD_NET) + +#define GPMC_SIZE_16M 0xF +#define GPMC_BASEADDR_MASK 0x3F +#define GPMC_CS_ENABLE 0x1 + +static void enable_gpmc_net_config(const u32 *gpmc_config, struct gpmc_cs *cs, + u32 base, u32 size) +{ + writel(0, &cs->config7); + sdelay(1000); + /* Delay for settling */ + writel(gpmc_config[0], &cs->config1); + writel(gpmc_config[1], &cs->config2); + writel(gpmc_config[2], &cs->config3); + writel(gpmc_config[3], &cs->config4); + writel(gpmc_config[4], &cs->config5); + writel(gpmc_config[5], &cs->config6); + + /* + * Enable the config. size is the CS size and goes in + * bits 11:8. We set bit 6 to enable this CS and the base + * address goes into bits 5:0. + */ + writel((size << 8) | (GPMC_CS_ENABLE << 6) | + ((base >> 24) & GPMC_BASEADDR_MASK), + &cs->config7); + + sdelay(2000); +} + +/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */ +#define NET_LAN9221_GPMC_CONFIG1 0x2a001203 +#define NET_LAN9221_GPMC_CONFIG2 0x000a0a02 +#define NET_LAN9221_GPMC_CONFIG3 0x00020200 +#define NET_LAN9221_GPMC_CONFIG4 0x0a030a03 +#define NET_LAN9221_GPMC_CONFIG5 0x000a0a0a +#define NET_LAN9221_GPMC_CONFIG6 0x8a070707 +#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c + +/* GPMC definitions for LAN9221 chips on expansion boards */ +static const u32 gpmc_lan_config[] = { + NET_LAN9221_GPMC_CONFIG1, + NET_LAN9221_GPMC_CONFIG2, + NET_LAN9221_GPMC_CONFIG3, + NET_LAN9221_GPMC_CONFIG4, + NET_LAN9221_GPMC_CONFIG5, + NET_LAN9221_GPMC_CONFIG6, + /*CONFIG7- computed as params */ +}; + +/* + * Routine: setup_net_chip + * Description: Setting up the configuration GPMC registers specific to the + * Ethernet hardware. + */ +static void setup_net_chip(void) +{ + enable_gpmc_net_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, + GPMC_SIZE_16M); + + /* Make GPIO SMSC_NRESET as output pin and send reset pulse */ + if (!gpio_request(SMSC_NRESET, "")) { + gpio_direction_output(SMSC_NRESET, 0); + gpio_set_value(SMSC_NRESET, 1); + udelay(1); + gpio_set_value(SMSC_NRESET, 0); + udelay(1); + gpio_set_value(SMSC_NRESET, 1); + } +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} + +#ifdef CONFIG_USB_EHCI + +static struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, +}; + +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + int ret; + unsigned int utmi_clk; + u32 auxclk, altclksrc; + + /* Now we can enable our port clocks */ + utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL); + utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK; + setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk); + + auxclk = readl(&scrm->auxclk3); + /* Select sys_clk */ + auxclk &= ~AUXCLK_SRCSELECT_MASK; + auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT; + /* Set the divisor to 2 */ + auxclk &= ~AUXCLK_CLKDIV_MASK; + auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT; + /* Request auxilary clock #3 */ + auxclk |= AUXCLK_ENABLE_MASK; + writel(auxclk, &scrm->auxclk3); + + altclksrc = readl(&scrm->altclksrc); + + /* Activate alternate system clock supplier */ + altclksrc &= ~ALTCLKSRC_MODE_MASK; + altclksrc |= ALTCLKSRC_MODE_ACTIVE; + + /* enable clocks */ + altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK; + + writel(altclksrc, &scrm->altclksrc); + + ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); + if (ret < 0) + return ret; + + return 0; +} + +int ehci_hcd_stop(int index) +{ + return omap_ehci_hcd_stop(); +} +#endif + +/* + * get_board_rev() - get board revision + */ +u32 get_board_rev(void) +{ + return 0x20; +} diff --git a/board/gumstix/duovero/duovero_mux_data.h b/board/gumstix/duovero/duovero_mux_data.h new file mode 100644 index 000000000..1be247b87 --- /dev/null +++ b/board/gumstix/duovero/duovero_mux_data.h @@ -0,0 +1,199 @@ +/* + * (C) Copyright 2012 + * Gumstix Incorporated, <www.gumstix.com> + * Maintainer: Ash Charles <ash@gumstix.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _DUOVERO_MUX_DATA_H_ +#define _DUOVERO_MUX_DATA_H_ + +#include <asm/arch/mux_omap4.h> + +const struct pad_conf_entry core_padconf_array_essential[] = { + {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ + {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ + {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ + {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ + {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ + {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ + {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ + {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ + {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ + {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ + {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ + {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ + {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ + {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ + {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ + {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ + {UART3_RX_IRRX, (PTU | IEN | M0)}, /* uart3_rx */ + {UART3_TX_IRTX, (M0)} /* uart3_tx */ +}; + +const struct pad_conf_entry wkup_padconf_array_essential[] = { + {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ + {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ + {PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ +}; + +const struct pad_conf_entry core_padconf_array_non_essential[] = { + {GPMC_AD0, (PTU | IEN | M0)}, /* gpmc_ad0 */ + {GPMC_AD1, (PTU | IEN | M0)}, /* gpmc_ad1 */ + {GPMC_AD2, (PTU | IEN | M0)}, /* gpmc_ad2 */ + {GPMC_AD3, (PTU | IEN | M0)}, /* gpmc_ad3 */ + {GPMC_AD4, (PTU | IEN | M0)}, /* gpmc_ad4 */ + {GPMC_AD5, (PTU | IEN | M0)}, /* gpmc_ad5 */ + {GPMC_AD6, (PTU | IEN | M0)}, /* gpmc_ad6 */ + {GPMC_AD7, (PTU | IEN | M0)}, /* gpmc_ad7 */ + {GPMC_AD8, (PTU | IEN | M0)}, /* gpmc_ad8 */ + {GPMC_AD9, (PTU | IEN | M0)}, /* gpmc_ad9 */ + {GPMC_AD10, (PTU | IEN | M0)}, /* gpmc_ad10 */ + {GPMC_AD11, (PTU | IEN | M0)}, /* gpmc_ad11 */ + {GPMC_AD12, (PTU | IEN | M0)}, /* gpmc_ad12 */ + {GPMC_AD13, (PTU | IEN | M0)}, /* gpmc_ad13 */ + {GPMC_AD14, (PTU | IEN | M0)}, /* gpmc_ad14 */ + {GPMC_AD15, (PTU | IEN | M0)}, /* gpmc_ad15 */ + {GPMC_A16, (PTU | IEN | M3)}, /* gpio_40 */ + {GPMC_A17, (PTU | IEN | M3)}, /* gpio_41 - hdmi_ls_oe */ + {GPMC_A18, (PTU | IEN | M3)}, /* gpio_42 */ + {GPMC_A19, (PTU | IEN | M3)}, /* gpio_43 - wifi_en */ + {GPMC_A20, (PTU | IEN | M3)}, /* gpio_44 - eth_irq */ + {GPMC_A21, (PTU | IEN | M3)}, /* gpio_45 - eth_nreset */ + {GPMC_A22, (PTU | IEN | M3)}, /* gpio_46 - eth_pme */ + {GPMC_A23, (PTU | IEN | M3)}, /* gpio_47 */ + {GPMC_A24, (PTU | IEN | M3)}, /* gpio_48 - eth_mdix */ + {GPMC_A25, (PTU | IEN | M3)}, /* gpio_49 - bt_wakeup */ + {GPMC_NCS0, (PTU | M0)}, /* gpmc_ncs0 */ + {GPMC_NCS1, (PTU | M0)}, /* gpmc_ncs1 */ + {GPMC_NCS2, (PTU | M0)}, /* gpmc_ncs2 */ + {GPMC_NCS3, (PTU | IEN | M3)}, /* gpio_53 */ + {C2C_DATA12, (PTU | M0)}, /* gpmc_ncs4 */ + {C2C_DATA13, (PTU | M0)}, /* gpmc_ncs5 - eth_cs */ + {GPMC_NWP, (PTU | IEN | M0)}, /* gpmc_nwp */ + {GPMC_CLK, (PTU | IEN | M0)}, /* gpmc_clk */ + {GPMC_NADV_ALE, (PTU | M0)}, /* gpmc_nadv_ale */ + {GPMC_NBE0_CLE, (PTU | M0)}, /* gpmc_nbe0_cle */ + {GPMC_NBE1, (PTU | M0)}, /* gpmc_nbe1 */ + {GPMC_WAIT0, (PTU | IEN | M0)}, /* gpmc_wait0 */ + {GPMC_WAIT1, (PTU | IEN | M0)}, /* gpio_62 - usbh_nreset */ + {GPMC_NOE, (PTU | M0)}, /* gpmc_noe */ + {GPMC_NWE, (PTU | M0)}, /* gpmc_nwe */ + {HDMI_HPD, (PTD | IEN | M3)}, /* gpio_63 - hdmi_hpd */ + {HDMI_CEC, (PTU | IEN | M0)}, /* hdmi_cec */ + {HDMI_DDC_SCL, (M0)}, /* hdmi_ddc_scl */ + {HDMI_DDC_SDA, (IEN | M0)}, /* hdmi_ddc_sda */ + {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ + {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ + {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ + {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ + {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ + {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ + {CSI21_DX3, (IEN | M0)}, /* csi21_dx3 */ + {CSI21_DY3, (IEN | M0)}, /* csi21_dy3 */ + {CSI21_DX4, (IEN | M0)}, /* csi21_dx4 */ + {CSI21_DY4, (IEN | M0)}, /* csi21_dy4 */ + {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ + {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ + {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ + {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ + {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ + {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ + {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ + {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ + {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ + {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ + {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ + {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ + {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ + {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ + {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ + {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ + {USBB1_HSIC_DATA, (PTU | IEN | M3)}, /* gpio_96 - usbh_cpen */ + {USBB1_HSIC_STROBE, (PTU | IEN | M3)}, /* gpio_97 - usbh_reset */ + {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ + {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ + {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ + {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ + {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ + {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ + {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ + {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ + {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ + {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ + {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ + {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ + {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ + {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ + {UART2_RTS, (M0)}, /* uart2_rts */ + {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ + {UART2_TX, (M0)}, /* uart2_tx */ + {HDQ_SIO, (M0)}, /* hdq-sio */ + {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ + {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ + {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ + {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ + {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs1 */ + {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_clk */ + {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ + {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ + {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ + {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ + {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ + {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ + {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ + {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ + {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ + {UART4_RX, (IEN | PTU | M0)}, /* uart4_rx */ + {UART4_TX, (M0)}, /* uart4_tx */ + {USBB2_ULPITLL_CLK, (PTU | IEN | M3)}, /* gpio_157 - start_adc */ + {USBB2_ULPITLL_STP, (PTU | IEN | M3)}, /* gpio_158 - spi_nirq */ + {USBB2_ULPITLL_DIR, (PTU | IEN | M3)}, /* gpio_159 - bt_nreset */ + {USBB2_ULPITLL_NXT, (PTU | IEN | M3)}, /* gpio_160 - audio_pwron*/ + {USBB2_ULPITLL_DAT0, (PTU | IEN | M3)}, /* gpio_161 - bid_0 */ + {USBB2_ULPITLL_DAT1, (PTU | IEN | M3)}, /* gpio_162 - bid_1 */ + {USBB2_ULPITLL_DAT2, (PTU | IEN | M3)}, /* gpio_163 - bid_2 */ + {USBB2_ULPITLL_DAT3, (PTU | IEN | M3)}, /* gpio_164 - bid_3 */ + {USBB2_ULPITLL_DAT4, (PTU | IEN | M3)}, /* gpio_165 - bid_4 */ + {USBB2_ULPITLL_DAT5, (PTU | IEN | M3)}, /* gpio_166 - ts_irq*/ + {USBB2_ULPITLL_DAT6, (PTU | IEN | M3)}, /* gpio_167 - gps_pps */ + {USBB2_ULPITLL_DAT7, (PTU | IEN | M3)}, /* gpio_168 */ + {USBB2_HSIC_DATA, (PTU | IEN | M3)}, /* gpio_169 */ + {USBB2_HSIC_STROBE, (PTU | IEN | M3)}, /* gpio_170 */ + {UNIPRO_TX1, (PTU | IEN | M3)}, /* gpio_173 */ + {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ + {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ + {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ + {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ + {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ + {SYS_BOOT0, (M0)}, /* sys_boot0 */ + {SYS_BOOT1, (M0)}, /* sys_boot1 */ + {SYS_BOOT2, (M0)}, /* sys_boot2 */ + {SYS_BOOT3, (M0)}, /* sys_boot3 */ + {SYS_BOOT4, (M0)}, /* sys_boot4 */ + {SYS_BOOT5, (M0)}, /* sys_boot5 */ + {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ + {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ + {DPM_EMU16, (PTU | IEN | M3)}, /* gpio_27 */ + {DPM_EMU17, (PTU | IEN | M3)}, /* gpio_28 */ + {DPM_EMU18, (PTU | IEN | M3)}, /* gpio_29 */ + {DPM_EMU19, (PTU | IEN | M3)}, /* gpio_30 */ +}; + +const struct pad_conf_entry wkup_padconf_array_non_essential[] = { + {PAD1_FREF_XTAL_IN, (M0)}, /* fref_xtal_in */ + {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ + {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ + {PAD0_FREF_CLK0_OUT, (M7)}, /* safe mode */ + {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ + {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ + {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ + {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ + {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ + {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ + {PAD0_SYS_BOOT6, (M0)}, /* sys_boot6 */ + {PAD1_SYS_BOOT7, (M0)}, /* sys_boot7 */ +}; + + +#endif /* _DUOVERO_MUX_DATA_H_ */ diff --git a/board/gumstix/pepper/Makefile b/board/gumstix/pepper/Makefile new file mode 100644 index 000000000..ecb1d6166 --- /dev/null +++ b/board/gumstix/pepper/Makefile @@ -0,0 +1,13 @@ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += mux.o +endif + +obj-y += board.o diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c new file mode 100644 index 000000000..75aac49fd --- /dev/null +++ b/board/gumstix/pepper/board.c @@ -0,0 +1,226 @@ +/* + * Board functions for Gumstix Pepper and AM335x-based boards + * + * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/ + * Based on board/ti/am335x/board.c from Texas Instruments, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <power/tps65217.h> +#include <environment.h> +#include <watchdog.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +static const struct ddr_data ddr2_data = { + .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | + (MT47H128M16RT25E_RD_DQS<<20) | + (MT47H128M16RT25E_RD_DQS<<10) | + (MT47H128M16RT25E_RD_DQS<<0)), + .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | + (MT47H128M16RT25E_WR_DQS<<20) | + (MT47H128M16RT25E_WR_DQS<<10) | + (MT47H128M16RT25E_WR_DQS<<0)), + .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | + (MT47H128M16RT25E_PHY_WRLVL<<20) | + (MT47H128M16RT25E_PHY_WRLVL<<10) | + (MT47H128M16RT25E_PHY_WRLVL<<0)), + .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | + (MT47H128M16RT25E_PHY_GATELVL<<20) | + (MT47H128M16RT25E_PHY_GATELVL<<10) | + (MT47H128M16RT25E_PHY_GATELVL<<0)), + .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | + (MT47H128M16RT25E_PHY_FIFO_WE<<20) | + (MT47H128M16RT25E_PHY_FIFO_WE<<10) | + (MT47H128M16RT25E_PHY_FIFO_WE<<0)), + .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | + (MT47H128M16RT25E_PHY_WR_DATA<<20) | + (MT47H128M16RT25E_PHY_WR_DATA<<10) | + (MT47H128M16RT25E_PHY_WR_DATA<<0)), +}; + +static const struct cmd_control ddr2_cmd_ctrl_data = { + .cmd0csratio = MT47H128M16RT25E_RATIO, + .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, + + .cmd1csratio = MT47H128M16RT25E_RATIO, + .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, + + .cmd2csratio = MT47H128M16RT25E_RATIO, + .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, +}; + +static const struct emif_regs ddr2_emif_reg_data = { + .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, + .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, + .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, + .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, + .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, +}; + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + return serial_tstc() && serial_getc() == 'c'; +} +#endif + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, +}; + +void sdram_init(void) +{ + config_ddr(266, &ioregs, &ddr2_data, + &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); +} +#endif + +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + + return 0; +} + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_RGMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + const char *devname; + + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + + /* + * + * CPSW RGMII Internal Delay Mode is not supported in all PVT + * operating points. So we must set the TX clock delay feature + * in the KSZ9021 PHY. Since we only support a single ethernet + * device in U-Boot, we only do this for the current instance. + */ + devname = miiphy_get_current_dev(); + /* max rx/tx clock delay, min rx/tx control delay */ + miiphy_write(devname, 0x0, 0x0b, 0x8104); + miiphy_write(devname, 0x0, 0xc, 0xa0a0); + + /* min rx data delay */ + miiphy_write(devname, 0x0, 0x0b, 0x8105); + miiphy_write(devname, 0x0, 0x0c, 0x0000); + + /* min tx data delay */ + miiphy_write(devname, 0x0, 0x0b, 0x8106); + miiphy_write(devname, 0x0, 0x0c, 0x0000); + + return n; +} +#endif diff --git a/board/gumstix/pepper/board.h b/board/gumstix/pepper/board.h new file mode 100644 index 000000000..0512735a7 --- /dev/null +++ b/board/gumstix/pepper/board.h @@ -0,0 +1,19 @@ +/* + * Gumstix Pepper and AM335x-based boards information header + * + * Copyright (C) 2014, Gumstix, Inc. - http://www.gumstix.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * We must be able to enable uart0, for initial output. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/gumstix/pepper/mux.c b/board/gumstix/pepper/mux.c new file mode 100644 index 000000000..50b12666d --- /dev/null +++ b/board/gumstix/pepper/mux.c @@ -0,0 +1,78 @@ +/* + * Muxing for Gumstix Pepper and AM335x-based boards + * + * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <i2c.h> +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + /* I2C_DATA */ + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + /* I2C_SCLK */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, /* ETH_INT */ + {OFFSET(mii1_col), MODE(7) | PULLUP_EN}, /* PHY_NRESET */ + {OFFSET(xdma_event_intr1), MODE(3)}, + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +/* + * Do board-specific muxes. + */ +void enable_board_pin_mux(void) +{ + /* I2C0 */ + configure_module_pin_mux(i2c0_pin_mux); + /* SD Card */ + configure_module_pin_mux(mmc0_pin_mux); + /* Ethernet pinmux. */ + configure_module_pin_mux(rgmii1_pin_mux); +} diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c index 5fec914f5..0183f781d 100644 --- a/board/hymod/hymod.c +++ b/board/hymod/hymod.c @@ -8,6 +8,8 @@ */ #include <common.h> +#include <bootretry.h> +#include <cli.h> #include <mpc8260.h> #include <mpc8260_irq.h> #include <ioports.h> @@ -413,13 +415,11 @@ last_stage_init (void) hymod_conf_t *cp = &gd->bd->bi_hymod_conf; int rc; -#ifdef CONFIG_BOOT_RETRY_TIME /* - * we use the readline () function, but we also want + * we use the cli_readline() function, but we also want * command timeout enabled */ - init_cmd_timeout (); -#endif + bootretry_init_cmd_timeout(); memset ((void *) cp, 0, sizeof (*cp)); diff --git a/board/hymod/input.c b/board/hymod/input.c index 184902cde..a9035d340 100644 --- a/board/hymod/input.c +++ b/board/hymod/input.c @@ -6,6 +6,8 @@ */ #include <common.h> +#include <bootretry.h> +#include <cli.h> int hymod_get_serno (const char *prompt) @@ -14,11 +16,9 @@ hymod_get_serno (const char *prompt) int n, serno; char *p; -#ifdef CONFIG_BOOT_RETRY_TIME - reset_cmd_timeout (); -#endif + bootretry_reset_cmd_timeout(); - n = readline (prompt); + n = cli_readline(prompt); if (n < 0) return (n); @@ -42,11 +42,9 @@ hymod_get_ethaddr (void) for (;;) { int n; -#ifdef CONFIG_BOOT_RETRY_TIME - reset_cmd_timeout (); -#endif + bootretry_reset_cmd_timeout(); - n = readline ("Enter board ethernet address: "); + n = cli_readline("Enter board ethernet address: "); if (n < 0) return (n); diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index f941e44e8..2ddb3da38 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -12,7 +12,7 @@ #include <ioports.h> #include <command.h> #include <malloc.h> -#include <hush.h> +#include <cli_hush.h> #include <net.h> #include <netdev.h> #include <asm/io.h> diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c index f0e91bbdf..bffc08be9 100644 --- a/board/keymile/common/ivm.c +++ b/board/keymile/common/ivm.c @@ -6,7 +6,7 @@ */ #include <common.h> -#include <hush.h> +#include <cli_hush.h> #include <i2c.h> #include "common.h" diff --git a/board/matrix_vision/common/mv_common.c b/board/matrix_vision/common/mv_common.c index 70133b511..1be5aba2e 100644 --- a/board/matrix_vision/common/mv_common.c +++ b/board/matrix_vision/common/mv_common.c @@ -77,7 +77,7 @@ int mv_load_fpga(void) return -1; } - result = fpga_load(0, fpga_data, data_size); + result = fpga_load(0, fpga_data, data_size, BIT_FULL); if (!result) bootstage_mark(BOOTSTAGE_ID_START); diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c index 2f622b084..43173ce06 100644 --- a/board/mcc200/auto_update.c +++ b/board/mcc200/auto_update.c @@ -12,11 +12,6 @@ #include <usb.h> #include <part.h> -#ifdef CONFIG_SYS_HUSH_PARSER -#include <hush.h> -#endif - - #ifdef CONFIG_AUTO_UPDATE #ifndef CONFIG_USB_OHCI @@ -247,7 +242,7 @@ int au_do_update(int idx, long sz) /* parse_string_outer() runs off the end. */ addr[image_get_data_size (hdr)] = 0; addr += 8; - parse_string_outer(addr, FLAG_PARSE_SEMICOLON); + run_command_list(addr, -1, 0); return 0; } diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index f97aafad4..5d37718f3 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include "pinmux-config-jetson-tk1.h" @@ -15,6 +16,11 @@ */ void pinmux_init(void) { + pinmux_set_tristate_input_clamping(); + + gpio_config_table(jetson_tk1_gpio_inits, + ARRAY_SIZE(jetson_tk1_gpio_inits)); + pinmux_config_pingrp_table(jetson_tk1_pingrps, ARRAY_SIZE(jetson_tk1_pingrps)); diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h index 1adcae4bd..d338818a6 100644 --- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h +++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h @@ -7,6 +7,98 @@ #ifndef _PINMUX_CONFIG_JETSON_TK1_H_ #define _PINMUX_CONFIG_JETSON_TK1_H_ +#define GPIO_INIT(_gpio, _init) \ + { \ + .gpio = GPIO_P##_gpio, \ + .init = TEGRA_GPIO_INIT_##_init, \ + } + +static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = { + /* gpio, init_val */ + GPIO_INIT(C7, IN), + GPIO_INIT(G0, OUT0), + GPIO_INIT(G1, OUT0), + GPIO_INIT(G2, IN), + GPIO_INIT(G3, IN), + GPIO_INIT(H2, OUT0), + GPIO_INIT(H3, OUT0), + GPIO_INIT(H4, IN), + GPIO_INIT(H5, OUT0), + GPIO_INIT(H6, IN), + GPIO_INIT(H7, OUT0), + GPIO_INIT(I0, OUT0), + GPIO_INIT(I2, OUT0), + GPIO_INIT(I4, OUT0), + GPIO_INIT(I5, IN), + GPIO_INIT(I6, IN), + GPIO_INIT(J0, IN), + GPIO_INIT(J2, IN), + GPIO_INIT(K1, OUT0), + GPIO_INIT(K2, IN), + GPIO_INIT(K3, IN), + GPIO_INIT(K4, OUT0), + GPIO_INIT(K5, OUT0), + GPIO_INIT(K6, OUT0), + GPIO_INIT(N7, IN), + GPIO_INIT(O0, IN), + GPIO_INIT(O1, IN), + GPIO_INIT(O2, IN), + GPIO_INIT(O3, IN), + GPIO_INIT(O4, IN), + GPIO_INIT(O5, IN), + GPIO_INIT(O6, OUT0), + GPIO_INIT(O7, IN), + GPIO_INIT(P0, OUT0), + GPIO_INIT(P1, OUT0), + GPIO_INIT(P2, OUT0), + GPIO_INIT(Q0, IN), + GPIO_INIT(Q1, IN), + GPIO_INIT(Q2, IN), + GPIO_INIT(Q5, IN), + GPIO_INIT(Q6, IN), + GPIO_INIT(Q7, IN), + GPIO_INIT(R0, OUT0), + GPIO_INIT(R1, OUT0), + GPIO_INIT(R2, OUT0), + GPIO_INIT(R4, IN), + GPIO_INIT(R5, OUT0), + GPIO_INIT(R7, IN), + GPIO_INIT(S0, IN), + GPIO_INIT(S3, OUT0), + GPIO_INIT(S4, OUT0), + GPIO_INIT(S5, IN), + GPIO_INIT(S6, OUT0), + GPIO_INIT(T0, OUT0), + GPIO_INIT(T1, OUT0), + GPIO_INIT(U0, OUT0), + GPIO_INIT(U1, IN), + GPIO_INIT(U2, IN), + GPIO_INIT(U3, OUT0), + GPIO_INIT(U4, OUT0), + GPIO_INIT(U5, IN), + GPIO_INIT(U6, IN), + GPIO_INIT(V0, IN), + GPIO_INIT(V1, IN), + GPIO_INIT(W2, IN), + GPIO_INIT(W3, IN), + GPIO_INIT(X1, OUT0), + GPIO_INIT(X3, IN), + GPIO_INIT(X4, OUT0), + GPIO_INIT(X5, IN), + GPIO_INIT(X6, IN), + GPIO_INIT(X7, OUT0), + GPIO_INIT(BB3, OUT0), + GPIO_INIT(BB5, OUT0), + GPIO_INIT(BB6, OUT0), + GPIO_INIT(BB7, OUT0), + GPIO_INIT(CC1, IN), + GPIO_INIT(CC2, IN), + GPIO_INIT(CC5, OUT0), + GPIO_INIT(EE1, OUT0), + GPIO_INIT(FF1, OUT0), + GPIO_INIT(FF2, IN), +}; + #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ { \ .pingrp = PMUX_PINGRP_##_pingrp, \ @@ -41,43 +133,43 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = { PINCFG(UART2_RXD_PC3, IRDA, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), - PINCFG(PC7, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PG0, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PG1, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PG2, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PG3, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PC7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG3, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PH2, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PH3, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PH4, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PH5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PH6, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PH7, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PI0, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PI1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PI2, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PI4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PI5, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PI6, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PJ0, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PJ2, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PJ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(UART2_CTS_N_PJ5, UARTB, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PK0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PK1, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PK2, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PK3, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PK4, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(SPDIF_OUT_PK5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(SPDIF_IN_PK6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SPDIF_OUT_PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SPDIF_IN_PK6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PK7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(DAP1_FS_PN0, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(DAP1_DIN_PN1, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), @@ -85,79 +177,79 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = { PINCFG(DAP1_SCLK_PN3, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(USB_VBUS_EN0_PN4, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(USB_VBUS_EN1_PN5, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT), - PINCFG(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, NORMAL), - PINCFG(ULPI_DATA7_PO0, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA0_PO1, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA1_PO2, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA2_PO3, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA3_PO4, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(ULPI_DATA6_PO7, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(DAP3_DOUT_PP2, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(ULPI_DATA7_PO0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA0_PO1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA1_PO2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA2_PO3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA3_PO4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA6_PO7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_FS_PP0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_DIN_PP1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(DAP4_DOUT_PP6, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(DAP4_SCLK_PP7, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL0_PQ0, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL1_PQ1, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL2_PQ2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL0_PQ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL1_PQ1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(KB_COL3_PQ3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL5_PQ5, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL6_PQ6, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_COL7_PQ7, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW0_PR0, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW1_PR1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW2_PR2, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL5_PQ5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW2_PR2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(KB_ROW3_PR3, SYS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW4_PR4, RSVD3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW5_PR5, RSVD3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW4_PR4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW5_PR5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW7_PR7, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW8_PS0, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW7_PR7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW8_PS0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(KB_ROW9_PS1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(KB_ROW10_PS2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW11_PS3, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW12_PS4, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW13_PS5, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW14_PS6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW13_PS5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW14_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(KB_ROW15_PS7, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW16_PT0, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(KB_ROW17_PT1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW16_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PU0, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PU1, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PU2, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PU3, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PU4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PU5, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PU6, RSVD3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PV0, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PV1, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PV0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PV1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), - PINCFG(GPIO_W2_AUD_PW2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_W3_AUD_PW3, SPI6, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_W2_AUD_PW2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_W3_AUD_PW3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_X1_AUD_PX1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_X3_AUD_PX3, RSVD4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_X4_AUD_PX4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_X5_AUD_PX5, RSVD4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_X6_AUD_PX6, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(GPIO_X7_AUD_PX7, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X3_AUD_PX3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X5_AUD_PX5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X6_AUD_PX6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(ULPI_DIR_PY1, SPI1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), @@ -181,25 +273,25 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = { PINCFG(PBB0, VIMCLK2_ALT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), - PINCFG(PBB3, VGP3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PBB5, RSVD3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PBB6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PBB7, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(PCC1, RSVD2, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(PCC2, RSVD2, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PCC1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PCC2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(CLK2_REQ_PCC5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), - PINCFG(CLK3_REQ_PEE1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK3_REQ_PEE1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(DAP_MCLK1_REQ_PEE2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(USB_VBUS_EN2_PFF1, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), - PINCFG(PFF2, RSVD2, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(USB_VBUS_EN2_PFF1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PFF2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(CPU_PWR_REQ, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h index 2f79ec752..bf8e3fd96 100644 --- a/board/nvidia/venice2/pinmux-config-venice2.h +++ b/board/nvidia/venice2/pinmux-config-venice2.h @@ -1,76 +1,286 @@ /* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _PINMUX_CONFIG_VENICE2_H_ #define _PINMUX_CONFIG_VENICE2_H_ -#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .lock = PMUX_PIN_LOCK_DEFAULT, \ - .od = PMUX_PIN_OD_DEFAULT, \ - .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ +#define GPIO_INIT(_gpio, _init) \ + { \ + .gpio = GPIO_P##_gpio, \ + .init = TEGRA_GPIO_INIT_##_init, \ } -#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .lock = PMUX_PIN_LOCK_##_lock, \ - .od = PMUX_PIN_OD_##_od, \ - .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ - } +static const struct tegra_gpio_config venice2_gpio_inits[] = { + /* gpio, init_val */ + GPIO_INIT(A0, IN), + GPIO_INIT(C7, IN), + GPIO_INIT(G0, IN), + GPIO_INIT(G1, IN), + GPIO_INIT(G2, IN), + GPIO_INIT(G3, IN), + GPIO_INIT(H2, IN), + GPIO_INIT(H4, IN), + GPIO_INIT(H5, OUT0), + GPIO_INIT(H6, IN), + GPIO_INIT(H7, OUT1), + GPIO_INIT(I0, IN), + GPIO_INIT(I1, IN), + GPIO_INIT(I2, OUT0), + GPIO_INIT(I4, OUT0), + GPIO_INIT(I5, OUT1), + GPIO_INIT(I6, IN), + GPIO_INIT(J0, IN), + GPIO_INIT(J7, IN), + GPIO_INIT(K0, IN), + GPIO_INIT(K1, OUT0), + GPIO_INIT(K2, IN), + GPIO_INIT(K3, IN), + GPIO_INIT(K4, OUT0), + GPIO_INIT(K6, OUT0), + GPIO_INIT(K7, IN), + GPIO_INIT(N7, IN), + GPIO_INIT(O2, IN), + GPIO_INIT(O5, IN), + GPIO_INIT(O6, OUT0), + GPIO_INIT(O7, IN), + GPIO_INIT(P2, OUT0), + GPIO_INIT(Q0, IN), + GPIO_INIT(Q2, IN), + GPIO_INIT(Q3, IN), + GPIO_INIT(Q6, IN), + GPIO_INIT(Q7, IN), + GPIO_INIT(R0, OUT0), + GPIO_INIT(R1, IN), + GPIO_INIT(R4, IN), + GPIO_INIT(S0, IN), + GPIO_INIT(S3, OUT0), + GPIO_INIT(S4, OUT0), + GPIO_INIT(S7, IN), + GPIO_INIT(T1, IN), + GPIO_INIT(U4, IN), + GPIO_INIT(U5, IN), + GPIO_INIT(U6, IN), + GPIO_INIT(V0, IN), + GPIO_INIT(V1, IN), + GPIO_INIT(W3, IN), + GPIO_INIT(X1, IN), + GPIO_INIT(X3, IN), + GPIO_INIT(X4, IN), + GPIO_INIT(X7, OUT0), + GPIO_INIT(CC5, OUT0), +}; -#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \ +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ { \ .pingrp = PMUX_PINGRP_##_pingrp, \ .func = PMUX_FUNC_##_mux, \ .pull = PMUX_PULL_##_pull, \ .tristate = PMUX_TRI_##_tri, \ .io = PMUX_PIN_##_io, \ - .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ } -#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .lock = PMUX_PIN_LOCK_##_lock, \ - .od = PMUX_PIN_OD_DEFAULT, \ - .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ - } - -#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .lock = PMUX_PIN_LOCK_##_lock, \ - .od = PMUX_PIN_OD_##_od, \ - .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ - } - -#define USB_PINMUX CEC_PINMUX +static const struct pmux_pingrp_config venice2_pingrps[] = { + /* pingrp, mux, pull, tri, e_input, od, rcv_sel */ + PINCFG(CLK_32K_OUT_PA0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PB0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PB1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_RXD_PC3, IRDA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(PC7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH0, PWM0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PJ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK4, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SPDIF_IN_PK6, DEFAULT, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA1_PO2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA6_PO7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL0_PQ0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL5_PQ5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW2_PR2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW7_PR7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW8_PS0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW9_PS1, UARTA, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW10_PS2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU0, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU1, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU3, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PV0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PV1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_W3_AUD_PW3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK2_OUT_PW5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X3_AUD_PX3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CAM_MCLK_PCC0, VI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L0_RST_N_PDD1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_WAKE_N_PDD3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PWR_INT_N, PMI, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL), + PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), +}; -#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ { \ .drvgrp = PMUX_DRVGRP_##_drvgrp, \ .slwf = _slwf, \ @@ -82,258 +292,7 @@ .hsm = PMUX_HSM_##_hsm, \ } -static struct pmux_pingrp_config tegra124_pinmux_common[] = { - /* EXTPERIPH1 pinmux */ - DEFAULT_PINMUX(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), - - /* I2S0 pinmux */ - DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), - - /* I2S1 pinmux */ - DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), - - /* I2S3 pinmux */ - DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), - - /* CLDVFS pinmux */ - DEFAULT_PINMUX(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT), - - /* ULPI pinmux */ - DEFAULT_PINMUX(ULPI_DATA0_PO1, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA1_PO2, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA2_PO3, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, UP, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT), - - /* EC KBC/SPI */ - DEFAULT_PINMUX(ULPI_CLK_PY0, SPI1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DIR_PY1, SPI1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, INPUT), - - /* I2C3 (TPM) pinmux */ - I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), - I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), - - /* I2C2 pinmux */ - I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), - I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), - - /* UARTD pinmux (UART4 on Servo board, unused) */ - DEFAULT_PINMUX(PJ7, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PB0, UARTD, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PB1, UARTD, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PK7, UARTD, NORMAL, NORMAL, OUTPUT), - - /* SPI4 (Winbond 'boot ROM') */ - DEFAULT_PINMUX(PG5, SPI4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PG6, SPI4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(PG7, SPI4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(PI3, SPI4, NORMAL, NORMAL, INPUT), - - /* Touch IRQ */ - DEFAULT_PINMUX(GPIO_W3_AUD_PW3, RSVD1, NORMAL, NORMAL, INPUT), - - /* PWM1 pinmux */ - DEFAULT_PINMUX(PH1, PWM1, NORMAL, NORMAL, OUTPUT), - - /* SDMMC1 pinmux */ - DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), - - /* SDMMC3 pinmux */ - DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, DOWN, NORMAL, INPUT), - - /* SDMMC4 pinmux */ - DEFAULT_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT), - - /* BLINK pinmux */ - DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT), - - /* KBC pinmux */ - DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT), - - /* Misc */ - DEFAULT_PINMUX(PV0, RSVD1, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(KB_ROW7_PR7, RSVD1, UP, NORMAL, INPUT), - - /* UARTA pinmux (BR_UART_TXD/RXD on Servo board) */ - DEFAULT_PINMUX(KB_ROW9_PS1, UARTA, UP, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW10_PS2, UARTA, UP, TRISTATE, INPUT), - - /* I2CPWR pinmux (I2C5) */ - I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), - I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), - - /* RTCK pinmux */ - DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT), - - /* CLK pinmux */ - DEFAULT_PINMUX(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT), - - /* PWRON pinmux */ - DEFAULT_PINMUX(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT), - - /* CPU pinmux */ - DEFAULT_PINMUX(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT), - - /* PMI pinmux */ - DEFAULT_PINMUX(PWR_INT_N, PMI, NORMAL, TRISTATE, INPUT), - - /* RESET_OUT_N pinmux */ - DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT), - - /* EXTPERIPH3 pinmux */ - DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), - - /* I2C1 pinmux */ - I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), - I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), - - /* UARTB, GPS */ - DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT), - - /* UARTC (WIFI/BT) */ - DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), - - /* CEC pinmux */ - CEC_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - - /* I2C4 (HDMI_DDC) pinmux */ - DDC_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), - DDC_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), - - /* USB pinmux */ - USB_PINMUX(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), - USB_PINMUX(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), - - /* Unused, marked SNN_ on schematic, TRISTATE 'em */ - DEFAULT_PINMUX(PBB0, RSVD3, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PBB3, RSVD3, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PBB4, RSVD3, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PBB5, RSVD2, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PBB6, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PBB7, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PCC2, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PH3, GMI, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PI7, GMI, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PJ2, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GPIO_X5_AUD_PX5, RSVD3, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GPIO_X6_AUD_PX6, GMI, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PFF2, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(USB_VBUS_EN2_PFF1, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_COL5_PQ5, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW2_PR2, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW3_PR3, KBC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW5_PR5, RSVD2, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW13_PS5, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW14_PS6, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW16_PT0, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(OWR, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(ULPI_DATA7_PO0, ULPI, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(DAP3_DIN_PP1, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(DAP3_FS_PP0, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(DAP3_SCLK_PP3, RSVD2, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(SDMMC1_WP_N_PV3, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(CAM_MCLK_PCC0, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(SPDIF_OUT_PK5, RSVD1, NORMAL, TRISTATE, INPUT), -}; - -static struct pmux_pingrp_config unused_pins_lowpower[] = { - DEFAULT_PINMUX(DAP_MCLK1_REQ_PEE2, RSVD3, DOWN, TRISTATE, OUTPUT), -}; - -/* Initially setting all used GPIO's to non-TRISTATE */ -static struct pmux_pingrp_config tegra124_pinmux_set_nontristate[] = { - DEFAULT_PINMUX(GPIO_X4_AUD_PX4, RSVD1, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_X7_AUD_PX7, RSVD1, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_X3_AUD_PX3, RSVD3, UP, NORMAL, INPUT), - - /* EN_VDD_BL */ - DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, OUTPUT), - - /* MODEM */ - DEFAULT_PINMUX(PV0, RSVD3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT), - - /* BOOT_SEL0-3 */ - DEFAULT_PINMUX(PG0, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PG1, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PG2, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PG3, GMI, NORMAL, NORMAL, INPUT), - - DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD3, NORMAL, NORMAL, OUTPUT), - - DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW4_PR4, KBC, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), - - DEFAULT_PINMUX(PU4, RSVD3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PU5, RSVD3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PU6, RSVD3, NORMAL, NORMAL, INPUT), - - DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(SPDIF_IN_PK6, RSVD2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT), - - /* TS_SHDN_L */ - DEFAULT_PINMUX(PK1, GMI, NORMAL, NORMAL, OUTPUT), +static const struct pmux_drvgrp_config venice2_drvgrps[] = { }; -static struct pmux_drvgrp_config venice2_padctrl[] = { - /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ - DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, - SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE), -}; #endif /* PINMUX_CONFIG_VENICE2_H */ diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c index 15082c419..c56ef129d 100644 --- a/board/nvidia/venice2/venice2.c +++ b/board/nvidia/venice2/venice2.c @@ -6,12 +6,9 @@ */ #include <common.h> -#include <asm-generic/gpio.h> #include <asm/arch/gpio.h> -#include <asm/arch/gp_padctrl.h> #include <asm/arch/pinmux.h> #include "pinmux-config-venice2.h" -#include <i2c.h> /* * Routine: pinmux_init @@ -19,16 +16,14 @@ */ void pinmux_init(void) { - pinmux_config_pingrp_table(tegra124_pinmux_set_nontristate, - ARRAY_SIZE(tegra124_pinmux_set_nontristate)); + pinmux_set_tristate_input_clamping(); - pinmux_config_pingrp_table(tegra124_pinmux_common, - ARRAY_SIZE(tegra124_pinmux_common)); + gpio_config_table(venice2_gpio_inits, + ARRAY_SIZE(venice2_gpio_inits)); - pinmux_config_pingrp_table(unused_pins_lowpower, - ARRAY_SIZE(unused_pins_lowpower)); + pinmux_config_pingrp_table(venice2_pingrps, + ARRAY_SIZE(venice2_pingrps)); - /* Initialize any non-default pad configs (APB_MISC_GP regs) */ - pinmux_config_drvgrp_table(venice2_padctrl, - ARRAY_SIZE(venice2_padctrl)); + pinmux_config_drvgrp_table(venice2_drvgrps, + ARRAY_SIZE(venice2_drvgrps)); } diff --git a/board/overo/overo.c b/board/overo/overo.c index 1192d02e9..62b50a8a0 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -39,6 +39,11 @@ DECLARE_GLOBAL_DATA_PTR; #define GUMSTIX_CHESTNUT43 0x06000200 #define GUMSTIX_PINTO 0x07000200 #define GUMSTIX_GALLOP43 0x08000200 +#define GUMSTIX_ALTO35 0x09000200 +#define GUMSTIX_STAGECOACH 0x0A000200 +#define GUMSTIX_THUMBO 0x0B000200 +#define GUMSTIX_TURTLECORE 0x0C000200 +#define GUMSTIX_ARBOR43C 0x0D000200 #define ETTUS_USRP_E 0x01000300 @@ -141,6 +146,7 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ + case REVISION_4: timings->mcfg = MICRON_V_MCFG_200(256 << 20); timings->ctrla = MICRON_V_ACTIMA_200; timings->ctrlb = MICRON_V_ACTIMB_200; @@ -230,6 +236,8 @@ unsigned int get_expansion_id(void) */ int misc_init_r(void) { + unsigned int expansion_id; + twl4030_power_init(); twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); @@ -252,7 +260,8 @@ int misc_init_r(void) puts("Unable to detect mmc2 connection type\n"); } - switch (get_expansion_id()) { + expansion_id = get_expansion_id(); + switch (expansion_id) { case GUMSTIX_SUMMIT: printf("Recognized Summit expansion board (rev %d %s)\n", expansion_config.revision, @@ -302,6 +311,35 @@ int misc_init_r(void) expansion_config.fab_revision); setenv("defaultdisplay", "lcd43"); break; + case GUMSTIX_ALTO35: + printf("Recognized Alto35 expansion board (rev %d %s)\n", + expansion_config.revision, + expansion_config.fab_revision); + MUX_ALTO35(); + setenv("defaultdisplay", "lcd35"); + break; + case GUMSTIX_STAGECOACH: + printf("Recognized Stagecoach expansion board (rev %d %s)\n", + expansion_config.revision, + expansion_config.fab_revision); + break; + case GUMSTIX_THUMBO: + printf("Recognized Thumbo expansion board (rev %d %s)\n", + expansion_config.revision, + expansion_config.fab_revision); + break; + case GUMSTIX_TURTLECORE: + printf("Recognized Turtlecore expansion board (rev %d %s)\n", + expansion_config.revision, + expansion_config.fab_revision); + break; + case GUMSTIX_ARBOR43C: + printf("Recognized Arbor43C expansion board (rev %d %s)\n", + expansion_config.revision, + expansion_config.fab_revision); + MUX_ARBOR43C(); + setenv("defaultdisplay", "lcd43"); + break; case ETTUS_USRP_E: printf("Recognized Ettus Research USRP-E (rev %d %s)\n", expansion_config.revision, @@ -313,7 +351,8 @@ int misc_init_r(void) puts("No EEPROM on expansion board\n"); break; default: - puts("Unrecognized expansion board\n"); + printf("Unrecognized expansion board 0x%08x\n", expansion_id); + break; } if (expansion_config.content == 1) diff --git a/board/overo/overo.h b/board/overo/overo.h index 64604de1b..57725d867 100644 --- a/board/overo/overo.h +++ b/board/overo/overo.h @@ -22,6 +22,7 @@ const omap3_sysinfo sysinfo = { #define REVISION_1 0x1 #define REVISION_2 0x2 #define REVISION_3 0x3 +#define REVISION_4 0x4 /* * IEN - Input Enable @@ -404,4 +405,20 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M4)) /*GPIO_173 */\ MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M4)) /*GPIO_175 */\ +#define MUX_ALTO35() \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10-BTN*/\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M4)) /*GPIO_148-RED LED*/\ + MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150-YELLOW LED*/\ + MUX_VAL(CP(UART1_RX), (IDIS | PTD | DIS | M4)) /*GPIO_151-BLUE LED*/\ + MUX_VAL(CP(HDQ_SIO), (IDIS | PTD | DIS | M4)) /*GPIO_170-GREEN LED*/\ + MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M4)) /*GPIO_175*/\ + +#define MUX_ARBOR43C() \ + MUX_VAL(CP(CSI2_DX1), (IDIS | PTD | DIS | M4)) /*GPIO_114-RED LED*/\ + MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150-YELLOW LED*/\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4)) /*GPIO_170-BUTTON */\ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M4)) /*GPIO_186-BLUE LED*/\ + MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | DIS | M4)) /*GPIO_31-CAP WAKE*/\ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10-CAP IRQ*/\ + #endif diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 32d3b584b..bfd0cc688 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -19,186 +19,28 @@ #include <netdev.h> #include <miiphy.h> #include <i2c.h> +#include <div64.h> #include "qos.h" DECLARE_GLOBAL_DATA_PTR; -#define s_init_wait(cnt) \ - ({ \ - u32 i = 0x10000 * cnt; \ - while (i > 0) \ - i--; \ - }) - - -#define dbpdrgd_check(bsc) \ - ({ \ - while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \ - ; \ - }) - -#if defined(CONFIG_NORFLASH) -static void bsc_init(void) -{ - struct r8a7791_lbsc *lbsc = (struct r8a7791_lbsc *)LBSC_BASE; - struct r8a7791_dbsc3 *dbsc3_0 = (struct r8a7791_dbsc3 *)DBSC3_0_BASE; - - /* LBSC */ - writel(0x00000020, &lbsc->cs0ctrl); - writel(0x00000020, &lbsc->cs1ctrl); - writel(0x00002020, &lbsc->ecs0ctrl); - writel(0x00002020, &lbsc->ecs1ctrl); - - writel(0x077F077F, &lbsc->cswcr0); - writel(0x077F077F, &lbsc->cswcr1); - writel(0x077F077F, &lbsc->ecswcr0); - writel(0x077F077F, &lbsc->ecswcr1); - - /* DBSC3 */ - s_init_wait(10); - - writel(0x0000A55A, &dbsc3_0->dbpdlck); - writel(0x00000001, &dbsc3_0->dbpdrga); - writel(0x80000000, &dbsc3_0->dbpdrgd); - writel(0x00000004, &dbsc3_0->dbpdrga); - dbpdrgd_check(dbsc3_0); - - writel(0x00000006, &dbsc3_0->dbpdrga); - writel(0x0001C000, &dbsc3_0->dbpdrgd); - - writel(0x00000023, &dbsc3_0->dbpdrga); - writel(0x00FD2480, &dbsc3_0->dbpdrgd); - - writel(0x00000010, &dbsc3_0->dbpdrga); - writel(0xF004649B, &dbsc3_0->dbpdrgd); - - writel(0x0000000F, &dbsc3_0->dbpdrga); - writel(0x00181EE4, &dbsc3_0->dbpdrgd); - - writel(0x0000000E, &dbsc3_0->dbpdrga); - writel(0x33C03812, &dbsc3_0->dbpdrgd); - - writel(0x00000003, &dbsc3_0->dbpdrga); - writel(0x0300C481, &dbsc3_0->dbpdrgd); - - writel(0x00000007, &dbsc3_0->dbkind); - writel(0x10030A02, &dbsc3_0->dbconf0); - writel(0x00000001, &dbsc3_0->dbphytype); - writel(0x00000000, &dbsc3_0->dbbl); - writel(0x0000000B, &dbsc3_0->dbtr0); - writel(0x00000008, &dbsc3_0->dbtr1); - writel(0x00000000, &dbsc3_0->dbtr2); - writel(0x0000000B, &dbsc3_0->dbtr3); - writel(0x000C000B, &dbsc3_0->dbtr4); - writel(0x00000027, &dbsc3_0->dbtr5); - writel(0x0000001C, &dbsc3_0->dbtr6); - writel(0x00000005, &dbsc3_0->dbtr7); - writel(0x00000018, &dbsc3_0->dbtr8); - writel(0x00000008, &dbsc3_0->dbtr9); - writel(0x0000000C, &dbsc3_0->dbtr10); - writel(0x00000009, &dbsc3_0->dbtr11); - writel(0x00000012, &dbsc3_0->dbtr12); - writel(0x000000D0, &dbsc3_0->dbtr13); - writel(0x00140005, &dbsc3_0->dbtr14); - writel(0x00050004, &dbsc3_0->dbtr15); - writel(0x70233005, &dbsc3_0->dbtr16); - writel(0x000C0000, &dbsc3_0->dbtr17); - writel(0x00000300, &dbsc3_0->dbtr18); - writel(0x00000040, &dbsc3_0->dbtr19); - writel(0x00000001, &dbsc3_0->dbrnk0); - writel(0x00020001, &dbsc3_0->dbadj0); - writel(0x20082008, &dbsc3_0->dbadj2); - writel(0x00020002, &dbsc3_0->dbwt0cnf0); - writel(0x0000000F, &dbsc3_0->dbwt0cnf4); - - writel(0x00000015, &dbsc3_0->dbpdrga); - writel(0x00000D70, &dbsc3_0->dbpdrgd); - - writel(0x00000016, &dbsc3_0->dbpdrga); - writel(0x00000006, &dbsc3_0->dbpdrgd); - - writel(0x00000017, &dbsc3_0->dbpdrga); - writel(0x00000018, &dbsc3_0->dbpdrgd); - - writel(0x00000012, &dbsc3_0->dbpdrga); - writel(0x9D5CBB66, &dbsc3_0->dbpdrgd); - - writel(0x00000013, &dbsc3_0->dbpdrga); - writel(0x1A868300, &dbsc3_0->dbpdrgd); - - writel(0x00000023, &dbsc3_0->dbpdrga); - writel(0x00FDB6C0, &dbsc3_0->dbpdrgd); - - writel(0x00000014, &dbsc3_0->dbpdrga); - writel(0x300214D8, &dbsc3_0->dbpdrgd); - - writel(0x0000001A, &dbsc3_0->dbpdrga); - writel(0x930035C7, &dbsc3_0->dbpdrgd); - - writel(0x00000060, &dbsc3_0->dbpdrga); - writel(0x330657B2, &dbsc3_0->dbpdrgd); - - writel(0x00000011, &dbsc3_0->dbpdrga); - writel(0x1000040B, &dbsc3_0->dbpdrgd); - - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x00000001, &dbsc3_0->dbpdrga); - writel(0x00000071, &dbsc3_0->dbpdrgd); - - writel(0x00000004, &dbsc3_0->dbpdrga); - dbpdrgd_check(dbsc3_0); - - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x2100FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - - writel(0x110000DB, &dbsc3_0->dbcmd); - - writel(0x00000001, &dbsc3_0->dbpdrga); - writel(0x00000181, &dbsc3_0->dbpdrgd); - - writel(0x00000004, &dbsc3_0->dbpdrga); - dbpdrgd_check(dbsc3_0); - - writel(0x00000001, &dbsc3_0->dbpdrga); - writel(0x0000FE01, &dbsc3_0->dbpdrgd); - - writel(0x00000004, &dbsc3_0->dbpdrga); - dbpdrgd_check(dbsc3_0); - - writel(0x00000000, &dbsc3_0->dbbs0cnt1); - writel(0x01004C20, &dbsc3_0->dbcalcnf); - writel(0x014000AA, &dbsc3_0->dbcaltr); - writel(0x00000140, &dbsc3_0->dbrfcnf0); - writel(0x00081860, &dbsc3_0->dbrfcnf1); - writel(0x00010000, &dbsc3_0->dbrfcnf2); - writel(0x00000001, &dbsc3_0->dbrfen); - writel(0x00000001, &dbsc3_0->dbacen); -} -#else -#define bsc_init() do {} while (0) -#endif /* CONFIG_NORFLASH */ - +#define CLK2MHZ(clk) (clk / 1000 / 1000) void s_init(void) { - struct r8a7791_rwdt *rwdt = (struct r8a7791_rwdt *)RWDT_BASE; - struct r8a7791_swdt *swdt = (struct r8a7791_swdt *)SWDT_BASE; + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + u32 stc; /* Watchdog init */ writel(0xA5A5A500, &rwdt->rwtcsra); writel(0xA5A5A500, &swdt->swtcsra); + /* CPU frequency setting. Set to 1.5GHz */ + stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; + clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); + /* QoS */ qos_init(); - - /* BSC */ - bsc_init(); } #define MSTPSR1 0xE6150038 @@ -213,18 +55,6 @@ void s_init(void) #define SMSTPCR8 0xE6150990 #define ETHER_MSTP813 (1 << 13) -#define PMMR 0xE6060000 -#define GPSR4 0xE6060014 -#define IPSR14 0xE6060058 - -#define set_guard_reg(addr, mask, value) \ -{ \ - u32 val; \ - val = (readl(addr) & ~(mask)) | (value); \ - writel(~val, PMMR); \ - writel(val, addr); \ -} - #define mstp_setbits(type, addr, saddr, set) \ out_##type((saddr), in_##type(addr) | (set)) #define mstp_clrbits(type, addr, saddr, clear) \ @@ -238,13 +68,7 @@ int board_early_init_f(void) { mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); -#if defined(CONFIG_NORFLASH) /* SCIF0 */ - set_guard_reg(GPSR4, 0x34000000, 0x00000000); - set_guard_reg(IPSR14, 0x00000FC7, 0x00000481); - set_guard_reg(GPSR4, 0x00000000, 0x34000000); -#endif - mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); /* ETHER */ diff --git a/board/renesas/koelsch/qos.c b/board/renesas/koelsch/qos.c index 7f88f7da8..55a04202c 100644 --- a/board/renesas/koelsch/qos.c +++ b/board/renesas/koelsch/qos.c @@ -1,7 +1,7 @@ /* * board/renesas/koelsch/qos.c * - * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013,2014 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0 * @@ -13,7 +13,7 @@ #include <asm/io.h> #include <asm/arch/rmobile.h> -/* QoS version 0.23 */ +/* QoS version 0.240 for ES1 and version 0.310 for ES2 */ enum { DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, @@ -102,24 +102,31 @@ static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = { void qos_init(void) { int i; - struct r8a7791_s3c *s3c; - struct r8a7791_s3c_qos *s3c_qos; - struct r8a7791_dbsc3_qos *qos_addr; - struct r8a7791_mxi *mxi; - struct r8a7791_mxi_qos *mxi_qos; - struct r8a7791_axi_qos *axi_qos; + struct rcar_s3c *s3c; + struct rcar_s3c_qos *s3c_qos; + struct rcar_dbsc3_qos *qos_addr; + struct rcar_mxi *mxi; + struct rcar_mxi_qos *mxi_qos; + struct rcar_axi_qos *axi_qos; /* DBSC DBADJ2 */ writel(0x20042004, DBSC3_0_DBADJ2); + writel(0x20042004, DBSC3_1_DBADJ2); /* S3C -QoS */ - s3c = (struct r8a7791_s3c *)S3C_BASE; - writel(0x00FF1B1D, &s3c->s3cadsplcr); - writel(0x1F0D0C0C, &s3c->s3crorr); - writel(0x1F0D0C0A, &s3c->s3cworr); - + s3c = (struct rcar_s3c *)S3C_BASE; + if (IS_R8A7791_ES2()) { + writel(0x00FF1B0D, &s3c->s3cadsplcr); + writel(0x1F0D0B0A, &s3c->s3crorr); + writel(0x1F0D0B09, &s3c->s3cworr); + writel(0x00200808, &s3c->s3carcr11); + } else { + writel(0x00FF1B1D, &s3c->s3cadsplcr); + writel(0x1F0D0C0C, &s3c->s3crorr); + writel(0x1F0D0C0A, &s3c->s3cworr); + } /* QoS Control Registers */ - s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_CCI0_BASE; + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; writel(0x00890089, &s3c_qos->s3cqos0); writel(0x20960010, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); @@ -130,7 +137,7 @@ void qos_init(void) writel(0x20AA2200, &s3c_qos->s3cqos7); writel(0x00002032, &s3c_qos->s3cqos8); - s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_CCI1_BASE; + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; writel(0x00890089, &s3c_qos->s3cqos0); writel(0x20960010, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); @@ -141,8 +148,11 @@ void qos_init(void) writel(0x20AA2200, &s3c_qos->s3cqos7); writel(0x00002032, &s3c_qos->s3cqos8); - s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_MXI_BASE; - writel(0x00820082, &s3c_qos->s3cqos0); + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; + if (IS_R8A7791_ES2()) + writel(0x80928092, &s3c_qos->s3cqos0); + else + writel(0x00820082, &s3c_qos->s3cqos0); writel(0x20960020, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); writel(0x20AA20DC, &s3c_qos->s3cqos3); @@ -152,7 +162,7 @@ void qos_init(void) writel(0x20AA20DC, &s3c_qos->s3cqos7); writel(0x00002032, &s3c_qos->s3cqos8); - s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_AXI_BASE; + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; writel(0x00820082, &s3c_qos->s3cqos0); writel(0x20960020, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); @@ -166,7 +176,7 @@ void qos_init(void) /* DBSC -QoS */ /* DBSC0 - Read */ for (i = DBSC3_00; i < DBSC3_NR; i++) { - qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; writel(0x00000002, &qos_addr->dblgcnt); writel(0x00002096, &qos_addr->dbtmval0); writel(0x00002064, &qos_addr->dbtmval1); @@ -181,7 +191,7 @@ void qos_init(void) /* DBSC0 - Write */ for (i = DBSC3_00; i < DBSC3_NR; i++) { - qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; writel(0x00000002, &qos_addr->dblgcnt); writel(0x000020EB, &qos_addr->dbtmval0); writel(0x0000206E, &qos_addr->dbtmval1); @@ -196,7 +206,7 @@ void qos_init(void) /* DBSC1 - Read */ for (i = DBSC3_00; i < DBSC3_NR; i++) { - qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_1_r_qos_addr[i]; + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_r_qos_addr[i]; writel(0x00000002, &qos_addr->dblgcnt); writel(0x00002096, &qos_addr->dbtmval0); writel(0x00002064, &qos_addr->dbtmval1); @@ -211,7 +221,7 @@ void qos_init(void) /* DBSC1 - Write */ for (i = DBSC3_00; i < DBSC3_NR; i++) { - qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_1_w_qos_addr[i]; + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_w_qos_addr[i]; writel(0x00000002, &qos_addr->dblgcnt); writel(0x000020EB, &qos_addr->dbtmval0); writel(0x0000206E, &qos_addr->dbtmval1); @@ -232,14 +242,14 @@ void qos_init(void) /* MXI -QoS */ /* Transaction Control (MXI) */ - mxi = (struct r8a7791_mxi *)MXI_BASE; + mxi = (struct rcar_mxi *)MXI_BASE; writel(0x00000013, &mxi->mxrtcr); writel(0x00000013, &mxi->mxwtcr); writel(0x00780080, &mxi->mxsaar0); writel(0x02000800, &mxi->mxsaar1); /* QoS Control (MXI) */ - mxi_qos = (struct r8a7791_mxi_qos *)MXI_QOS_BASE; + mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; writel(0x0000000C, &mxi_qos->vspdu0); writel(0x0000000C, &mxi_qos->vspdu1); writel(0x0000000D, &mxi_qos->du0); @@ -247,7 +257,7 @@ void qos_init(void) /* AXI -QoS */ /* Transaction Control (MXI) */ - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SYX64TO128_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x00002245, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -259,7 +269,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_AVB_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x000020A6, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -268,7 +278,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_G2D_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x000020A6, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -277,7 +287,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMP0_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002021, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -286,7 +296,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMP1_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002037, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -295,7 +305,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX0_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x00002245, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -307,7 +317,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX1_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x00002245, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -319,7 +329,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX2_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x00002245, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -331,7 +341,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_LBS_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000214C, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -340,7 +350,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUDS_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002004, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -352,7 +362,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUM_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002004, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -364,7 +374,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUR_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002004, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -376,7 +386,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUS0_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002004, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -388,7 +398,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUS1_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002004, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -400,7 +410,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MTSB0_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002021, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -409,7 +419,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MTSB1_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002021, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -418,7 +428,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_PCI_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000214C, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -427,7 +437,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_RTX_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x00002245, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -439,7 +449,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDS0_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x000020A6, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -448,7 +458,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDS1_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x000020A6, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -457,7 +467,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB20_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -466,7 +476,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB21_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -475,7 +485,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB22_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -484,7 +494,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB30_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000214C, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -493,7 +503,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_AX2M_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x00002245, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -502,7 +512,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CC50_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002029, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -511,7 +521,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CCI_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x00002245, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -520,7 +530,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CS_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -529,7 +539,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_DDM_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x000020A6, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -538,7 +548,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_ETH_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -547,7 +557,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MPXM_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x00002245, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -556,7 +566,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SAT0_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -565,7 +575,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SAT1_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -574,7 +584,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDM0_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000214C, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -583,7 +593,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDM1_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000214C, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -592,7 +602,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_TRAB_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x000020A6, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -601,7 +611,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_UDM0_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -610,7 +620,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_UDM1_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -620,7 +630,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosqon); /* QoS Register (RT-AXI) */ - axi_qos = (struct r8a7791_axi_qos *)RT_AXI_SHX_BASE; + axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -632,7 +642,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)RT_AXI_DBG_BASE; + axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -644,7 +654,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RDM_BASE; + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002299, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -653,7 +663,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RDS_BASE; + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002029, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -662,7 +672,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RTX64TO128_BASE; + axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x00002245, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -674,7 +684,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)RT_AXI_STPRO_BASE; + axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002029, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -686,12 +696,9 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)RT_AXI_SY2RT_BASE; + axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x00002245, &axi_qos->qosctset0); - writel(0x00002096, &axi_qos->qosctset1); - writel(0x00002030, &axi_qos->qosctset2); - writel(0x00002030, &axi_qos->qosctset3); writel(0x00000001, &axi_qos->qosreqctr); writel(0x00002064, &axi_qos->qosthres0); writel(0x00002004, &axi_qos->qosthres1); @@ -699,7 +706,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosqon); /* QoS Register (MP-AXI) */ - axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ADSP_BASE; + axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002037, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -708,34 +715,34 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ASDS0_BASE; + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002014, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00000040, &axi_qos->qosreqctr); writel(0x00002064, &axi_qos->qosthres0); writel(0x00002004, &axi_qos->qosthres1); writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ASDS1_BASE; + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002014, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00000040, &axi_qos->qosreqctr); writel(0x00002064, &axi_qos->qosthres0); writel(0x00002004, &axi_qos->qosthres1); writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MP_AXI_MLP_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002014, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); + axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); writel(0x00002064, &axi_qos->qosthres0); writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); + writel(0x00002001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MP_AXI_MMUMP_BASE; + axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002004, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -747,7 +754,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MP_AXI_SPU_BASE; + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -756,7 +763,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MP_AXI_SPUC_BASE; + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000206E, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -766,9 +773,12 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosqon); /* QoS Register (SYS-AXI256) */ - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_AXI128TO256_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); + if (IS_R8A7791_ES2()) + writel(0x000020EB, &axi_qos->qosctset0); + else + writel(0x00002245, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); writel(0x00002030, &axi_qos->qosctset2); writel(0x00002030, &axi_qos->qosctset3); @@ -778,9 +788,12 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_SYX_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); + if (IS_R8A7791_ES2()) + writel(0x000020EB, &axi_qos->qosctset0); + else + writel(0x00002245, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); writel(0x00002030, &axi_qos->qosctset2); writel(0x00002030, &axi_qos->qosctset3); @@ -790,9 +803,12 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_MPX_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; writel(0x00000002, &axi_qos->qosconf); - writel(0x00002245, &axi_qos->qosctset0); + if (IS_R8A7791_ES2()) + writel(0x000020EB, &axi_qos->qosctset0); + else + writel(0x00002245, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); writel(0x00002030, &axi_qos->qosctset2); writel(0x00002030, &axi_qos->qosctset3); @@ -802,7 +818,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_MXI_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x00002245, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -815,7 +831,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosqon); /* QoS Register (CCI-AXI) */ - axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUS0_BASE; + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002004, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -827,7 +843,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_SYX2_BASE; + axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x00002245, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -839,7 +855,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUR_BASE; + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002004, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -851,7 +867,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUDS_BASE; + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002004, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -863,7 +879,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUM_BASE; + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002004, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -875,7 +891,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MXI_BASE; + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x00002245, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -887,7 +903,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUS1_BASE; + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002004, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -899,7 +915,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUMP_BASE; + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002004, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -912,7 +928,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosqon); /* QoS Register (Media-AXI) */ - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_MXR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x000020DC, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -923,7 +939,7 @@ void qos_init(void) writel(0x00002032, &axi_qos->qosthres1); writel(0x00000001, &axi_qos->qosthres2); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_MXW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x000020DC, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); @@ -934,7 +950,7 @@ void qos_init(void) writel(0x00002032, &axi_qos->qosthres1); writel(0x00000001, &axi_qos->qosthres2); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_JPR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002190, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -943,16 +959,21 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_JPW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002190, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_TDMR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002190, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -961,7 +982,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_TDMW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002190, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -970,7 +991,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1CR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002190, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -979,16 +1000,21 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1CW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002190, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002190, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -997,16 +1023,21 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002190, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002190, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1015,25 +1046,36 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002190, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VIN0W_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; writel(0x00000001, &axi_qos->qosconf); - writel(0x000020C8, &axi_qos->qosctset0); + if (IS_R8A7791_ES2()) + writel(0x00001FF0, &axi_qos->qosctset0); + else + writel(0x000020C8, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); writel(0x00002064, &axi_qos->qosthres0); writel(0x00002004, &axi_qos->qosthres1); - writel(0x00000001, &axi_qos->qosthres2); + if (IS_R8A7791_ES2()) + writel(0x00002001, &axi_qos->qosthres2); + else + writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP0R_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x000020C8, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1042,16 +1084,21 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP0W_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x000020C8, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMSR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x000020C8, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1060,7 +1107,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMSW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x000020C8, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1069,7 +1116,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1R_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x000020C8, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1078,16 +1125,21 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1W_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x000020C8, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP1R_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x000020C8, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1096,16 +1148,21 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP1W_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x000020C8, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMRR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x000020C8, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1114,7 +1171,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMRW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x000020C8, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1123,40 +1180,55 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD0R_BASE; - writel(0x00000000, &axi_qos->qosconf); + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; + if (IS_R8A7791_ES2()) + writel(0x00000003, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); writel(0x000020C8, &axi_qos->qosctset0); writel(0x00002064, &axi_qos->qosthres0); writel(0x00002004, &axi_qos->qosthres1); writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD0W_BASE; - writel(0x00000000, &axi_qos->qosconf); + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; + if (IS_R8A7791_ES2()) + writel(0x00000003, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); writel(0x000020C8, &axi_qos->qosctset0); writel(0x00002064, &axi_qos->qosthres0); writel(0x00002004, &axi_qos->qosthres1); writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD1R_BASE; - writel(0x00000000, &axi_qos->qosconf); + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE; + if (IS_R8A7791_ES2()) + writel(0x00000003, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); writel(0x000020C8, &axi_qos->qosctset0); writel(0x00002064, &axi_qos->qosthres0); writel(0x00002004, &axi_qos->qosthres1); writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD1W_BASE; - writel(0x00000000, &axi_qos->qosconf); + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE; + if (IS_R8A7791_ES2()) + writel(0x00000003, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); writel(0x000020C8, &axi_qos->qosctset0); writel(0x00002064, &axi_qos->qosthres0); writel(0x00002004, &axi_qos->qosthres1); writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_DU0R_BASE; - writel(0x00000000, &axi_qos->qosconf); + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; + if (IS_R8A7791_ES2()) + writel(0x00000003, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); writel(0x00002063, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); writel(0x00002064, &axi_qos->qosthres0); @@ -1164,8 +1236,11 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_DU0W_BASE; - writel(0x00000000, &axi_qos->qosconf); + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; + if (IS_R8A7791_ES2()) + writel(0x00000000, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); writel(0x00002063, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); writel(0x00002064, &axi_qos->qosthres0); @@ -1173,7 +1248,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0CR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002073, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1182,16 +1257,21 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0CW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002073, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0VR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002073, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1200,16 +1280,21 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0VW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002073, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); - writel(0x00002064, &axi_qos->qosthres0); - writel(0x00002004, &axi_qos->qosthres1); + if (IS_R8A7791_ES2()) { + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + } else { + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + } writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VPC0R_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002073, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index ad5289a23..a5a0474cd 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -24,181 +24,23 @@ DECLARE_GLOBAL_DATA_PTR; -#define s_init_wait(cnt) \ - ({ \ - u32 i = 0x10000 * cnt; \ - while (i > 0) \ - i--; \ - }) - -#define dbpdrgd_check(bsc) \ - ({ \ - while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \ - ; \ - }) - -#if defined(CONFIG_NORFLASH) -static void bsc_init(void) -{ - struct r8a7790_lbsc *lbsc = (struct r8a7790_lbsc *)LBSC_BASE; - struct r8a7790_dbsc3 *dbsc3_0 = (struct r8a7790_dbsc3 *)DBSC3_0_BASE; - - /* LBSC */ - writel(0x00000020, &lbsc->cs0ctrl); - writel(0x00000020, &lbsc->cs1ctrl); - writel(0x00002020, &lbsc->ecs0ctrl); - writel(0x00002020, &lbsc->ecs1ctrl); - - writel(0x077F077F, &lbsc->cswcr0); - writel(0x077F077F, &lbsc->cswcr1); - writel(0x077F077F, &lbsc->ecswcr0); - writel(0x077F077F, &lbsc->ecswcr1); - - /* DBSC3 */ - s_init_wait(10); - - writel(0x0000A55A, &dbsc3_0->dbpdlck); - writel(0x00000001, &dbsc3_0->dbpdrga); - writel(0x80000000, &dbsc3_0->dbpdrgd); - writel(0x00000004, &dbsc3_0->dbpdrga); - dbpdrgd_check(dbsc3_0); - - writel(0x00000006, &dbsc3_0->dbpdrga); - writel(0x0001C000, &dbsc3_0->dbpdrgd); - - writel(0x00000023, &dbsc3_0->dbpdrga); - writel(0x00FD2480, &dbsc3_0->dbpdrgd); - - writel(0x00000010, &dbsc3_0->dbpdrga); - writel(0xF004649B, &dbsc3_0->dbpdrgd); - - writel(0x0000000F, &dbsc3_0->dbpdrga); - writel(0x00181EE4, &dbsc3_0->dbpdrgd); - - writel(0x0000000E, &dbsc3_0->dbpdrga); - writel(0x33C03812, &dbsc3_0->dbpdrgd); - - writel(0x00000003, &dbsc3_0->dbpdrga); - writel(0x0300C481, &dbsc3_0->dbpdrgd); - - writel(0x00000007, &dbsc3_0->dbkind); - writel(0x10030A02, &dbsc3_0->dbconf0); - writel(0x00000001, &dbsc3_0->dbphytype); - writel(0x00000000, &dbsc3_0->dbbl); - writel(0x0000000B, &dbsc3_0->dbtr0); - writel(0x00000008, &dbsc3_0->dbtr1); - writel(0x00000000, &dbsc3_0->dbtr2); - writel(0x0000000B, &dbsc3_0->dbtr3); - writel(0x000C000B, &dbsc3_0->dbtr4); - writel(0x00000027, &dbsc3_0->dbtr5); - writel(0x0000001C, &dbsc3_0->dbtr6); - writel(0x00000005, &dbsc3_0->dbtr7); - writel(0x00000018, &dbsc3_0->dbtr8); - writel(0x00000008, &dbsc3_0->dbtr9); - writel(0x0000000C, &dbsc3_0->dbtr10); - writel(0x00000009, &dbsc3_0->dbtr11); - writel(0x00000012, &dbsc3_0->dbtr12); - writel(0x000000D0, &dbsc3_0->dbtr13); - writel(0x00140005, &dbsc3_0->dbtr14); - writel(0x00050004, &dbsc3_0->dbtr15); - writel(0x70233005, &dbsc3_0->dbtr16); - writel(0x000C0000, &dbsc3_0->dbtr17); - writel(0x00000300, &dbsc3_0->dbtr18); - writel(0x00000040, &dbsc3_0->dbtr19); - writel(0x00000001, &dbsc3_0->dbrnk0); - writel(0x00020001, &dbsc3_0->dbadj0); - writel(0x20082008, &dbsc3_0->dbadj2); - writel(0x00020002, &dbsc3_0->dbwt0cnf0); - writel(0x0000000F, &dbsc3_0->dbwt0cnf4); - - writel(0x00000015, &dbsc3_0->dbpdrga); - writel(0x00000D70, &dbsc3_0->dbpdrgd); - - writel(0x00000016, &dbsc3_0->dbpdrga); - writel(0x00000006, &dbsc3_0->dbpdrgd); - - writel(0x00000017, &dbsc3_0->dbpdrga); - writel(0x00000018, &dbsc3_0->dbpdrgd); - - writel(0x00000012, &dbsc3_0->dbpdrga); - writel(0x9D5CBB66, &dbsc3_0->dbpdrgd); - - writel(0x00000013, &dbsc3_0->dbpdrga); - writel(0x1A868300, &dbsc3_0->dbpdrgd); - - writel(0x00000023, &dbsc3_0->dbpdrga); - writel(0x00FDB6C0, &dbsc3_0->dbpdrgd); - - writel(0x00000014, &dbsc3_0->dbpdrga); - writel(0x300214D8, &dbsc3_0->dbpdrgd); - - writel(0x0000001A, &dbsc3_0->dbpdrga); - writel(0x930035C7, &dbsc3_0->dbpdrgd); - - writel(0x00000060, &dbsc3_0->dbpdrga); - writel(0x330657B2, &dbsc3_0->dbpdrgd); - - writel(0x00000011, &dbsc3_0->dbpdrga); - writel(0x1000040B, &dbsc3_0->dbpdrgd); - - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x00000001, &dbsc3_0->dbpdrga); - writel(0x00000071, &dbsc3_0->dbpdrgd); - - writel(0x00000004, &dbsc3_0->dbpdrga); - dbpdrgd_check(dbsc3_0); - - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x2100FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - writel(0x0000FA00, &dbsc3_0->dbcmd); - - writel(0x110000DB, &dbsc3_0->dbcmd); - - writel(0x00000001, &dbsc3_0->dbpdrga); - writel(0x00000181, &dbsc3_0->dbpdrgd); - - writel(0x00000004, &dbsc3_0->dbpdrga); - dbpdrgd_check(dbsc3_0); - - writel(0x00000001, &dbsc3_0->dbpdrga); - writel(0x0000FE01, &dbsc3_0->dbpdrgd); - - writel(0x00000004, &dbsc3_0->dbpdrga); - dbpdrgd_check(dbsc3_0); - - writel(0x00000000, &dbsc3_0->dbbs0cnt1); - writel(0x01004C20, &dbsc3_0->dbcalcnf); - writel(0x014000AA, &dbsc3_0->dbcaltr); - writel(0x00000140, &dbsc3_0->dbrfcnf0); - writel(0x00081860, &dbsc3_0->dbrfcnf1); - writel(0x00010000, &dbsc3_0->dbrfcnf2); - writel(0x00000001, &dbsc3_0->dbrfen); - writel(0x00000001, &dbsc3_0->dbacen); -} -#else -#define bsc_init() do {} while (0) -#endif /* CONFIG_NORFLASH */ - +#define CLK2MHZ(clk) (clk / 1000 / 1000) void s_init(void) { - struct r8a7790_rwdt *rwdt = (struct r8a7790_rwdt *)RWDT_BASE; - struct r8a7790_swdt *swdt = (struct r8a7790_swdt *)SWDT_BASE; + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + u32 stc; /* Watchdog init */ writel(0xA5A5A500, &rwdt->rwtcsra); writel(0xA5A5A500, &swdt->swtcsra); + /* CPU frequency setting. Set to 1.4GHz */ + stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; + clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); + /* QoS(Quality-of-Service) Init */ qos_init(); - - /* BSC init */ - bsc_init(); } #define MSTPSR1 0xE6150038 @@ -213,18 +55,6 @@ void s_init(void) #define SMSTPCR8 0xE6150990 #define ETHER_MSTP813 (1 << 13) -#define PMMR 0xE6060000 -#define GPSR4 0xE6060014 -#define IPSR14 0xE6060058 - -#define set_guard_reg(addr, mask, value) \ -{ \ - u32 val; \ - val = (readl(addr) & ~(mask)) | (value); \ - writel(~val, PMMR); \ - writel(val, addr); \ -} - #define mstp_setbits(type, addr, saddr, set) \ out_##type((saddr), in_##type(addr) | (set)) #define mstp_clrbits(type, addr, saddr, clear) \ @@ -238,16 +68,8 @@ int board_early_init_f(void) { /* TMU0 */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); - -#if defined(CONFIG_NORFLASH) /* SCIF0 */ - set_guard_reg(GPSR4, 0x34000000, 0x00000000); - set_guard_reg(IPSR14, 0x00000FC7, 0x00000481); - set_guard_reg(GPSR4, 0x00000000, 0x34000000); -#endif - mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); - /* ETHER */ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); @@ -263,8 +85,6 @@ void arch_preboot_os(void) DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - /* board id for linux */ - gd->bd->bi_arch_number = MACH_TYPE_LAGER; /* adress of boot parameters */ gd->bd->bi_boot_params = LAGER_SDRAM_BASE + 0x100; diff --git a/board/renesas/lager/qos.c b/board/renesas/lager/qos.c index b88511a32..374275747 100644 --- a/board/renesas/lager/qos.c +++ b/board/renesas/lager/qos.c @@ -1,7 +1,7 @@ /* * board/renesas/lager/qos.c * - * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013,2014 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0 */ @@ -12,7 +12,7 @@ #include <asm/io.h> #include <asm/arch/rmobile.h> -/* QoS version 0.954 */ +/* QoS version 0.955 */ enum { DBSC3_R00, DBSC3_R01, DBSC3_R02, DBSC3_R03, DBSC3_R04, @@ -64,24 +64,24 @@ static const u32 dbsc3_qos_addr[DBSC3_NR] = { void qos_init(void) { int i; - struct r8a7790_s3c *s3c; - struct r8a7790_s3c_qos *s3c_qos; - struct r8a7790_dbsc3_qos *qos_addr; - struct r8a7790_mxi *mxi; - struct r8a7790_mxi_qos *mxi_qos; - struct r8a7790_axi_qos *axi_qos; + struct rcar_s3c *s3c; + struct rcar_s3c_qos *s3c_qos; + struct rcar_dbsc3_qos *qos_addr; + struct rcar_mxi *mxi; + struct rcar_mxi_qos *mxi_qos; + struct rcar_axi_qos *axi_qos; /* DBSC DBADJ2 */ writel(0x20042004, DBSC3_0_DBADJ2); /* S3C -QoS */ - s3c = (struct r8a7790_s3c *)S3C_BASE; + s3c = (struct rcar_s3c *)S3C_BASE; writel(0x80FF1C1E, &s3c->s3cadsplcr); writel(0x1F060505, &s3c->s3crorr); writel(0x1F020100, &s3c->s3cworr); /* QoS Control Registers */ - s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_CCI0_BASE; + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; writel(0x00800080, &s3c_qos->s3cqos0); writel(0x22000010, &s3c_qos->s3cqos1); writel(0x22002200, &s3c_qos->s3cqos2); @@ -92,7 +92,7 @@ void qos_init(void) writel(0x2F002200, &s3c_qos->s3cqos7); writel(0x2F002F00, &s3c_qos->s3cqos8); - s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_CCI1_BASE; + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; writel(0x00800080, &s3c_qos->s3cqos0); writel(0x22000010, &s3c_qos->s3cqos1); writel(0x22002200, &s3c_qos->s3cqos2); @@ -103,7 +103,7 @@ void qos_init(void) writel(0x2F002200, &s3c_qos->s3cqos7); writel(0x2F002F00, &s3c_qos->s3cqos8); - s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_MXI_BASE; + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; writel(0x80918099, &s3c_qos->s3cqos0); writel(0x20410010, &s3c_qos->s3cqos1); writel(0x200A2023, &s3c_qos->s3cqos2); @@ -114,7 +114,7 @@ void qos_init(void) writel(0x20502001, &s3c_qos->s3cqos7); writel(0x20142032, &s3c_qos->s3cqos8); - s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_AXI_BASE; + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; writel(0x00810089, &s3c_qos->s3cqos0); writel(0x20410001, &s3c_qos->s3cqos1); @@ -131,7 +131,7 @@ void qos_init(void) /* DBSC -QoS */ /* DBSC0 - Read/Write */ for (i = DBSC3_R00; i < DBSC3_NR; i++) { - qos_addr = (struct r8a7790_dbsc3_qos *)dbsc3_qos_addr[i]; + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_qos_addr[i]; writel(0x00000203, &qos_addr->dblgcnt); writel(0x00002064, &qos_addr->dbtmval0); writel(0x00002048, &qos_addr->dbtmval1); @@ -151,7 +151,7 @@ void qos_init(void) /* MXI -QoS */ /* Transaction Control (MXI) */ - mxi = (struct r8a7790_mxi *)MXI_BASE; + mxi = (struct rcar_mxi *)MXI_BASE; writel(0x00000013, &mxi->mxrtcr); writel(0x00000013, &mxi->mxwtcr); writel(0x00B800C0, &mxi->mxsaar0); @@ -162,7 +162,7 @@ void qos_init(void) writel(0x00200000, &mxi->mxaxiwacr); /* QoS Control (MXI) */ - mxi_qos = (struct r8a7790_mxi_qos *)MXI_QOS_BASE; + mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; writel(0x0000000C, &mxi_qos->vspdu0); writel(0x0000000C, &mxi_qos->vspdu1); writel(0x0000000D, &mxi_qos->du0); @@ -170,7 +170,7 @@ void qos_init(void) /* AXI -QoS */ /* Transaction Control (MXI) */ - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SYX64TO128_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x0000200F, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -182,7 +182,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_AVB_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000200A, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -191,7 +191,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_G2D_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000200A, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -200,7 +200,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMP0_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002002, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -209,7 +209,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMP1_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002004, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -218,7 +218,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX0_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x0000200F, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -230,7 +230,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX1_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x0000200F, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -242,7 +242,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX2_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x0000200F, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -254,7 +254,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_LBS_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002014, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -263,7 +263,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUDS_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002001, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -275,7 +275,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUM_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002001, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -287,7 +287,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUR_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002001, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -299,7 +299,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUS0_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002001, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -311,7 +311,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUS1_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002001, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -323,7 +323,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MTSB0_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002002, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -332,7 +332,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MTSB1_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002002, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -341,7 +341,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_PCI_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002014, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -350,7 +350,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_RTX_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x0000200F, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -362,7 +362,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SDS0_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000200A, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -371,7 +371,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SDS1_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000200A, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -380,7 +380,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB20_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002005, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -389,7 +389,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB21_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002005, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -398,7 +398,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB22_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002005, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -407,7 +407,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB30_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002014, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -417,7 +417,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosqon); /* QoS Register (RT-AXI) */ - axi_qos = (struct r8a7790_axi_qos *)RT_AXI_SHX_BASE; + axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002005, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -429,7 +429,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)RT_AXI_RDS_BASE; + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002007, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -438,7 +438,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)RT_AXI_RTX64TO128_BASE; + axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x0000200F, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -450,7 +450,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)RT_AXI_STPRO_BASE; + axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002003, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -463,7 +463,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosqon); /* QoS Register (MP-AXI) */ - axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ADSP_BASE; + axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002007, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -472,34 +472,34 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ASDS0_BASE; + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002014, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00000040, &axi_qos->qosreqctr); writel(0x00002006, &axi_qos->qosthres0); writel(0x00002001, &axi_qos->qosthres1); writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ASDS1_BASE; + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002014, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00000040, &axi_qos->qosreqctr); writel(0x00002006, &axi_qos->qosthres0); writel(0x00002001, &axi_qos->qosthres1); writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MP_AXI_MLP_BASE; - writel(0x00000000, &axi_qos->qosconf); - writel(0x00002002, &axi_qos->qosctset0); - writel(0x00000001, &axi_qos->qosreqctr); + axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); writel(0x00002006, &axi_qos->qosthres0); writel(0x00002001, &axi_qos->qosthres1); - writel(0x00000000, &axi_qos->qosthres2); + writel(0x00002001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MP_AXI_MMUMP_BASE; + axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002001, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -511,7 +511,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MP_AXI_SPU_BASE; + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x00002018, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -520,7 +520,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MP_AXI_SPUC_BASE; + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000200D, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -530,7 +530,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosqon); /* QoS Register (SYS-AXI256) */ - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_AXI128TO256_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x0000200F, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -542,7 +542,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_SYX_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x0000200F, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -554,7 +554,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_MPX_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x0000200F, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -566,7 +566,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_MXI_BASE; + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x0000200F, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -579,7 +579,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosqon); /* QoS Register (CCI-AXI) */ - axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUS0_BASE; + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002001, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -591,7 +591,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_SYX2_BASE; + axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x0000200F, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -603,7 +603,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUR_BASE; + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002001, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -615,7 +615,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUDS_BASE; + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002001, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -627,7 +627,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUM_BASE; + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002001, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -639,7 +639,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MXI_BASE; + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; writel(0x00000002, &axi_qos->qosconf); writel(0x0000200F, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -651,7 +651,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUS1_BASE; + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002001, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -663,7 +663,7 @@ void qos_init(void) writel(0x00000000, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUMP_BASE; + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002001, &axi_qos->qosctset0); writel(0x00002009, &axi_qos->qosctset1); @@ -676,7 +676,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosqon); /* QoS Register (Media-AXI) */ - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_JPR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002018, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -685,7 +685,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_JPW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002018, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -694,7 +694,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU0R_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0R_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002018, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -703,7 +703,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU0W_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0W_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002018, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -712,7 +712,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU1R_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1R_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002018, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -721,7 +721,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU1W_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1W_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002018, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -730,7 +730,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_TDMR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002018, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -739,7 +739,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_TDMW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002018, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -748,7 +748,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0CR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002018, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -757,7 +757,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0CW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002018, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -766,7 +766,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1CR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002018, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -775,7 +775,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1CW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002018, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -784,7 +784,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002018, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -793,7 +793,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002018, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -802,7 +802,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002018, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -811,7 +811,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002018, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -820,7 +820,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VIN0W_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -829,7 +829,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0R_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -838,7 +838,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0W_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -847,7 +847,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP0R_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -856,7 +856,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP0W_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -865,7 +865,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMSR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -874,7 +874,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMSW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -883,7 +883,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1R_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -892,7 +892,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1W_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -901,7 +901,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP1R_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -910,7 +910,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP1W_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -919,7 +919,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMRR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -928,7 +928,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMRW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -937,7 +937,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP2R_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2R_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -946,7 +946,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP2W_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2W_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -955,7 +955,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD0R_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -964,7 +964,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD0W_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -973,7 +973,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD1R_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -982,7 +982,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD1W_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -991,7 +991,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU0R_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -1000,7 +1000,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU0W_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -1009,7 +1009,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU1R_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1R_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -1018,7 +1018,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU1W_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1W_BASE; writel(0x00000000, &axi_qos->qosconf); writel(0x0000200C, &axi_qos->qosctset0); writel(0x00000001, &axi_qos->qosreqctr); @@ -1027,7 +1027,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0CR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002007, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1036,7 +1036,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0CW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002007, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1045,7 +1045,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0VR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002007, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1054,7 +1054,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0VW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002007, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1063,7 +1063,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VPC0R_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002007, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1072,7 +1072,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1CR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002007, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1081,7 +1081,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1CW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002007, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1090,7 +1090,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1VR_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VR_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002007, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1099,7 +1099,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1VW_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VW_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002007, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); @@ -1108,7 +1108,7 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); - axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VPC1R_BASE; + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC1R_BASE; writel(0x00000001, &axi_qos->qosconf); writel(0x00002007, &axi_qos->qosctset0); writel(0x00000020, &axi_qos->qosreqctr); diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index 9efc355da..ef88314f7 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -16,17 +16,14 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_USB_EHCI_EXYNOS int board_usb_init(int index, enum usb_init_type init) { - struct exynos5_gpio_part1 *gpio = (struct exynos5_gpio_part1 *) - samsung_get_base_gpio_part1(); - /* Configure gpios for usb 3503 hub: * disconnect, toggle reset and connect */ - s5p_gpio_direction_output(&gpio->d1, 7, 0); - s5p_gpio_direction_output(&gpio->x3, 5, 0); + gpio_direction_output(EXYNOS5_GPIO_D17, 0); + gpio_direction_output(EXYNOS5_GPIO_X35, 0); - s5p_gpio_direction_output(&gpio->x3, 5, 1); - s5p_gpio_direction_output(&gpio->d1, 7, 1); + gpio_direction_output(EXYNOS5_GPIO_X35, 1); + gpio_direction_output(EXYNOS5_GPIO_D17, 1); return 0; } diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile index 7d2bb8c4a..41d0cc381 100644 --- a/board/samsung/common/Makefile +++ b/board/samsung/common/Makefile @@ -7,7 +7,6 @@ obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o obj-$(CONFIG_THOR_FUNCTION) += thor.o -obj-$(CONFIG_CMD_USB_MASS_STORAGE) += ums.o obj-$(CONFIG_MISC_COMMON) += misc.o ifndef CONFIG_SPL_BUILD diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 3ff428978..03106fdb9 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -116,12 +116,14 @@ static int check_keys(void) * 4 BOOT_MODE_EXIT */ static char * -mode_name[BOOT_MODE_EXIT + 1] = { - "DEVICE", - "THOR", - "UMS", - "DFU", - "EXIT" +mode_name[BOOT_MODE_EXIT + 1][2] = { + {"DEVICE", ""}, + {"THOR", "thor"}, + {"UMS", "ums"}, + {"DFU", "dfu"}, + {"GPT", "gpt"}, + {"ENV", "env"}, + {"EXIT", ""}, }; static char * @@ -130,18 +132,20 @@ mode_info[BOOT_MODE_EXIT + 1] = { "downloader", "mass storage", "firmware update", + "restore", + "default", "and run normal boot" }; -#define MODE_CMD_ARGC 4 - static char * -mode_cmd[BOOT_MODE_EXIT + 1][MODE_CMD_ARGC] = { - {"", "", "", ""}, - {"thor", "0", "mmc", "0"}, - {"ums", "0", "mmc", "0"}, - {"dfu", "0", "mmc", "0"}, - {"", "", "", ""}, +mode_cmd[BOOT_MODE_EXIT + 1] = { + "", + "thor 0 mmc 0", + "ums 0 mmc 0", + "dfu 0 mmc 0", + "gpt write mmc 0 $partitions", + "env default -a; saveenv", + "", }; static void display_board_info(void) @@ -182,11 +186,10 @@ static void display_board_info(void) static int mode_leave_menu(int mode) { char *exit_option; - char *exit_boot = "boot"; + char *exit_reset = "reset"; char *exit_back = "back"; cmd_tbl_t *cmd; int cmd_result; - int cmd_repeatable; int leave; lcd_clear(); @@ -200,31 +203,29 @@ static int mode_leave_menu(int mode) leave = 0; break; default: - cmd = find_cmd(mode_cmd[mode][0]); + cmd = find_cmd(mode_name[mode][1]); if (cmd) { - printf("Enter: %s %s\n", mode_name[mode], + printf("Enter: %s %s\n", mode_name[mode][0], mode_info[mode]); - lcd_printf("\n\n\t%s %s\n", mode_name[mode], + lcd_printf("\n\n\t%s %s\n", mode_name[mode][0], mode_info[mode]); lcd_puts("\n\tDo not turn off device before finish!\n"); - cmd_result = cmd_process(0, MODE_CMD_ARGC, - *(mode_cmd + mode), - &cmd_repeatable, NULL); + cmd_result = run_command(mode_cmd[mode], 0); if (cmd_result == CMD_RET_SUCCESS) { printf("Command finished\n"); lcd_clear(); lcd_printf("\n\n\t%s finished\n", - mode_name[mode]); + mode_name[mode][0]); - exit_option = exit_boot; + exit_option = exit_reset; leave = 1; } else { printf("Command error\n"); lcd_clear(); lcd_printf("\n\n\t%s command error\n", - mode_name[mode]); + mode_name[mode][0]); exit_option = exit_back; leave = 0; @@ -260,11 +261,11 @@ static void display_download_menu(int mode) selection[mode] = "[=>]"; lcd_clear(); - lcd_printf("\n\t\tDownload Mode Menu\n"); + lcd_printf("\n\n\t\tDownload Mode Menu\n\n"); for (i = 0; i <= BOOT_MODE_EXIT; i++) lcd_printf("\t%s %s - %s\n\n", selection[i], - mode_name[i], + mode_name[i][0], mode_info[i]); } @@ -273,10 +274,38 @@ static void download_menu(void) int mode = 0; int last_mode = 0; int run; - int key; + int key = 0; + int timeout = 15; /* sec */ + int i; display_download_menu(mode); + lcd_puts("\n"); + + /* Start count if no key is pressed */ + while (check_keys()) + continue; + + while (timeout--) { + lcd_printf("\r\tNormal boot will start in: %2.d seconds.", + timeout); + + /* about 1000 ms in for loop */ + for (i = 0; i < 10; i++) { + mdelay(100); + key = check_keys(); + if (key) + break; + } + if (key) + break; + } + + if (!key) { + lcd_clear(); + return; + } + while (1) { run = 0; @@ -284,7 +313,7 @@ static void download_menu(void) display_download_menu(mode); last_mode = mode; - mdelay(100); + mdelay(200); key = check_keys(); switch (key) { @@ -305,7 +334,7 @@ static void download_menu(void) if (run) { if (mode_leave_menu(mode)) - break; + run_command("reset", 0); display_download_menu(mode); } @@ -314,45 +343,6 @@ static void download_menu(void) lcd_clear(); } -static void display_mode_info(void) -{ - lcd_position_cursor(4, 4); - lcd_printf("%s\n", U_BOOT_VERSION); - lcd_puts("\nDownload Mode Menu\n"); -#ifdef CONFIG_SYS_BOARD - lcd_printf("Board name: %s\n", CONFIG_SYS_BOARD); -#endif - lcd_printf("Press POWER KEY to display MENU options."); -} - -static int boot_menu(void) -{ - int key = 0; - int timeout = 10; - - display_mode_info(); - - while (timeout--) { - lcd_printf("\rNormal boot will start in: %d seconds.", timeout); - mdelay(1000); - - key = key_pressed(KEY_POWER); - if (key) - break; - } - - lcd_clear(); - - /* If PWR pressed - show download menu */ - if (key) { - printf("Power pressed - go to download menu\n"); - download_menu(); - printf("Download mode exit.\n"); - } - - return 0; -} - void check_boot_mode(void) { int pwr_key; @@ -365,7 +355,7 @@ void check_boot_mode(void) power_key_pressed(KEY_PWR_INTERRUPT_REG); if (key_pressed(KEY_VOLUMEUP)) - boot_menu(); + download_menu(); else if (key_pressed(KEY_VOLUMEDOWN)) mode_leave_menu(BOOT_MODE_THOR); } diff --git a/board/samsung/common/ums.c b/board/samsung/common/ums.c deleted file mode 100644 index cebabe920..000000000 --- a/board/samsung/common/ums.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (C) 2013 Samsung Electronics - * Lukasz Majewski <l.majewski@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <usb_mass_storage.h> -#include <part.h> - -static int ums_read_sector(struct ums *ums_dev, - ulong start, lbaint_t blkcnt, void *buf) -{ - block_dev_desc_t *block_dev = &ums_dev->mmc->block_dev; - lbaint_t blkstart = start + ums_dev->start_sector; - int dev_num = block_dev->dev; - - return block_dev->block_read(dev_num, blkstart, blkcnt, buf); -} - -static int ums_write_sector(struct ums *ums_dev, - ulong start, lbaint_t blkcnt, const void *buf) -{ - block_dev_desc_t *block_dev = &ums_dev->mmc->block_dev; - lbaint_t blkstart = start + ums_dev->start_sector; - int dev_num = block_dev->dev; - - return block_dev->block_write(dev_num, blkstart, blkcnt, buf); -} - -static struct ums ums_dev = { - .read_sector = ums_read_sector, - .write_sector = ums_write_sector, - .name = "UMS disk", -}; - -static struct ums *ums_disk_init(struct mmc *mmc) -{ - uint64_t mmc_end_sector = mmc->capacity / SECTOR_SIZE; - uint64_t ums_end_sector = UMS_NUM_SECTORS + UMS_START_SECTOR; - - if (!mmc_end_sector) { - error("MMC capacity is not valid"); - return NULL; - } - - ums_dev.mmc = mmc; - - if (ums_end_sector <= mmc_end_sector) { - ums_dev.start_sector = UMS_START_SECTOR; - if (UMS_NUM_SECTORS) - ums_dev.num_sectors = UMS_NUM_SECTORS; - else - ums_dev.num_sectors = mmc_end_sector - UMS_START_SECTOR; - } else { - ums_dev.num_sectors = mmc_end_sector; - puts("UMS: defined bad disk parameters. Using default.\n"); - } - - printf("UMS: disk start sector: %#x, count: %#x\n", - ums_dev.start_sector, ums_dev.num_sectors); - - return &ums_dev; -} - -struct ums *ums_init(unsigned int dev_num) -{ - struct mmc *mmc = find_mmc_device(dev_num); - - if (!mmc || mmc_init(mmc)) - return NULL; - return ums_disk_init(mmc); -} diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index 61b9ece03..4cea63b81 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -17,8 +17,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct s5pc110_gpio *s5pc110_gpio; - u32 get_board_rev(void) { return 0; @@ -27,8 +25,6 @@ u32 get_board_rev(void) int board_init(void) { /* Set Initial global variables */ - s5pc110_gpio = (struct s5pc110_gpio *)S5PC110_GPIO_BASE; - gd->bd->bi_arch_number = MACH_TYPE_GONI; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; @@ -82,7 +78,7 @@ int board_mmc_init(bd_t *bis) int i, ret, ret_sd = 0; /* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */ - s5p_gpio_direction_output(&s5pc110_gpio->j2, 7, 1); + gpio_direction_output(S5PC110_GPIO_J27, 1); /* * MMC0 GPIO @@ -91,15 +87,15 @@ int board_mmc_init(bd_t *bis) * GPG0[2] SD_0_CDn -> Not used * GPG0[3:6] SD_0_DATA[0:3] */ - for (i = 0; i < 7; i++) { - if (i == 2) + for (i = S5PC110_GPIO_G00; i < S5PC110_GPIO_G07; i++) { + if (i == S5PC110_GPIO_G02) continue; /* GPG0[0:6] special function 2 */ - s5p_gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2); + gpio_cfg_pin(i, 0x2); /* GPG0[0:6] pull disable */ - s5p_gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); /* GPG0[0:6] drv 4x */ - s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } ret = s5p_mmc_init(0, 4); @@ -110,20 +106,20 @@ int board_mmc_init(bd_t *bis) * SD card (T_FLASH) detect and init * T_FLASH_DETECT: EINT28: GPH3[4] input mode */ - s5p_gpio_cfg_pin(&s5pc110_gpio->h3, 4, GPIO_INPUT); - s5p_gpio_set_pull(&s5pc110_gpio->h3, 4, GPIO_PULL_UP); + gpio_cfg_pin(S5PC110_GPIO_H34, S5P_GPIO_INPUT); + gpio_set_pull(S5PC110_GPIO_H34, S5P_GPIO_PULL_UP); - if (!s5p_gpio_get_value(&s5pc110_gpio->h3, 4)) { - for (i = 0; i < 7; i++) { - if (i == 2) + if (!gpio_get_value(S5PC110_GPIO_H34)) { + for (i = S5PC110_GPIO_G20; i < S5PC110_GPIO_G27; i++) { + if (i == S5PC110_GPIO_G22) continue; /* GPG2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&s5pc110_gpio->g2, i, 0x2); + gpio_cfg_pin(i, 0x2); /* GPG2[0:6] pull disable */ - s5p_gpio_set_pull(&s5pc110_gpio->g2, i, GPIO_PULL_NONE); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); /* GPG2[0:6] drv 4x */ - s5p_gpio_set_drv(&s5pc110_gpio->g2, i, GPIO_DRV_4X); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } ret_sd = s5p_mmc_init(2, 4); diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c index 379a45cc2..58821c41a 100644 --- a/board/samsung/smdk5250/exynos5-dt.c +++ b/board/samsung/smdk5250/exynos5-dt.c @@ -27,12 +27,9 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SOUND_MAX98095 static void board_enable_audio_codec(void) { - struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) - samsung_get_base_gpio_part1(); - /* Enable MAX98095 Codec */ - s5p_gpio_direction_output(&gpio1->x1, 7, 1); - s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE); + gpio_direction_output(EXYNOS5_GPIO_X17, 1); + gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE); } #endif @@ -47,19 +44,16 @@ int exynos_init(void) #ifdef CONFIG_LCD void exynos_cfg_lcd_gpio(void) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1(); - /* For Backlight */ - s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->b2, 0, 1); + gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT); + gpio_set_value(EXYNOS5_GPIO_B20, 1); /* LCD power on */ - s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->x1, 5, 1); + gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT); + gpio_set_value(EXYNOS5_GPIO_X15, 1); /* Set Hotplug detect for DP */ - s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3)); } void exynos_set_dp_phy(unsigned int onoff) diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index 28a6d9e71..014b7bdf8 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -29,12 +29,9 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SOUND_MAX98095 static void board_enable_audio_codec(void) { - struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) - samsung_get_base_gpio_part1(); - /* Enable MAX98095 Codec */ - s5p_gpio_direction_output(&gpio1->x1, 7, 1); - s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE); + gpio_direction_output(EXYNOS5_GPIO_X17, 1); + gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE); } #endif @@ -275,19 +272,17 @@ int exynos_power_init(void) #ifdef CONFIG_LCD void exynos_cfg_lcd_gpio(void) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); /* For Backlight */ - s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->b2, 0, 1); + gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT); + gpio_set_value(EXYNOS5_GPIO_B20, 1); /* LCD power on */ - s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->x1, 5, 1); + gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT); + gpio_set_value(EXYNOS5_GPIO_X15, 1); /* Set Hotplug detect for DP */ - s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3)); } void exynos_set_dp_phy(unsigned int onoff) diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index e4606ecd2..920752295 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -21,11 +21,8 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_USB_EHCI_EXYNOS static int board_usb_vbus_init(void) { - struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) - samsung_get_base_gpio_part1(); - /* Enable VBUS power switch */ - s5p_gpio_direction_output(&gpio1->x2, 6, 1); + gpio_direction_output(EXYNOS5420_GPIO_X26, 1); /* VBUS turn ON time */ mdelay(3); @@ -49,15 +46,15 @@ void cfg_lcd_gpio(void) (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1(); /* For Backlight */ - s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->b2, 0, 1); + gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_OUTPUT); + gpio_set_value(EXYNOS5420_GPIO_B20, 1); /* LCD power on */ - s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->x1, 5, 1); + gpio_cfg_pin(EXYNOS5420_GPIO_X15, S5P_GPIO_OUTPUT); + gpio_set_value(EXYNOS5420_GPIO_X15, 1); /* Set Hotplug detect for DP */ - s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_X07, S5P_GPIO_FUNC(0x3)); } vidinfo_t panel_info = { diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 860c851b2..e009564a5 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -21,11 +21,8 @@ static void smc9115_pre_init(void) { u32 smc_bw_conf, smc_bc_conf; - struct s5pc100_gpio *const gpio = - (struct s5pc100_gpio *)samsung_get_base_gpio(); - /* gpio configuration GPK0CON */ - s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + gpio_cfg_pin(S5PC100_GPIO_K00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index 81a306082..8eca35898 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -15,15 +15,13 @@ #include <asm/arch/sromc.h> DECLARE_GLOBAL_DATA_PTR; -struct exynos4_gpio_part1 *gpio1; -struct exynos4_gpio_part2 *gpio2; static void smc9115_pre_init(void) { u32 smc_bw_conf, smc_bc_conf; /* gpio configuration GPK0CON */ - s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); @@ -38,9 +36,6 @@ static void smc9115_pre_init(void) int board_init(void) { - gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; - gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; - smc9115_pre_init(); gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); @@ -103,21 +98,21 @@ int board_mmc_init(bd_t *bis) * GPK2[2] SD_2_CDn * GPK2[3:6] SD_2_DATA[0:3](2) */ - for (i = 0; i < 7; i++) { + for (i = EXYNOS4_GPIO_K20; i < EXYNOS4_GPIO_K27; i++) { /* GPK2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2)); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); /* GPK2[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); + gpio_set_drv(i, S5P_GPIO_DRV_4X); /* GPK2[0:1] pull disable */ - if (i == 0 || i == 1) { - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); + if (i == EXYNOS4_GPIO_K20 || i == EXYNOS4_GPIO_K21) { + gpio_set_pull(i, S5P_GPIO_PULL_NONE); continue; } /* GPK2[2:6] pull up */ - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP); + gpio_set_pull(i, S5P_GPIO_PULL_UP); } err = s5p_mmc_init(2, 4); return err; diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index ab0ad1d65..fec72d4c5 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -54,8 +54,6 @@ int exynos_init(void) void i2c_init_board(void) { int err; - struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); /* I2C_5 -> PMIC */ err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE); @@ -65,8 +63,8 @@ void i2c_init_board(void) } /* I2C_8 -> FG */ - s5p_gpio_direction_output(&gpio2->y4, 0, 1); - s5p_gpio_direction_output(&gpio2->y4, 1, 1); + gpio_direction_output(EXYNOS4_GPIO_Y40, 1); + gpio_direction_output(EXYNOS4_GPIO_Y41, 1); } static void trats_low_power_mode(void) @@ -347,21 +345,19 @@ int exynos_power_init(void) static unsigned int get_hw_revision(void) { - struct exynos4_gpio_part1 *gpio = - (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); int hwrev = 0; int i; /* hw_rev[3:0] == GPE1[3:0] */ - for (i = 0; i < 4; i++) { - s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT); - s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE); + for (i = EXYNOS4_GPIO_E10; i < EXYNOS4_GPIO_E14; i++) { + gpio_cfg_pin(i, S5P_GPIO_INPUT); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); } udelay(1); for (i = 0; i < 4; i++) - hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i); + hwrev |= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i); debug("hwrev 0x%x\n", hwrev); @@ -442,11 +438,8 @@ int g_dnl_board_usb_cable_connected(void) static void pmic_reset(void) { - struct exynos4_gpio_part2 *gpio = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - - s5p_gpio_direction_output(&gpio->x0, 7, 1); - s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE); + gpio_direction_output(EXYNOS4_GPIO_X07, 1); + gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE); } static void board_clock_init(void) @@ -523,12 +516,9 @@ static void board_power_init(void) static void exynos_uart_init(void) { - struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ - s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP); - s5p_gpio_direction_output(&gpio2->y4, 7, 1); + gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP); + gpio_direction_output(EXYNOS4_GPIO_Y47, 1); } int exynos_early_init_f(void) @@ -544,14 +534,11 @@ int exynos_early_init_f(void) void exynos_reset_lcd(void) { - struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - - s5p_gpio_direction_output(&gpio2->y4, 5, 1); + gpio_direction_output(EXYNOS4_GPIO_Y45, 1); udelay(10000); - s5p_gpio_direction_output(&gpio2->y4, 5, 0); + gpio_direction_output(EXYNOS4_GPIO_Y45, 0); udelay(10000); - s5p_gpio_direction_output(&gpio2->y4, 5, 1); + gpio_direction_output(EXYNOS4_GPIO_Y45, 1); } int lcd_power(void) diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index 47095252a..e4987ce8b 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -25,9 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct exynos4x12_gpio_part1 *gpio1; -static struct exynos4x12_gpio_part2 *gpio2; - static unsigned int board_rev = -1; static inline u32 get_model_rev(void); @@ -37,26 +34,24 @@ static void check_hw_revision(void) int modelrev = 0; int i; - gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2(); - /* * GPM1[1:0]: MODEL_REV[1:0] * Don't set as pull-none for these N/C pin. * TRM say that it may cause unexcepted state and leakage current. * and pull-none is only for output function. */ - for (i = 0; i < 2; i++) - s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT); + for (i = EXYNOS4X12_GPIO_M10; i < EXYNOS4X12_GPIO_M12; i++) + gpio_cfg_pin(i, S5P_GPIO_INPUT); /* GPM1[5:2]: HW_REV[3:0] */ - for (i = 2; i < 6; i++) { - s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT); - s5p_gpio_set_pull(&gpio2->m1, i, GPIO_PULL_NONE); + for (i = EXYNOS4X12_GPIO_M12; i < EXYNOS4X12_GPIO_M16; i++) { + gpio_cfg_pin(i, S5P_GPIO_INPUT); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); } /* GPM1[1:0]: MODEL_REV[1:0] */ for (i = 0; i < 2; i++) - modelrev |= (s5p_gpio_get_value(&gpio2->m1, i) << i); + modelrev |= (gpio_get_value(EXYNOS4X12_GPIO_M10 + i) << i); /* board_rev[15:8] = model */ board_rev = modelrev << 8; @@ -74,26 +69,24 @@ static inline u32 get_model_rev(void) static void board_external_gpio_init(void) { - gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2(); - /* * some pins which in alive block are connected with external pull-up * but it's default setting is pull-down. * if that pin set as input then that floated */ - s5p_gpio_set_pull(&gpio2->x0, 2, GPIO_PULL_NONE); /* PS_ALS_INT */ - s5p_gpio_set_pull(&gpio2->x0, 4, GPIO_PULL_NONE); /* TSP_nINT */ - s5p_gpio_set_pull(&gpio2->x0, 7, GPIO_PULL_NONE); /* AP_PMIC_IRQ*/ - s5p_gpio_set_pull(&gpio2->x1, 5, GPIO_PULL_NONE); /* IF_PMIC_IRQ*/ - s5p_gpio_set_pull(&gpio2->x2, 0, GPIO_PULL_NONE); /* VOL_UP */ - s5p_gpio_set_pull(&gpio2->x2, 1, GPIO_PULL_NONE); /* VOL_DOWN */ - s5p_gpio_set_pull(&gpio2->x2, 3, GPIO_PULL_NONE); /* FUEL_ALERT */ - s5p_gpio_set_pull(&gpio2->x2, 4, GPIO_PULL_NONE); /* ADC_INT */ - s5p_gpio_set_pull(&gpio2->x2, 7, GPIO_PULL_NONE); /* nPOWER */ - s5p_gpio_set_pull(&gpio2->x3, 0, GPIO_PULL_NONE); /* WPC_INT */ - s5p_gpio_set_pull(&gpio2->x3, 5, GPIO_PULL_NONE); /* OK_KEY */ - s5p_gpio_set_pull(&gpio2->x3, 7, GPIO_PULL_NONE); /* HDMI_HPD */ + gpio_set_pull(EXYNOS4X12_GPIO_X02, S5P_GPIO_PULL_NONE); /* PS_ALS_INT */ + gpio_set_pull(EXYNOS4X12_GPIO_X04, S5P_GPIO_PULL_NONE); /* TSP_nINT */ + gpio_set_pull(EXYNOS4X12_GPIO_X07, S5P_GPIO_PULL_NONE); /* AP_PMIC_IRQ*/ + gpio_set_pull(EXYNOS4X12_GPIO_X15, S5P_GPIO_PULL_NONE); /* IF_PMIC_IRQ*/ + gpio_set_pull(EXYNOS4X12_GPIO_X20, S5P_GPIO_PULL_NONE); /* VOL_UP */ + gpio_set_pull(EXYNOS4X12_GPIO_X21, S5P_GPIO_PULL_NONE); /* VOL_DOWN */ + gpio_set_pull(EXYNOS4X12_GPIO_X23, S5P_GPIO_PULL_NONE); /* FUEL_ALERT */ + gpio_set_pull(EXYNOS4X12_GPIO_X24, S5P_GPIO_PULL_NONE); /* ADC_INT */ + gpio_set_pull(EXYNOS4X12_GPIO_X27, S5P_GPIO_PULL_NONE); /* nPOWER */ + gpio_set_pull(EXYNOS4X12_GPIO_X30, S5P_GPIO_PULL_NONE); /* WPC_INT */ + gpio_set_pull(EXYNOS4X12_GPIO_X35, S5P_GPIO_PULL_NONE); /* OK_KEY */ + gpio_set_pull(EXYNOS4X12_GPIO_X37, S5P_GPIO_PULL_NONE); /* HDMI_HPD */ } #ifdef CONFIG_SYS_I2C_INIT_BOARD @@ -101,9 +94,6 @@ static void board_init_i2c(void) { int err; - gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1(); - gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2(); - /* I2C_7 */ err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE); if (err) { @@ -112,12 +102,12 @@ static void board_init_i2c(void) } /* I2C_8 */ - s5p_gpio_direction_output(&gpio1->f1, 4, 1); - s5p_gpio_direction_output(&gpio1->f1, 5, 1); + gpio_direction_output(EXYNOS4X12_GPIO_F14, 1); + gpio_direction_output(EXYNOS4X12_GPIO_F15, 1); /* I2C_9 */ - s5p_gpio_direction_output(&gpio2->m2, 1, 1); - s5p_gpio_direction_output(&gpio2->m2, 0, 1); + gpio_direction_output(EXYNOS4X12_GPIO_M21, 1); + gpio_direction_output(EXYNOS4X12_GPIO_M20, 1); } #endif @@ -125,17 +115,17 @@ static void board_init_i2c(void) int get_soft_i2c_scl_pin(void) { if (I2C_ADAP_HWNR) - return exynos4x12_gpio_get(2, m2, 1); /* I2C9 */ + return EXYNOS4X12_GPIO_M21; /* I2C9 */ else - return exynos4x12_gpio_get(1, f1, 4); /* I2C8 */ + return EXYNOS4X12_GPIO_F14; /* I2C8 */ } int get_soft_i2c_sda_pin(void) { if (I2C_ADAP_HWNR) - return exynos4x12_gpio_get(2, m2, 0); /* I2C9 */ + return EXYNOS4X12_GPIO_M20; /* I2C9 */ else - return exynos4x12_gpio_get(1, f1, 5); /* I2C8 */ + return EXYNOS4X12_GPIO_F15; /* I2C8 */ } #endif @@ -396,11 +386,9 @@ void exynos_lcd_power_on(void) { struct pmic *p = pmic_get("MAX77686_PMIC"); - gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1(); - /* LCD_2.2V_EN: GPC0[1] */ - s5p_gpio_set_pull(&gpio1->c0, 1, GPIO_PULL_UP); - s5p_gpio_direction_output(&gpio1->c0, 1, 1); + gpio_set_pull(EXYNOS4X12_GPIO_C01, S5P_GPIO_PULL_UP); + gpio_direction_output(EXYNOS4X12_GPIO_C01, 1); /* LDO25 VCC_3.1V_LCD */ pmic_probe(p); @@ -410,12 +398,10 @@ void exynos_lcd_power_on(void) void exynos_reset_lcd(void) { - gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1(); - /* reset lcd */ - s5p_gpio_direction_output(&gpio1->f2, 1, 0); + gpio_direction_output(EXYNOS4X12_GPIO_F21, 0); udelay(10); - s5p_gpio_set_value(&gpio1->f2, 1, 1); + gpio_set_value(EXYNOS4X12_GPIO_F21, 1); } void exynos_lcd_misc_init(vidinfo_t *vid) diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 8e49195fe..47e7f538d 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -27,8 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; -struct exynos4_gpio_part1 *gpio1; -struct exynos4_gpio_part2 *gpio2; unsigned int board_rev; u32 get_board_rev(void) @@ -305,35 +303,35 @@ void exynos_cfg_lcd_gpio(void) for (i = 0; i < 8; i++) { /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */ - s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS4_GPIO_F00 + i, S5P_GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS4_GPIO_F10 + i, S5P_GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS4_GPIO_F20 + i, S5P_GPIO_FUNC(2)); /* pull-up/down disable */ - s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE); - s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE); - s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE); + gpio_set_pull(EXYNOS4_GPIO_F00 + i, S5P_GPIO_PULL_NONE); + gpio_set_pull(EXYNOS4_GPIO_F10 + i, S5P_GPIO_PULL_NONE); + gpio_set_pull(EXYNOS4_GPIO_F20 + i, S5P_GPIO_PULL_NONE); /* drive strength to max (24bit) */ - s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW); - s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW); - s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW); + gpio_set_drv(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_4X); + gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW); + gpio_set_drv(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_4X); + gpio_set_rate(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_SLOW); + gpio_set_drv(EXYNOS4_GPIO_F20 + i, S5P_GPIO_DRV_4X); + gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW); } - for (i = 0; i < f3_end; i++) { + for (i = EXYNOS4_GPIO_F30; i < (EXYNOS4_GPIO_F30 + f3_end); i++) { /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */ - s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2)); + gpio_cfg_pin(i, S5P_GPIO_FUNC(2)); /* pull-up/down disable */ - s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); /* drive strength to max (24bit) */ - s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW); + gpio_set_drv(i, S5P_GPIO_DRV_4X); + gpio_set_rate(i, S5P_GPIO_DRV_SLOW); } /* gpio pad configuration for LCD reset. */ - s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT); + gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT); spi_init(); } @@ -345,11 +343,11 @@ int mipi_power(void) void exynos_reset_lcd(void) { - s5p_gpio_set_value(&gpio2->y4, 5, 1); + gpio_set_value(EXYNOS4_GPIO_Y45, 1); udelay(10000); - s5p_gpio_set_value(&gpio2->y4, 5, 0); + gpio_set_value(EXYNOS4_GPIO_Y45, 0); udelay(10000); - s5p_gpio_set_value(&gpio2->y4, 5, 1); + gpio_set_value(EXYNOS4_GPIO_Y45, 1); udelay(100); } @@ -379,9 +377,6 @@ void exynos_enable_ldo(unsigned int onoff) int exynos_init(void) { - gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; - gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; - gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; switch (get_hwrev()) { @@ -392,7 +387,7 @@ int exynos_init(void) * you should set it HIGH since it removes the inverter */ /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */ - s5p_gpio_direction_output(&gpio1->e3, 6, 0); + gpio_direction_output(EXYNOS4_GPIO_E36, 0); break; default: /* @@ -400,7 +395,7 @@ int exynos_init(void) * But set it as HIGH to ensure */ /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */ - s5p_gpio_direction_output(&gpio1->e1, 3, 1); + gpio_direction_output(EXYNOS4_GPIO_E13, 1); break; } diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 7e8731bb3..2782bcc2a 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -128,12 +128,6 @@ do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) button = 0; gpio_free(gpio); - if (!button) { - /* LED0 - RED=1: GPIO2_0 2*32 = 64 */ - gpio_request(BOARD_DFU_BUTTON_LED, ""); - gpio_direction_output(BOARD_DFU_BUTTON_LED, 1); - gpio_set_value(BOARD_DFU_BUTTON_LED, 1); - } return button; } @@ -144,6 +138,46 @@ U_BOOT_CMD( "" ); #endif +/* + * This command sets led + * Input - name of led + * value of led + * Returns - 1 if input does not match + * 0 if led was set + */ +static int +do_setled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int gpio = 0; + if (argc != 3) + goto exit; +#if defined(BOARD_STATUS_LED) + if (!strcmp(argv[1], "stat")) + gpio = BOARD_STATUS_LED; +#endif +#if defined(BOARD_DFU_BUTTON_LED) + if (!strcmp(argv[1], "dfu")) + gpio = BOARD_DFU_BUTTON_LED; +#endif + /* If argument does not mach exit */ + if (gpio == 0) + goto exit; + gpio_request(gpio, ""); + gpio_direction_output(gpio, 1); + if (!strcmp(argv[2], "1")) + gpio_set_value(gpio, 1); + else + gpio_set_value(gpio, 0); + return 0; +exit: + return 1; +} + +U_BOOT_CMD( + led, CONFIG_SYS_MAXARGS, 2, do_setled, + "Set led on or off", + "dfu val - set dfu led\nled stat val - set status led" +); static int do_usertestwdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/board/siemens/dxr2/Makefile b/board/siemens/draco/Makefile index f15993216..f15993216 100644 --- a/board/siemens/dxr2/Makefile +++ b/board/siemens/draco/Makefile diff --git a/board/siemens/dxr2/board.c b/board/siemens/draco/board.c index 38ac93d79..9be2e344f 100644 --- a/board/siemens/dxr2/board.c +++ b/board/siemens/draco/board.c @@ -1,5 +1,5 @@ /* - * Board functions for TI AM335X based dxr2 board + * Board functions for TI AM335X based draco board * (C) Copyright 2013 Siemens Schweiz AG * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. * @@ -37,13 +37,27 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SPL_BUILD -static struct dxr2_baseboard_id __attribute__((section(".data"))) settings; -/* @303MHz-i0 */ +static struct draco_baseboard_id __attribute__((section(".data"))) settings; + +#if DDR_PLL_FREQ == 303 +/* Default@303MHz-i0 */ +const struct ddr3_data ddr3_default = { + 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F, + 0x0079, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32, + 0x0000093B, 0x0000014A, + "default name @303MHz \0", + "default marking \0", +}; +#elif DDR_PLL_FREQ == 400 +/* Default@400MHz-i0 */ const struct ddr3_data ddr3_default = { - 0x33524444, 0x56312e34, 0x0080, 0x0000, 0x0038, 0x003E, 0x00A4, - 0x0075, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32, + 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab, + 0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232, 0x00000618, 0x0000014A, + "default name @400MHz \0", + "default marking \0", }; +#endif static void set_default_ddr3_timings(void) { @@ -53,8 +67,12 @@ static void set_default_ddr3_timings(void) static void print_ddr3_timings(void) { - printf("\n\nDDR3 Timing parameters:\n"); - printf("Diff Eeprom Default\n"); + printf("\nDDR3\n"); + printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ); + printf("device:\t\t%s\n", settings.ddr3.manu_name); + printf("marking:\t%s\n", settings.ddr3.manu_marking); + printf("timing parameters\n"); + printf("diff\teeprom\tdefault\n"); PRINTARGS(magic); PRINTARGS(version); PRINTARGS(ddr3_sratio); @@ -78,9 +96,9 @@ static void print_ddr3_timings(void) static void print_chip_data(void) { - printf("\n"); - printf("Device: '%s'\n", settings.chip.sdevname); - printf("HW version: '%s'\n", settings.chip.shwver); + printf("\nCPU BOARD\n"); + printf("device: \t'%s'\n", settings.chip.sdevname); + printf("hw version: \t'%s'\n", settings.chip.shwver); } #endif /* CONFIG_SPL_BUILD */ @@ -112,20 +130,18 @@ static int read_eeprom(void) printf("Using DDR3 settings from EEPROM\n"); } else { if (ddr3_default.magic != settings.ddr3.magic) - printf("Error: No valid DDR3 data in eeprom.\n"); + printf("Warning: No valid DDR3 data in eeprom.\n"); if (ddr3_default.version != settings.ddr3.version) - printf("Error: DDR3 data version does not match.\n"); + printf("Warning: DDR3 data version does not match.\n"); printf("Using default settings\n"); set_default_ddr3_timings(); } - if (MAGIC_CHIP == settings.chip.magic) { - printf("Valid chip data in eeprom\n"); + if (MAGIC_CHIP == settings.chip.magic) print_chip_data(); - } else { - printf("Error: No chip data in eeprom\n"); - } + else + printf("Warning: No chip data in eeprom\n"); print_ddr3_timings(); #endif @@ -135,48 +151,48 @@ static int read_eeprom(void) #ifdef CONFIG_SPL_BUILD static void board_init_ddr(void) { -struct emif_regs dxr2_ddr3_emif_reg_data = { +struct emif_regs draco_ddr3_emif_reg_data = { .zq_config = 0x50074BE4, }; -struct ddr_data dxr2_ddr3_data = { +struct ddr_data draco_ddr3_data = { }; -struct cmd_control dxr2_ddr3_cmd_ctrl_data = { +struct cmd_control draco_ddr3_cmd_ctrl_data = { }; -struct ctrl_ioregs dxr2_ddr3_ioregs = { +struct ctrl_ioregs draco_ddr3_ioregs = { }; /* pass values from eeprom */ - dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1; - dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2; - dxr2_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3; - dxr2_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 = + draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1; + draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2; + draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3; + draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 = settings.ddr3.emif_ddr_phy_ctlr_1; - dxr2_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config; - dxr2_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl; - - dxr2_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0; - dxr2_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0; - dxr2_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0; - dxr2_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0; - - dxr2_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio; - dxr2_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout; - dxr2_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio; - dxr2_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout; - dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio; - dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout; - - dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val, - dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val, - dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val, - dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val, - dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val, - - config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data, - &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0); + draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config; + draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl; + + draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0; + draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0; + draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0; + draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0; + + draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio; + draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout; + draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio; + draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout; + draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio; + draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout; + + draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val, + draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val, + draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val, + draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val, + draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val, + + config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data, + &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0); } static void spl_siemens_board_init(void) diff --git a/board/siemens/dxr2/board.h b/board/siemens/draco/board.h index abf543232..ff8ab764c 100644 --- a/board/siemens/dxr2/board.h +++ b/board/siemens/draco/board.h @@ -22,24 +22,26 @@ #define MAGIC_CHIP 0x50494843 /* Automatic generated definition */ -/* Wed, 18 Sep 2013 18:58:27 +0200 */ -/* From file: draco/ddr3-data-micron-v2.txt */ +/* Wed, 16 Apr 2014 16:50:41 +0200 */ +/* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */ struct ddr3_data { unsigned int magic; /* 0x33524444 */ - unsigned int version; /* 0x56312e34 */ - unsigned short int ddr3_sratio; /* 0x0100 */ - unsigned short int iclkout; /* 0x0001 */ + unsigned int version; /* 0x56312e35 */ + unsigned short int ddr3_sratio; /* 0x0080 */ + unsigned short int iclkout; /* 0x0000 */ unsigned short int dt0rdsratio0; /* 0x003A */ - unsigned short int dt0wdsratio0; /* 0x008A */ - unsigned short int dt0fwsratio0; /* 0x010B */ - unsigned short int dt0wrsratio0; /* 0x00C4 */ + unsigned short int dt0wdsratio0; /* 0x003F */ + unsigned short int dt0fwsratio0; /* 0x009F */ + unsigned short int dt0wrsratio0; /* 0x0079 */ unsigned int sdram_tim1; /* 0x0888A39B */ unsigned int sdram_tim2; /* 0x26247FDA */ unsigned int sdram_tim3; /* 0x501F821F */ unsigned int emif_ddr_phy_ctlr_1; /* 0x00100206 */ - unsigned int sdram_config; /* 0x61C04AB2 */ - unsigned int ref_ctrl; /* 0x00000618 */ - unsigned int ioctr_val; /* 0x0000018B */ + unsigned int sdram_config; /* 0x61A44A32 */ + unsigned int ref_ctrl; /* 0x0000093B */ + unsigned int ioctr_val; /* 0x0000014A */ + char manu_name[32]; /* "default@303MHz \0" */ + char manu_marking[32]; /* "default \0" */ }; struct chip_data { @@ -48,7 +50,7 @@ struct chip_data { char shwver[7]; }; -struct dxr2_baseboard_id { +struct draco_baseboard_id { struct ddr3_data ddr3; struct chip_data chip; }; diff --git a/board/siemens/dxr2/mux.c b/board/siemens/draco/mux.c index f2314b5d3..eaa3c7079 100644 --- a/board/siemens/dxr2/mux.c +++ b/board/siemens/draco/mux.c @@ -1,5 +1,5 @@ /* - * pinmux setup for siemens dxr2 board + * pinmux setup for siemens draco board * * (C) Copyright 2013 Siemens Schweiz AG * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c index 98083d52c..64e69dc93 100644 --- a/board/siemens/pxm2/board.c +++ b/board/siemens/pxm2/board.c @@ -70,11 +70,11 @@ struct cmd_control pxm2_ddr3_cmd_ctrl_data = { }; const struct ctrl_ioregs ioregs = { - .cm0ioctl = DXR2_IOCTRL_VAL, - .cm1ioctl = DXR2_IOCTRL_VAL, - .cm2ioctl = DXR2_IOCTRL_VAL, - .dt0ioctl = DXR2_IOCTRL_VAL, - .dt1ioctl = DXR2_IOCTRL_VAL, + .cm0ioctl = DDR_IOCTRL_VAL, + .cm1ioctl = DDR_IOCTRL_VAL, + .cm2ioctl = DDR_IOCTRL_VAL, + .dt0ioctl = DDR_IOCTRL_VAL, + .dt1ioctl = DDR_IOCTRL_VAL, }; config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data, diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c index e0ada3f6a..1752df2c4 100644 --- a/board/siemens/rut/board.c +++ b/board/siemens/rut/board.c @@ -400,7 +400,7 @@ static int conf_disp_pll(int m, int n) #if defined(DISPL_PLL_SPREAD_SPECTRUM) writel(0x64, &cmwkup->resv6[3]); /* 0x50 */ writel(0x800, &cmwkup->resv6[2]); /* 0x4c */ - writel(readl(&cmwkup->clkmoddplldisp) | (1 << 12), + writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK, &cmwkup->clkmoddplldisp); /* 0x98 */ #endif return 0; diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile new file mode 100644 index 000000000..cbf8f086a --- /dev/null +++ b/board/sunxi/Makefile @@ -0,0 +1,13 @@ +# +# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net> +# +# Based on some other board Makefile +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y += board.o +obj-$(CONFIG_SUNXI_GMAC) += gmac.o +obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o diff --git a/board/sunxi/board.c b/board/sunxi/board.c new file mode 100644 index 000000000..b05d0b9b1 --- /dev/null +++ b/board/sunxi/board.c @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * Some board init for the Allwinner A10-evb board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/arch/dram.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* add board specific code here */ +int board_init(void) +{ + int id_pfr1; + + gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); + + asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); + debug("id_pfr1: 0x%08x\n", id_pfr1); + /* Generic Timer Extension available? */ + if ((id_pfr1 >> 16) & 0xf) { + debug("Setting CNTFRQ\n"); + /* CNTFRQ == 24 MHz */ + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000)); + } + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); + + return 0; +} + +#ifdef CONFIG_GENERIC_MMC +static void mmc_pinmux_setup(int sdc) +{ + unsigned int pin; + + switch (sdc) { + case 0: + /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */ + for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + break; + + case 1: + /* CMD-PH22, CLK-PH23, D0~D3-PH24~27 : 5 */ + for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + break; + + case 2: + /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + break; + + case 3: + /* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */ + for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + break; + + default: + printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); + break; + } +} + +int board_mmc_init(bd_t *bis) +{ + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); + sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); +#if !defined (CONFIG_SPL_BUILD) && defined (CONFIG_MMC_SUNXI_SLOT_EXTRA) + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); + sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); +#endif + + return 0; +} +#endif + +#ifdef CONFIG_SPL_BUILD +void sunxi_board_init(void) +{ + unsigned long ramsize; + + printf("DRAM:"); + ramsize = sunxi_dram_init(); + printf(" %lu MiB\n", ramsize >> 20); + if (!ramsize) + hang(); +} +#endif diff --git a/board/sunxi/dram_cubietruck.c b/board/sunxi/dram_cubietruck.c new file mode 100644 index 000000000..fbcd68771 --- /dev/null +++ b/board/sunxi/dram_cubietruck.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include <common.h> +#include <asm/arch/dram.h> + +static struct dram_para dram_para = { + .clock = 432, + .type = 3, + .rank_num = 1, + .density = 4096, + .io_width = 8, + .bus_width = 32, + .cas = 9, + .zq = 0x7f, + .odt_en = 0, + .size = 2048, + .tpr0 = 0x42d899b7, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .tpr3 = 0x0, + .tpr4 = 0x1, + .tpr5 = 0x0, + .emr1 = 0x4, + .emr2 = 0x10, + .emr3 = 0x0, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c new file mode 100644 index 000000000..e48328d9e --- /dev/null +++ b/board/sunxi/gmac.c @@ -0,0 +1,32 @@ +#include <common.h> +#include <netdev.h> +#include <miiphy.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> + +int sunxi_gmac_initialize(bd_t *bis) +{ + int pin; + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* Set up clock gating */ + setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); + + /* Set MII clock */ + setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | + CCM_GMAC_CTRL_GPIT_RGMII); + + /* Configure pin mux settings for GMAC */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { + /* skip unused pins in RGMII mode */ + if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14)) + continue; + sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } + + return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII); +} diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds index a9e3d34df..2c5a0f8a1 100644 --- a/board/ti/am335x/u-boot.lds +++ b/board/ti/am335x/u-boot.lds @@ -34,6 +34,7 @@ SECTIONS .text : { *(.__image_copy_start) + *(.vectors) CPUDIR/start.o (.text*) board/ti/am335x/built-in.o (.text*) *(.text*) diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index f1951dc5e..3c8b7a5d2 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Copyright (C) 2014 O.S. Systems Software LTDA. * * Author: Fabio Estevam <fabio.estevam@freescale.com> * @@ -15,18 +16,19 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> #include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/video.h> #include <asm/io.h> #include <linux/sizes.h> #include <common.h> #include <fsl_esdhc.h> -#include <ipu_pixfmt.h> #include <mmc.h> #include <miiphy.h> #include <netdev.h> -#include <linux/fb.h> #include <phy.h> #include <input.h> +#include <i2c.h> DECLARE_GLOBAL_DATA_PTR; @@ -41,6 +43,10 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) #define ETH_PHY_RESET IMX_GPIO_NR(3, 29) @@ -210,38 +216,120 @@ int board_phy_config(struct phy_device *phydev) } #if defined(CONFIG_VIDEO_IPUV3) -static struct fb_videomode const hdmi = { - .name = "HDMI", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED +struct i2c_pads_info i2c2_pad_info = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 + | MUX_PAD_CTRL(I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(4, 13) + } }; -int board_video_skip(void) -{ - int ret; +static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = { + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSync */ + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSync */ + MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 + | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm), /* Contrast */ + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* DISP0_DRDY */ + + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, + + MX6_PAD_SD4_DAT2__GPIO2_IO10 + | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_BKLEN */ + MX6_PAD_SD4_DAT3__GPIO2_IO11 + | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_VDDEN */ +}; - ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24); +static void do_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} - if (ret) { - printf("HDMI cannot be configured: %d\n", ret); - return ret; - } +static int detect_i2c(struct display_info_t const *dev) +{ + return (0 == i2c_set_bus_num(dev->bus)) && + (0 == i2c_probe(dev->addr)); +} - imx_enable_hdmi_phy(); +static void enable_fwadapt_7wvga(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads( + fwadapt_7wvga_pads, + ARRAY_SIZE(fwadapt_7wvga_pads)); - return ret; + gpio_direction_output(IMX_GPIO_NR(2, 10), 1); + gpio_direction_output(IMX_GPIO_NR(2, 11), 1); } +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 1, + .addr = 0x10, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = detect_i2c, + .enable = enable_fwadapt_7wvga, + .mode = { + .name = "FWBADAPT-LCD-F07A-0102", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 33260, + .left_margin = 128, + .right_margin = 128, + .upper_margin = 22, + .lower_margin = 22, + .hsync_len = 1, + .vsync_len = 1, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + static void setup_display(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -254,6 +342,10 @@ static void setup_display(void) reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); writel(reg, &mxc_ccm->chsccdr); + + /* Disable LCD backlight */ + imx_iomux_v3_setup_pad(MX6_PAD_DI0_PIN4__GPIO4_IO20); + gpio_direction_input(IMX_GPIO_NR(4, 20)); } #endif /* CONFIG_VIDEO_IPUV3 */ @@ -305,6 +397,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c2_pad_info); + return 0; } diff --git a/board/xilinx/zynq/.gitignore b/board/xilinx/zynq/.gitignore new file mode 100644 index 000000000..68b8edd26 --- /dev/null +++ b/board/xilinx/zynq/.gitignore @@ -0,0 +1 @@ +ps7_init.[ch] diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index 3f19a1cd8..fd93f6317 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -6,4 +6,7 @@ # obj-y := board.o -obj-$(CONFIG_SPL_BUILD) += ps7_init.o + +# Please copy ps7_init.c/h from hw project to this directory +obj-$(CONFIG_SPL_BUILD) += \ + $(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o) diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index c8cc2bc93..258632e52 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -6,6 +6,8 @@ #include <common.h> #include <fdtdec.h> +#include <fpga.h> +#include <mmc.h> #include <netdev.h> #include <zynqpl.h> #include <asm/arch/hardware.h> @@ -13,21 +15,23 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_FPGA -xilinx_desc fpga; +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static xilinx_desc fpga; /* It can be done differently */ -xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); -xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); -xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); -xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); -xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); -xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); +static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); +static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); +static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); +static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); +static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); +static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); #endif int board_init(void) { -#ifdef CONFIG_FPGA +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) u32 idcode; idcode = zynq_slcr_get_idcode(); @@ -54,7 +58,8 @@ int board_init(void) } #endif -#ifdef CONFIG_FPGA +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) fpga_init(); fpga_add(fpga_xilinx, &fpga); #endif diff --git a/board/xilinx/zynq/ps7_init.c b/board/xilinx/zynq/ps7_init.c deleted file mode 100644 index c47da09b9..000000000 --- a/board/xilinx/zynq/ps7_init.c +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2014 Xilinx, Inc. Michal Simek - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <asm/arch/spl.h> - -__weak void ps7_init(void) -{ - puts("Please copy ps7_init.c/h from hw project\n"); -} diff --git a/board/xilinx/zynq/xil_io.h b/board/xilinx/zynq/xil_io.h new file mode 100644 index 000000000..e59a977eb --- /dev/null +++ b/board/xilinx/zynq/xil_io.h @@ -0,0 +1,13 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H + +/* + * This empty file is here because ps7_init.c exported by hw project + * has #include "xil_io.h" line. + */ + +#endif /* XIL_IO_H */ diff --git a/boards.cfg b/boards.cfg index 0497a917c..4760a1f47 100644 --- a/boards.cfg +++ b/boards.cfg @@ -47,6 +47,7 @@ Active aarch64 armv8 - armltd vexpress64 Active arc arc700 - synopsys - axs101 - Alexey Brodkin <abrodkin@synopsys.com> Active arc arc700 - synopsys <none> arcangel4 - Alexey Brodkin <abrodkin@synopsys.com> Active arc arc700 - synopsys <none> arcangel4-be - Alexey Brodkin <abrodkin@synopsys.com> +Active arc arc700 - abilis - tb100 - Alexey Brodkin <abrodkin@synopsys.com> Active arm arm1136 - armltd integrator integratorcp_cm1136 integratorcp:CM1136 Linus Walleij <linus.walleij@linaro.org> Active arm arm1136 mx31 - - imx31_phycore - - Active arm arm1136 mx31 davedenx - qong - Wolfgang Denk <wd@denx.de> @@ -102,6 +103,7 @@ Active arm arm926ejs at91 atmel at91sam9263ek Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash at91sam9263ek:AT91SAM9263,SYS_USE_NORFLASH Stelian Pop <stelian@popies.net> Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash_boot at91sam9263ek:AT91SAM9263,SYS_USE_BOOT_NORFLASH Stelian Pop <stelian@popies.net> Active arm arm926ejs at91 atmel at91sam9m10g45ek at91sam9m10g45ek_nandflash at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH Bo Shen<voice.shen@atmel.com> +Active arm arm926ejs at91 atmel at91sam9m10g45ek at91sam9m10g45ek_mmc at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_MMC Bo Shen<voice.shen@atmel.com> Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_mmc at91sam9n12ek:AT91SAM9N12,SYS_USE_MMC Josh Wu <josh.wu@atmel.com> Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_nandflash at91sam9n12ek:AT91SAM9N12,SYS_USE_NANDFLASH Josh Wu <josh.wu@atmel.com> Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_spiflash at91sam9n12ek:AT91SAM9N12,SYS_USE_SPIFLASH Josh Wu <josh.wu@atmel.com> @@ -257,10 +259,12 @@ Active arm armv7 am33xx BuR tseries Active arm armv7 am33xx BuR tseries tseries_nand tseries:SERIAL1,CONS_INDEX=1,NAND Hannes Petermaier <hannes.petermaier@br-automation.com> Active arm armv7 am33xx BuR tseries tseries_spi tseries:SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com> Active arm armv7 am33xx compulab cm_t335 cm_t335 - Igor Grinberg <grinberg@compulab.co.il> +Active arm armv7 am33xx gumstix pepper pepper - Ash Charles <ash@gumstix.com> Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com> Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel <poeschel@lemonage.de> Active arm armv7 am33xx phytec pcm051 pcm051_rev3 pcm051:REV3 Lars Poeschel <poeschel@lemonage.de> -Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier@siemens.com> +Active arm armv7 am33xx siemens draco draco - Roger Meier <r.meier@siemens.com> +Active arm armv7 am33xx siemens draco dxr2 - Roger Meier <r.meier@siemens.com> Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier@siemens.com> Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier@siemens.com> Active arm armv7 am33xx silica pengwyn pengwyn - Lothar Felten <lothar.felten@gmail.com> @@ -293,7 +297,7 @@ Active arm armv7 exynos samsung smdkv310 Active arm armv7 exynos samsung trats trats - Lukasz Majewski <l.majewski@samsung.com> Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek <p.wilczek@samsung.com> Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak <p.marczak@samsung.com> -Active arm armv7 highbank - highbank highbank - Rob Herring <rob.herring@calxeda.com> +Active arm armv7 highbank - highbank highbank - Rob Herring <robh@kernel.org> Active arm armv7 keystone ti k2hk_evm k2hk_evm - Vitaly Andrianov <vitalya@ti.com> Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <marek.vasut@gmail.com> Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg - @@ -318,6 +322,8 @@ Active arm armv7 mx6 boundary nitrogen6x Active arm armv7 mx6 boundary nitrogen6x nitrogen6s nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Eric Nelson <eric.nelson@boundarydevices.com> Active arm armv7 mx6 boundary nitrogen6x nitrogen6s1g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com> Active arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre <lsartre@adeneo-embedded.com> +Active arm armv7 mx6 embest mx6boards marsboard embestmx6boards:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH Eric Bénard <eric@eukrea.com> +Active arm armv7 mx6 embest mx6boards riotboard embestmx6boards:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC Eric Bénard <eric@eukrea.com> Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg Jason Liu <r64343@freescale.com> Active arm armv7 mx6 freescale mx6qsabreauto mx6qsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com> Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com> @@ -358,8 +364,10 @@ Active arm armv7 omap3 ti evm Active arm armv7 omap3 ti evm omap3_evm_quick_nand - - Active arm armv7 omap3 ti sdp3430 omap3_sdp3430 - Nishanth Menon <nm@ti.com> Active arm armv7 omap3 timll devkit8000 devkit8000 - Thomas Weber <weber@corscience.de> +Active arm armv7 omap4 gumstix duovero duovero - Ash Charles <ash@gumstix.com> Active arm armv7 omap4 ti panda omap4_panda - Sricharan R <r.sricharan@ti.com> Active arm armv7 omap4 ti sdp4430 omap4_sdp4430 - Sricharan R <r.sricharan@ti.com> +Active arm armv7 omap5 compulab cm_t54 cm_t54 - Dmitry Lifshitz <lifshitz@compulab.co.il> Active arm armv7 omap5 ti dra7xx dra7xx_evm dra7xx_evm:CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com> Active arm armv7 omap5 ti dra7xx dra7xx_evm_qspiboot dra7xx_evm:CONS_INDEX=1,QSPI_BOOT Lokesh Vutla <lokeshvutla@ti.com> Active arm armv7 omap5 ti dra7xx dra7xx_evm_uart3 dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT Lokesh Vutla <lokeshvutla@ti.com> @@ -370,9 +378,11 @@ Active arm armv7 rmobile renesas koelsch Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> -Active arm armv7 s5pc1xx samsung goni s5p_goni - Mateusz Zalega <m.zalega@samsung.com> +Active arm armv7 s5pc1xx samsung goni s5p_goni - Przemyslaw Marczak <p.marczak@samsung.com> Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com> Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - +Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII - +Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII - Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org> Active arm armv7 u8500 st-ericsson u8500 u8500_href - - Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com> @@ -652,6 +662,7 @@ Active powerpc mpc8260 - - cpu86 Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd@denx.de> Active powerpc mpc8260 - - cpu87 CPU87 - - Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM - +Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com> Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg@denx.de> Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher <hs@denx.de> Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher <hs@denx.de> @@ -1212,7 +1223,7 @@ Active sparc leon3 - gaisler - Active sparc leon3 - gaisler - gr_ep2s60 - - Active sparc leon3 - gaisler - gr_xc3s_1500 - - Active sparc leon3 - gaisler - grsim - - -Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 - +Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 Simon Glass <sjg@chromium.org> # The following were moved to "Orphan" in April, 2014 Orphan powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu <nyet@zumanetworks.com> Orphan powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim@musenki.com> diff --git a/common/Makefile b/common/Makefile index 7c853ae44..391a8d623 100644 --- a/common/Makefile +++ b/common/Makefile @@ -11,11 +11,29 @@ obj-y += main.o obj-y += command.o obj-y += exports.o obj-y += hash.o -obj-$(CONFIG_SYS_HUSH_PARSER) += hush.o +ifdef CONFIG_SYS_HUSH_PARSER +obj-y += cli_hush.o +endif + +# We always have this since drivers/ddr/fs/interactive.c needs it +obj-y += cli_simple.o + +obj-y += cli.o +obj-y += cli_readline.o obj-y += s_record.o obj-y += xyzModem.o obj-y += cmd_disk.o +# This option is not just y/n - it can have a numeric value +ifdef CONFIG_BOOTDELAY +obj-y += autoboot.o +endif + +# This option is not just y/n - it can have a numeric value +ifdef CONFIG_BOOT_RETRY_TIME +obj-y += bootretry.o +endif + # boards obj-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o obj-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o @@ -168,6 +186,8 @@ obj-y += cmd_usb.o obj-y += usb.o usb_hub.o obj-$(CONFIG_USB_STORAGE) += usb_storage.o endif +obj-$(CONFIG_CMD_FASTBOOT) += cmd_fastboot.o + obj-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o obj-$(CONFIG_CMD_THOR_DOWNLOAD) += cmd_thordown.o obj-$(CONFIG_CMD_XIMG) += cmd_ximg.o @@ -237,6 +257,7 @@ obj-y += console.o obj-$(CONFIG_CROS_EC) += cros_ec.o obj-y += dlmalloc.o obj-y += image.o +obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o obj-$(CONFIG_OF_LIBFDT) += image-fdt.o obj-$(CONFIG_FIT) += image-fit.o obj-$(CONFIG_FIT_SIGNATURE) += image-sig.o diff --git a/common/autoboot.c b/common/autoboot.c new file mode 100644 index 000000000..dc24cae61 --- /dev/null +++ b/common/autoboot.c @@ -0,0 +1,303 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <bootretry.h> +#include <cli.h> +#include <fdtdec.h> +#include <menu.h> +#include <post.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define MAX_DELAY_STOP_STR 32 + +#ifndef DEBUG_BOOTKEYS +#define DEBUG_BOOTKEYS 0 +#endif +#define debug_bootkeys(fmt, args...) \ + debug_cond(DEBUG_BOOTKEYS, fmt, ##args) + +/* Stored value of bootdelay, used by autoboot_command() */ +static int stored_bootdelay; + +/*************************************************************************** + * Watch for 'delay' seconds for autoboot stop or autoboot delay string. + * returns: 0 - no key string, allow autoboot 1 - got key string, abort + */ +# if defined(CONFIG_AUTOBOOT_KEYED) +static int abortboot_keyed(int bootdelay) +{ + int abort = 0; + uint64_t etime = endtick(bootdelay); + struct { + char *str; + u_int len; + int retry; + } + delaykey[] = { + { str: getenv("bootdelaykey"), retry: 1 }, + { str: getenv("bootdelaykey2"), retry: 1 }, + { str: getenv("bootstopkey"), retry: 0 }, + { str: getenv("bootstopkey2"), retry: 0 }, + }; + + char presskey[MAX_DELAY_STOP_STR]; + u_int presskey_len = 0; + u_int presskey_max = 0; + u_int i; + +#ifndef CONFIG_ZERO_BOOTDELAY_CHECK + if (bootdelay == 0) + return 0; +#endif + +# ifdef CONFIG_AUTOBOOT_PROMPT + printf(CONFIG_AUTOBOOT_PROMPT); +# endif + +# ifdef CONFIG_AUTOBOOT_DELAY_STR + if (delaykey[0].str == NULL) + delaykey[0].str = CONFIG_AUTOBOOT_DELAY_STR; +# endif +# ifdef CONFIG_AUTOBOOT_DELAY_STR2 + if (delaykey[1].str == NULL) + delaykey[1].str = CONFIG_AUTOBOOT_DELAY_STR2; +# endif +# ifdef CONFIG_AUTOBOOT_STOP_STR + if (delaykey[2].str == NULL) + delaykey[2].str = CONFIG_AUTOBOOT_STOP_STR; +# endif +# ifdef CONFIG_AUTOBOOT_STOP_STR2 + if (delaykey[3].str == NULL) + delaykey[3].str = CONFIG_AUTOBOOT_STOP_STR2; +# endif + + for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i++) { + delaykey[i].len = delaykey[i].str == NULL ? + 0 : strlen(delaykey[i].str); + delaykey[i].len = delaykey[i].len > MAX_DELAY_STOP_STR ? + MAX_DELAY_STOP_STR : delaykey[i].len; + + presskey_max = presskey_max > delaykey[i].len ? + presskey_max : delaykey[i].len; + + debug_bootkeys("%s key:<%s>\n", + delaykey[i].retry ? "delay" : "stop", + delaykey[i].str ? delaykey[i].str : "NULL"); + } + + /* In order to keep up with incoming data, check timeout only + * when catch up. + */ + do { + if (tstc()) { + if (presskey_len < presskey_max) { + presskey[presskey_len++] = getc(); + } else { + for (i = 0; i < presskey_max - 1; i++) + presskey[i] = presskey[i + 1]; + + presskey[i] = getc(); + } + } + + for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i++) { + if (delaykey[i].len > 0 && + presskey_len >= delaykey[i].len && + memcmp(presskey + presskey_len - + delaykey[i].len, delaykey[i].str, + delaykey[i].len) == 0) { + debug_bootkeys("got %skey\n", + delaykey[i].retry ? "delay" : + "stop"); + + /* don't retry auto boot */ + if (!delaykey[i].retry) + bootretry_dont_retry(); + abort = 1; + } + } + } while (!abort && get_ticks() <= etime); + + if (!abort) + debug_bootkeys("key timeout\n"); + +#ifdef CONFIG_SILENT_CONSOLE + if (abort) + gd->flags &= ~GD_FLG_SILENT; +#endif + + return abort; +} + +# else /* !defined(CONFIG_AUTOBOOT_KEYED) */ + +#ifdef CONFIG_MENUKEY +static int menukey; +#endif + +static int abortboot_normal(int bootdelay) +{ + int abort = 0; + unsigned long ts; + +#ifdef CONFIG_MENUPROMPT + printf(CONFIG_MENUPROMPT); +#else + if (bootdelay >= 0) + printf("Hit any key to stop autoboot: %2d ", bootdelay); +#endif + +#if defined CONFIG_ZERO_BOOTDELAY_CHECK + /* + * Check if key already pressed + * Don't check if bootdelay < 0 + */ + if (bootdelay >= 0) { + if (tstc()) { /* we got a key press */ + (void) getc(); /* consume input */ + puts("\b\b\b 0"); + abort = 1; /* don't auto boot */ + } + } +#endif + + while ((bootdelay > 0) && (!abort)) { + --bootdelay; + /* delay 1000 ms */ + ts = get_timer(0); + do { + if (tstc()) { /* we got a key press */ + abort = 1; /* don't auto boot */ + bootdelay = 0; /* no more delay */ +# ifdef CONFIG_MENUKEY + menukey = getc(); +# else + (void) getc(); /* consume input */ +# endif + break; + } + udelay(10000); + } while (!abort && get_timer(ts) < 1000); + + printf("\b\b\b%2d ", bootdelay); + } + + putc('\n'); + +#ifdef CONFIG_SILENT_CONSOLE + if (abort) + gd->flags &= ~GD_FLG_SILENT; +#endif + + return abort; +} +# endif /* CONFIG_AUTOBOOT_KEYED */ + +static int abortboot(int bootdelay) +{ +#ifdef CONFIG_AUTOBOOT_KEYED + return abortboot_keyed(bootdelay); +#else + return abortboot_normal(bootdelay); +#endif +} + +static void process_fdt_options(const void *blob) +{ +#if defined(CONFIG_OF_CONTROL) + ulong addr; + + /* Add an env variable to point to a kernel payload, if available */ + addr = fdtdec_get_config_int(gd->fdt_blob, "kernel-offset", 0); + if (addr) + setenv_addr("kernaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr)); + + /* Add an env variable to point to a root disk, if available */ + addr = fdtdec_get_config_int(gd->fdt_blob, "rootdisk-offset", 0); + if (addr) + setenv_addr("rootaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr)); +#endif /* CONFIG_OF_CONTROL */ +} + +const char *bootdelay_process(void) +{ + char *s; + int bootdelay; +#ifdef CONFIG_BOOTCOUNT_LIMIT + unsigned long bootcount = 0; + unsigned long bootlimit = 0; +#endif /* CONFIG_BOOTCOUNT_LIMIT */ + +#ifdef CONFIG_BOOTCOUNT_LIMIT + bootcount = bootcount_load(); + bootcount++; + bootcount_store(bootcount); + setenv_ulong("bootcount", bootcount); + bootlimit = getenv_ulong("bootlimit", 10, 0); +#endif /* CONFIG_BOOTCOUNT_LIMIT */ + + s = getenv("bootdelay"); + bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY; + +#ifdef CONFIG_OF_CONTROL + bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay", + bootdelay); +#endif + + debug("### main_loop entered: bootdelay=%d\n\n", bootdelay); + +#if defined(CONFIG_MENU_SHOW) + bootdelay = menu_show(bootdelay); +#endif + bootretry_init_cmd_timeout(); + +#ifdef CONFIG_POST + if (gd->flags & GD_FLG_POSTFAIL) { + s = getenv("failbootcmd"); + } else +#endif /* CONFIG_POST */ +#ifdef CONFIG_BOOTCOUNT_LIMIT + if (bootlimit && (bootcount > bootlimit)) { + printf("Warning: Bootlimit (%u) exceeded. Using altbootcmd.\n", + (unsigned)bootlimit); + s = getenv("altbootcmd"); + } else +#endif /* CONFIG_BOOTCOUNT_LIMIT */ + s = getenv("bootcmd"); + + process_fdt_options(gd->fdt_blob); + stored_bootdelay = bootdelay; + + return s; +} + +void autoboot_command(const char *s) +{ + debug("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>"); + + if (stored_bootdelay != -1 && s && !abortboot(stored_bootdelay)) { +#if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC) + int prev = disable_ctrlc(1); /* disable Control C checking */ +#endif + + run_command_list(s, -1, 0); + +#if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC) + disable_ctrlc(prev); /* restore Control C checking */ +#endif + } + +#ifdef CONFIG_MENUKEY + if (menukey == CONFIG_MENUKEY) { + s = getenv("menucmd"); + if (s) + run_command_list(s, -1, 0); + } +#endif /* CONFIG_MENUKEY */ +} diff --git a/common/board_r.c b/common/board_r.c index d1f0aa9b1..602a23938 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -704,17 +704,6 @@ static int initr_kbd(void) } #endif -#ifdef CONFIG_MODEM_SUPPORT -static int initr_modem(void) -{ - /* TODO: with new initcalls, move this into the driver */ - extern int do_mdm_init; - - do_mdm_init = gd->do_mdm_init; - return 0; -} -#endif - static int run_main_loop(void) { #ifdef CONFIG_SANDBOX @@ -929,9 +918,6 @@ init_fnc_t init_sequence_r[] = { #ifdef CONFIG_PS2KBD initr_kbd, #endif -#ifdef CONFIG_MODEM_SUPPORT - initr_modem, -#endif run_main_loop, }; diff --git a/common/bootretry.c b/common/bootretry.c new file mode 100644 index 000000000..2d82798cd --- /dev/null +++ b/common/bootretry.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <bootretry.h> +#include <cli.h> +#include <errno.h> +#include <watchdog.h> + +#ifndef CONFIG_BOOT_RETRY_MIN +#define CONFIG_BOOT_RETRY_MIN CONFIG_BOOT_RETRY_TIME +#endif + +static uint64_t endtime; /* must be set, default is instant timeout */ +static int retry_time = -1; /* -1 so can call readline before main_loop */ + +/*************************************************************************** + * initialize command line timeout + */ +void bootretry_init_cmd_timeout(void) +{ + char *s = getenv("bootretry"); + + if (s != NULL) + retry_time = (int)simple_strtol(s, NULL, 10); + else + retry_time = CONFIG_BOOT_RETRY_TIME; + + if (retry_time >= 0 && retry_time < CONFIG_BOOT_RETRY_MIN) + retry_time = CONFIG_BOOT_RETRY_MIN; +} + +/*************************************************************************** + * reset command line timeout to retry_time seconds + */ +void bootretry_reset_cmd_timeout(void) +{ + endtime = endtick(retry_time); +} + +int bootretry_tstc_timeout(void) +{ + while (!tstc()) { /* while no incoming data */ + if (retry_time >= 0 && get_ticks() > endtime) + return -ETIMEDOUT; + WATCHDOG_RESET(); + } + + return 0; +} + +void bootretry_dont_retry(void) +{ + retry_time = -1; +} diff --git a/common/cli.c b/common/cli.c new file mode 100644 index 000000000..ea6bfb316 --- /dev/null +++ b/common/cli.c @@ -0,0 +1,194 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Add to readline cmdline-editing by + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <cli.h> +#include <cli_hush.h> +#include <fdtdec.h> +#include <malloc.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Run a command using the selected parser. + * + * @param cmd Command to run + * @param flag Execution flags (CMD_FLAG_...) + * @return 0 on success, or != 0 on error. + */ +int run_command(const char *cmd, int flag) +{ +#ifndef CONFIG_SYS_HUSH_PARSER + /* + * cli_run_command can return 0 or 1 for success, so clean up + * its result. + */ + if (cli_simple_run_command(cmd, flag) == -1) + return 1; + + return 0; +#else + return parse_string_outer(cmd, + FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP); +#endif +} + +int run_command_list(const char *cmd, int len, int flag) +{ + int need_buff = 1; + char *buff = (char *)cmd; /* cast away const */ + int rcode = 0; + + if (len == -1) { + len = strlen(cmd); +#ifdef CONFIG_SYS_HUSH_PARSER + /* hush will never change our string */ + need_buff = 0; +#else + /* the built-in parser will change our string if it sees \n */ + need_buff = strchr(cmd, '\n') != NULL; +#endif + } + if (need_buff) { + buff = malloc(len + 1); + if (!buff) + return 1; + memcpy(buff, cmd, len); + buff[len] = '\0'; + } +#ifdef CONFIG_SYS_HUSH_PARSER + rcode = parse_string_outer(buff, FLAG_PARSE_SEMICOLON); +#else + /* + * This function will overwrite any \n it sees with a \0, which + * is why it can't work with a const char *. Here we are making + * using of internal knowledge of this function, to avoid always + * doing a malloc() which is actually required only in a case that + * is pretty rare. + */ + rcode = cli_simple_run_command_list(buff, flag); + if (need_buff) + free(buff); +#endif + + return rcode; +} + +/****************************************************************************/ + +#if defined(CONFIG_CMD_RUN) +int do_run(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i; + + if (argc < 2) + return CMD_RET_USAGE; + + for (i = 1; i < argc; ++i) { + char *arg; + + arg = getenv(argv[i]); + if (arg == NULL) { + printf("## Error: \"%s\" not defined\n", argv[i]); + return 1; + } + + if (run_command(arg, flag) != 0) + return 1; + } + return 0; +} +#endif + +#ifdef CONFIG_OF_CONTROL +bool cli_process_fdt(const char **cmdp) +{ + /* Allow the fdt to override the boot command */ + char *env = fdtdec_get_config_string(gd->fdt_blob, "bootcmd"); + if (env) + *cmdp = env; + /* + * If the bootsecure option was chosen, use secure_boot_cmd(). + * Always use 'env' in this case, since bootsecure requres that the + * bootcmd was specified in the FDT too. + */ + return fdtdec_get_config_int(gd->fdt_blob, "bootsecure", 0) != 0; +} + +/* + * Runs the given boot command securely. Specifically: + * - Doesn't run the command with the shell (run_command or parse_string_outer), + * since that's a lot of code surface that an attacker might exploit. + * Because of this, we don't do any argument parsing--the secure boot command + * has to be a full-fledged u-boot command. + * - Doesn't check for keypresses before booting, since that could be a + * security hole; also disables Ctrl-C. + * - Doesn't allow the command to return. + * + * Upon any failures, this function will drop into an infinite loop after + * printing the error message to console. + */ +void cli_secure_boot_cmd(const char *cmd) +{ + cmd_tbl_t *cmdtp; + int rc; + + if (!cmd) { + printf("## Error: Secure boot command not specified\n"); + goto err; + } + + /* Disable Ctrl-C just in case some command is used that checks it. */ + disable_ctrlc(1); + + /* Find the command directly. */ + cmdtp = find_cmd(cmd); + if (!cmdtp) { + printf("## Error: \"%s\" not defined\n", cmd); + goto err; + } + + /* Run the command, forcing no flags and faking argc and argv. */ + rc = (cmdtp->cmd)(cmdtp, 0, 1, (char **)&cmd); + + /* Shouldn't ever return from boot command. */ + printf("## Error: \"%s\" returned (code %d)\n", cmd, rc); + +err: + /* + * Not a whole lot to do here. Rebooting won't help much, since we'll + * just end up right back here. Just loop. + */ + hang(); +} +#endif /* CONFIG_OF_CONTROL */ + +void cli_loop(void) +{ +#ifdef CONFIG_SYS_HUSH_PARSER + parse_file_outer(); + /* This point is never reached */ + for (;;); +#else + cli_simple_loop(); +#endif /*CONFIG_SYS_HUSH_PARSER*/ +} + +void cli_init(void) +{ +#ifdef CONFIG_SYS_HUSH_PARSER + u_boot_hush_start(); +#endif + +#if defined(CONFIG_HUSH_INIT_VAR) + hush_init_var(); +#endif +} diff --git a/common/hush.c b/common/cli_hush.c index 5b4322475..0f069b010 100644 --- a/common/hush.c +++ b/common/cli_hush.c @@ -79,7 +79,9 @@ #include <malloc.h> /* malloc, free, realloc*/ #include <linux/ctype.h> /* isalpha, isdigit */ #include <common.h> /* readline */ -#include <hush.h> +#include <bootretry.h> +#include <cli.h> +#include <cli_hush.h> #include <command.h> /* find_cmd */ #ifndef CONFIG_SYS_PROMPT_HUSH_PS2 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " @@ -222,7 +224,7 @@ struct child_prog { #endif char **argv; /* program name and arguments */ /* was quoted when parsed; copy of struct o_string.nonnull field */ - int *argv_nonnull; + int *argv_nonnull; #ifdef __U_BOOT__ int argc; /* number of program arguments */ #endif @@ -998,17 +1000,12 @@ static void get_user_input(struct in_str *i) int n; static char the_command[CONFIG_SYS_CBSIZE + 1]; -#ifdef CONFIG_BOOT_RETRY_TIME -# ifndef CONFIG_RESET_TO_RETRY -# error "This currently only works with CONFIG_RESET_TO_RETRY enabled" -# endif - reset_cmd_timeout(); -#endif + bootretry_reset_cmd_timeout(); i->__promptme = 1; if (i->promptmode == 1) { - n = readline(CONFIG_SYS_PROMPT); + n = cli_readline(CONFIG_SYS_PROMPT); } else { - n = readline(CONFIG_SYS_PROMPT_HUSH_PS2); + n = cli_readline(CONFIG_SYS_PROMPT_HUSH_PS2); } #ifdef CONFIG_BOOT_RETRY_TIME if (n == -2) { diff --git a/common/cli_readline.c b/common/cli_readline.c new file mode 100644 index 000000000..9a9fb35b7 --- /dev/null +++ b/common/cli_readline.c @@ -0,0 +1,621 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Add to readline cmdline-editing by + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <bootretry.h> +#include <cli.h> +#include <watchdog.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const char erase_seq[] = "\b \b"; /* erase sequence */ +static const char tab_seq[] = " "; /* used to expand TABs */ + +char console_buffer[CONFIG_SYS_CBSIZE + 1]; /* console I/O buffer */ + +static char *delete_char (char *buffer, char *p, int *colp, int *np, int plen) +{ + char *s; + + if (*np == 0) + return p; + + if (*(--p) == '\t') { /* will retype the whole line */ + while (*colp > plen) { + puts(erase_seq); + (*colp)--; + } + for (s = buffer; s < p; ++s) { + if (*s == '\t') { + puts(tab_seq + ((*colp) & 07)); + *colp += 8 - ((*colp) & 07); + } else { + ++(*colp); + putc(*s); + } + } + } else { + puts(erase_seq); + (*colp)--; + } + (*np)--; + + return p; +} + +#ifdef CONFIG_CMDLINE_EDITING + +/* + * cmdline-editing related codes from vivi. + * Author: Janghoon Lyu <nandy@mizi.com> + */ + +#define putnstr(str, n) printf("%.*s", (int)n, str) + +#define CTL_CH(c) ((c) - 'a' + 1) +#define CTL_BACKSPACE ('\b') +#define DEL ((char)255) +#define DEL7 ((char)127) +#define CREAD_HIST_CHAR ('!') + +#define getcmd_putch(ch) putc(ch) +#define getcmd_getch() getc() +#define getcmd_cbeep() getcmd_putch('\a') + +#define HIST_MAX 20 +#define HIST_SIZE CONFIG_SYS_CBSIZE + +static int hist_max; +static int hist_add_idx; +static int hist_cur = -1; +static unsigned hist_num; + +static char *hist_list[HIST_MAX]; +static char hist_lines[HIST_MAX][HIST_SIZE + 1]; /* Save room for NULL */ + +#define add_idx_minus_one() ((hist_add_idx == 0) ? hist_max : hist_add_idx-1) + +static void hist_init(void) +{ + int i; + + hist_max = 0; + hist_add_idx = 0; + hist_cur = -1; + hist_num = 0; + + for (i = 0; i < HIST_MAX; i++) { + hist_list[i] = hist_lines[i]; + hist_list[i][0] = '\0'; + } +} + +static void cread_add_to_hist(char *line) +{ + strcpy(hist_list[hist_add_idx], line); + + if (++hist_add_idx >= HIST_MAX) + hist_add_idx = 0; + + if (hist_add_idx > hist_max) + hist_max = hist_add_idx; + + hist_num++; +} + +static char *hist_prev(void) +{ + char *ret; + int old_cur; + + if (hist_cur < 0) + return NULL; + + old_cur = hist_cur; + if (--hist_cur < 0) + hist_cur = hist_max; + + if (hist_cur == hist_add_idx) { + hist_cur = old_cur; + ret = NULL; + } else { + ret = hist_list[hist_cur]; + } + + return ret; +} + +static char *hist_next(void) +{ + char *ret; + + if (hist_cur < 0) + return NULL; + + if (hist_cur == hist_add_idx) + return NULL; + + if (++hist_cur > hist_max) + hist_cur = 0; + + if (hist_cur == hist_add_idx) + ret = ""; + else + ret = hist_list[hist_cur]; + + return ret; +} + +#ifndef CONFIG_CMDLINE_EDITING +static void cread_print_hist_list(void) +{ + int i; + unsigned long n; + + n = hist_num - hist_max; + + i = hist_add_idx + 1; + while (1) { + if (i > hist_max) + i = 0; + if (i == hist_add_idx) + break; + printf("%s\n", hist_list[i]); + n++; + i++; + } +} +#endif /* CONFIG_CMDLINE_EDITING */ + +#define BEGINNING_OF_LINE() { \ + while (num) { \ + getcmd_putch(CTL_BACKSPACE); \ + num--; \ + } \ +} + +#define ERASE_TO_EOL() { \ + if (num < eol_num) { \ + printf("%*s", (int)(eol_num - num), ""); \ + do { \ + getcmd_putch(CTL_BACKSPACE); \ + } while (--eol_num > num); \ + } \ +} + +#define REFRESH_TO_EOL() { \ + if (num < eol_num) { \ + wlen = eol_num - num; \ + putnstr(buf + num, wlen); \ + num = eol_num; \ + } \ +} + +static void cread_add_char(char ichar, int insert, unsigned long *num, + unsigned long *eol_num, char *buf, unsigned long len) +{ + unsigned long wlen; + + /* room ??? */ + if (insert || *num == *eol_num) { + if (*eol_num > len - 1) { + getcmd_cbeep(); + return; + } + (*eol_num)++; + } + + if (insert) { + wlen = *eol_num - *num; + if (wlen > 1) + memmove(&buf[*num+1], &buf[*num], wlen-1); + + buf[*num] = ichar; + putnstr(buf + *num, wlen); + (*num)++; + while (--wlen) + getcmd_putch(CTL_BACKSPACE); + } else { + /* echo the character */ + wlen = 1; + buf[*num] = ichar; + putnstr(buf + *num, wlen); + (*num)++; + } +} + +static void cread_add_str(char *str, int strsize, int insert, + unsigned long *num, unsigned long *eol_num, + char *buf, unsigned long len) +{ + while (strsize--) { + cread_add_char(*str, insert, num, eol_num, buf, len); + str++; + } +} + +static int cread_line(const char *const prompt, char *buf, unsigned int *len, + int timeout) +{ + unsigned long num = 0; + unsigned long eol_num = 0; + unsigned long wlen; + char ichar; + int insert = 1; + int esc_len = 0; + char esc_save[8]; + int init_len = strlen(buf); + int first = 1; + + if (init_len) + cread_add_str(buf, init_len, 1, &num, &eol_num, buf, *len); + + while (1) { + if (bootretry_tstc_timeout()) + return -2; /* timed out */ + if (first && timeout) { + uint64_t etime = endtick(timeout); + + while (!tstc()) { /* while no incoming data */ + if (get_ticks() >= etime) + return -2; /* timed out */ + WATCHDOG_RESET(); + } + first = 0; + } + + ichar = getcmd_getch(); + + if ((ichar == '\n') || (ichar == '\r')) { + putc('\n'); + break; + } + + /* + * handle standard linux xterm esc sequences for arrow key, etc. + */ + if (esc_len != 0) { + if (esc_len == 1) { + if (ichar == '[') { + esc_save[esc_len] = ichar; + esc_len = 2; + } else { + cread_add_str(esc_save, esc_len, + insert, &num, &eol_num, + buf, *len); + esc_len = 0; + } + continue; + } + + switch (ichar) { + case 'D': /* <- key */ + ichar = CTL_CH('b'); + esc_len = 0; + break; + case 'C': /* -> key */ + ichar = CTL_CH('f'); + esc_len = 0; + break; /* pass off to ^F handler */ + case 'H': /* Home key */ + ichar = CTL_CH('a'); + esc_len = 0; + break; /* pass off to ^A handler */ + case 'A': /* up arrow */ + ichar = CTL_CH('p'); + esc_len = 0; + break; /* pass off to ^P handler */ + case 'B': /* down arrow */ + ichar = CTL_CH('n'); + esc_len = 0; + break; /* pass off to ^N handler */ + default: + esc_save[esc_len++] = ichar; + cread_add_str(esc_save, esc_len, insert, + &num, &eol_num, buf, *len); + esc_len = 0; + continue; + } + } + + switch (ichar) { + case 0x1b: + if (esc_len == 0) { + esc_save[esc_len] = ichar; + esc_len = 1; + } else { + puts("impossible condition #876\n"); + esc_len = 0; + } + break; + + case CTL_CH('a'): + BEGINNING_OF_LINE(); + break; + case CTL_CH('c'): /* ^C - break */ + *buf = '\0'; /* discard input */ + return -1; + case CTL_CH('f'): + if (num < eol_num) { + getcmd_putch(buf[num]); + num++; + } + break; + case CTL_CH('b'): + if (num) { + getcmd_putch(CTL_BACKSPACE); + num--; + } + break; + case CTL_CH('d'): + if (num < eol_num) { + wlen = eol_num - num - 1; + if (wlen) { + memmove(&buf[num], &buf[num+1], wlen); + putnstr(buf + num, wlen); + } + + getcmd_putch(' '); + do { + getcmd_putch(CTL_BACKSPACE); + } while (wlen--); + eol_num--; + } + break; + case CTL_CH('k'): + ERASE_TO_EOL(); + break; + case CTL_CH('e'): + REFRESH_TO_EOL(); + break; + case CTL_CH('o'): + insert = !insert; + break; + case CTL_CH('x'): + case CTL_CH('u'): + BEGINNING_OF_LINE(); + ERASE_TO_EOL(); + break; + case DEL: + case DEL7: + case 8: + if (num) { + wlen = eol_num - num; + num--; + memmove(&buf[num], &buf[num+1], wlen); + getcmd_putch(CTL_BACKSPACE); + putnstr(buf + num, wlen); + getcmd_putch(' '); + do { + getcmd_putch(CTL_BACKSPACE); + } while (wlen--); + eol_num--; + } + break; + case CTL_CH('p'): + case CTL_CH('n'): + { + char *hline; + + esc_len = 0; + + if (ichar == CTL_CH('p')) + hline = hist_prev(); + else + hline = hist_next(); + + if (!hline) { + getcmd_cbeep(); + continue; + } + + /* nuke the current line */ + /* first, go home */ + BEGINNING_OF_LINE(); + + /* erase to end of line */ + ERASE_TO_EOL(); + + /* copy new line into place and display */ + strcpy(buf, hline); + eol_num = strlen(buf); + REFRESH_TO_EOL(); + continue; + } +#ifdef CONFIG_AUTO_COMPLETE + case '\t': { + int num2, col; + + /* do not autocomplete when in the middle */ + if (num < eol_num) { + getcmd_cbeep(); + break; + } + + buf[num] = '\0'; + col = strlen(prompt) + eol_num; + num2 = num; + if (cmd_auto_complete(prompt, buf, &num2, &col)) { + col = num2 - num; + num += col; + eol_num += col; + } + break; + } +#endif + default: + cread_add_char(ichar, insert, &num, &eol_num, buf, + *len); + break; + } + } + *len = eol_num; + buf[eol_num] = '\0'; /* lose the newline */ + + if (buf[0] && buf[0] != CREAD_HIST_CHAR) + cread_add_to_hist(buf); + hist_cur = hist_add_idx; + + return 0; +} + +#endif /* CONFIG_CMDLINE_EDITING */ + +/****************************************************************************/ + +int cli_readline(const char *const prompt) +{ + /* + * If console_buffer isn't 0-length the user will be prompted to modify + * it instead of entering it from scratch as desired. + */ + console_buffer[0] = '\0'; + + return cli_readline_into_buffer(prompt, console_buffer, 0); +} + + +int cli_readline_into_buffer(const char *const prompt, char *buffer, + int timeout) +{ + char *p = buffer; +#ifdef CONFIG_CMDLINE_EDITING + unsigned int len = CONFIG_SYS_CBSIZE; + int rc; + static int initted; + + /* + * History uses a global array which is not + * writable until after relocation to RAM. + * Revert to non-history version if still + * running from flash. + */ + if (gd->flags & GD_FLG_RELOC) { + if (!initted) { + hist_init(); + initted = 1; + } + + if (prompt) + puts(prompt); + + rc = cread_line(prompt, p, &len, timeout); + return rc < 0 ? rc : len; + + } else { +#endif /* CONFIG_CMDLINE_EDITING */ + char *p_buf = p; + int n = 0; /* buffer index */ + int plen = 0; /* prompt length */ + int col; /* output column cnt */ + char c; + + /* print prompt */ + if (prompt) { + plen = strlen(prompt); + puts(prompt); + } + col = plen; + + for (;;) { + if (bootretry_tstc_timeout()) + return -2; /* timed out */ + WATCHDOG_RESET(); /* Trigger watchdog, if needed */ + +#ifdef CONFIG_SHOW_ACTIVITY + while (!tstc()) { + show_activity(0); + WATCHDOG_RESET(); + } +#endif + c = getc(); + + /* + * Special character handling + */ + switch (c) { + case '\r': /* Enter */ + case '\n': + *p = '\0'; + puts("\r\n"); + return p - p_buf; + + case '\0': /* nul */ + continue; + + case 0x03: /* ^C - break */ + p_buf[0] = '\0'; /* discard input */ + return -1; + + case 0x15: /* ^U - erase line */ + while (col > plen) { + puts(erase_seq); + --col; + } + p = p_buf; + n = 0; + continue; + + case 0x17: /* ^W - erase word */ + p = delete_char(p_buf, p, &col, &n, plen); + while ((n > 0) && (*p != ' ')) + p = delete_char(p_buf, p, &col, &n, plen); + continue; + + case 0x08: /* ^H - backspace */ + case 0x7F: /* DEL - backspace */ + p = delete_char(p_buf, p, &col, &n, plen); + continue; + + default: + /* + * Must be a normal character then + */ + if (n < CONFIG_SYS_CBSIZE-2) { + if (c == '\t') { /* expand TABs */ +#ifdef CONFIG_AUTO_COMPLETE + /* + * if auto completion triggered just + * continue + */ + *p = '\0'; + if (cmd_auto_complete(prompt, + console_buffer, + &n, &col)) { + p = p_buf + n; /* reset */ + continue; + } +#endif + puts(tab_seq + (col & 07)); + col += 8 - (col & 07); + } else { + char buf[2]; + + /* + * Echo input using puts() to force an + * LCD flush if we are using an LCD + */ + ++col; + buf[0] = c; + buf[1] = '\0'; + puts(buf); + } + *p++ = c; + ++n; + } else { /* Buffer full */ + putc('\a'); + } + } + } +#ifdef CONFIG_CMDLINE_EDITING + } +#endif +} diff --git a/common/cli_simple.c b/common/cli_simple.c new file mode 100644 index 000000000..413c2eb89 --- /dev/null +++ b/common/cli_simple.c @@ -0,0 +1,337 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Add to readline cmdline-editing by + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <bootretry.h> +#include <cli.h> +#include <linux/ctype.h> + +#define DEBUG_PARSER 0 /* set to 1 to debug */ + +#define debug_parser(fmt, args...) \ + debug_cond(DEBUG_PARSER, fmt, ##args) + + +int cli_simple_parse_line(char *line, char *argv[]) +{ + int nargs = 0; + + debug_parser("%s: \"%s\"\n", __func__, line); + while (nargs < CONFIG_SYS_MAXARGS) { + /* skip any white space */ + while (isblank(*line)) + ++line; + + if (*line == '\0') { /* end of line, no more args */ + argv[nargs] = NULL; + debug_parser("%s: nargs=%d\n", __func__, nargs); + return nargs; + } + + argv[nargs++] = line; /* begin of argument string */ + + /* find end of string */ + while (*line && !isblank(*line)) + ++line; + + if (*line == '\0') { /* end of line, no more args */ + argv[nargs] = NULL; + debug_parser("parse_line: nargs=%d\n", nargs); + return nargs; + } + + *line++ = '\0'; /* terminate current arg */ + } + + printf("** Too many args (max. %d) **\n", CONFIG_SYS_MAXARGS); + + debug_parser("%s: nargs=%d\n", __func__, nargs); + return nargs; +} + +static void process_macros(const char *input, char *output) +{ + char c, prev; + const char *varname_start = NULL; + int inputcnt = strlen(input); + int outputcnt = CONFIG_SYS_CBSIZE; + int state = 0; /* 0 = waiting for '$' */ + + /* 1 = waiting for '(' or '{' */ + /* 2 = waiting for ')' or '}' */ + /* 3 = waiting for ''' */ + char *output_start = output; + + debug_parser("[PROCESS_MACROS] INPUT len %zd: \"%s\"\n", strlen(input), + input); + + prev = '\0'; /* previous character */ + + while (inputcnt && outputcnt) { + c = *input++; + inputcnt--; + + if (state != 3) { + /* remove one level of escape characters */ + if ((c == '\\') && (prev != '\\')) { + if (inputcnt-- == 0) + break; + prev = c; + c = *input++; + } + } + + switch (state) { + case 0: /* Waiting for (unescaped) $ */ + if ((c == '\'') && (prev != '\\')) { + state = 3; + break; + } + if ((c == '$') && (prev != '\\')) { + state++; + } else { + *(output++) = c; + outputcnt--; + } + break; + case 1: /* Waiting for ( */ + if (c == '(' || c == '{') { + state++; + varname_start = input; + } else { + state = 0; + *(output++) = '$'; + outputcnt--; + + if (outputcnt) { + *(output++) = c; + outputcnt--; + } + } + break; + case 2: /* Waiting for ) */ + if (c == ')' || c == '}') { + int i; + char envname[CONFIG_SYS_CBSIZE], *envval; + /* Varname # of chars */ + int envcnt = input - varname_start - 1; + + /* Get the varname */ + for (i = 0; i < envcnt; i++) + envname[i] = varname_start[i]; + envname[i] = 0; + + /* Get its value */ + envval = getenv(envname); + + /* Copy into the line if it exists */ + if (envval != NULL) + while ((*envval) && outputcnt) { + *(output++) = *(envval++); + outputcnt--; + } + /* Look for another '$' */ + state = 0; + } + break; + case 3: /* Waiting for ' */ + if ((c == '\'') && (prev != '\\')) { + state = 0; + } else { + *(output++) = c; + outputcnt--; + } + break; + } + prev = c; + } + + if (outputcnt) + *output = 0; + else + *(output - 1) = 0; + + debug_parser("[PROCESS_MACROS] OUTPUT len %zd: \"%s\"\n", + strlen(output_start), output_start); +} + + /* + * WARNING: + * + * We must create a temporary copy of the command since the command we get + * may be the result from getenv(), which returns a pointer directly to + * the environment data, which may change magicly when the command we run + * creates or modifies environment variables (like "bootp" does). + */ +int cli_simple_run_command(const char *cmd, int flag) +{ + char cmdbuf[CONFIG_SYS_CBSIZE]; /* working copy of cmd */ + char *token; /* start of token in cmdbuf */ + char *sep; /* end of token (separator) in cmdbuf */ + char finaltoken[CONFIG_SYS_CBSIZE]; + char *str = cmdbuf; + char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */ + int argc, inquotes; + int repeatable = 1; + int rc = 0; + + debug_parser("[RUN_COMMAND] cmd[%p]=\"", cmd); + if (DEBUG_PARSER) { + /* use puts - string may be loooong */ + puts(cmd ? cmd : "NULL"); + puts("\"\n"); + } + clear_ctrlc(); /* forget any previous Control C */ + + if (!cmd || !*cmd) + return -1; /* empty command */ + + if (strlen(cmd) >= CONFIG_SYS_CBSIZE) { + puts("## Command too long!\n"); + return -1; + } + + strcpy(cmdbuf, cmd); + + /* Process separators and check for invalid + * repeatable commands + */ + + debug_parser("[PROCESS_SEPARATORS] %s\n", cmd); + while (*str) { + /* + * Find separator, or string end + * Allow simple escape of ';' by writing "\;" + */ + for (inquotes = 0, sep = str; *sep; sep++) { + if ((*sep == '\'') && + (*(sep - 1) != '\\')) + inquotes = !inquotes; + + if (!inquotes && + (*sep == ';') && /* separator */ + (sep != str) && /* past string start */ + (*(sep - 1) != '\\')) /* and NOT escaped */ + break; + } + + /* + * Limit the token to data between separators + */ + token = str; + if (*sep) { + str = sep + 1; /* start of command for next pass */ + *sep = '\0'; + } else { + str = sep; /* no more commands for next pass */ + } + debug_parser("token: \"%s\"\n", token); + + /* find macros in this token and replace them */ + process_macros(token, finaltoken); + + /* Extract arguments */ + argc = cli_simple_parse_line(finaltoken, argv); + if (argc == 0) { + rc = -1; /* no command at all */ + continue; + } + + if (cmd_process(flag, argc, argv, &repeatable, NULL)) + rc = -1; + + /* Did the user stop this? */ + if (had_ctrlc()) + return -1; /* if stopped then not repeatable */ + } + + return rc ? rc : repeatable; +} + +void cli_simple_loop(void) +{ + static char lastcommand[CONFIG_SYS_CBSIZE] = { 0, }; + + int len; + int flag; + int rc = 1; + + for (;;) { + if (rc >= 0) { + /* Saw enough of a valid command to + * restart the timeout. + */ + bootretry_reset_cmd_timeout(); + } + len = cli_readline(CONFIG_SYS_PROMPT); + + flag = 0; /* assume no special flags for now */ + if (len > 0) + strcpy(lastcommand, console_buffer); + else if (len == 0) + flag |= CMD_FLAG_REPEAT; +#ifdef CONFIG_BOOT_RETRY_TIME + else if (len == -2) { + /* -2 means timed out, retry autoboot + */ + puts("\nTimed out waiting for command\n"); +# ifdef CONFIG_RESET_TO_RETRY + /* Reinit board to run initialization code again */ + do_reset(NULL, 0, 0, NULL); +# else + return; /* retry autoboot */ +# endif + } +#endif + + if (len == -1) + puts("<INTERRUPT>\n"); + else + rc = run_command(lastcommand, flag); + + if (rc <= 0) { + /* invalid command or not repeatable, forget it */ + lastcommand[0] = 0; + } + } +} + +int cli_simple_run_command_list(char *cmd, int flag) +{ + char *line, *next; + int rcode = 0; + + /* + * Break into individual lines, and execute each line; terminate on + * error. + */ + next = cmd; + line = cmd; + while (*next) { + if (*next == '\n') { + *next = '\0'; + /* run only non-empty commands */ + if (*line) { + debug("** exec: \"%s\"\n", line); + if (cli_simple_run_command(line, 0) < 0) { + rcode = 1; + break; + } + } + line = next + 1; + } + ++next; + } + if (rcode == 0 && *line) + rcode = (cli_simple_run_command(line, 0) >= 0); + + return rcode; +} diff --git a/common/cmd_bedbug.c b/common/cmd_bedbug.c index 77b6e3e88..bdcf712d1 100644 --- a/common/cmd_bedbug.c +++ b/common/cmd_bedbug.c @@ -3,6 +3,7 @@ */ #include <common.h> +#include <cli.h> #include <command.h> #include <linux/ctype.h> #include <net.h> @@ -19,7 +20,7 @@ extern int run_command __P ((const char *, int)); ulong dis_last_addr = 0; /* Last address disassembled */ ulong dis_last_len = 20; /* Default disassembler length */ CPU_DEBUG_CTX bug_ctx; /* Bedbug context structure */ - + /* ====================================================================== * U-Boot's puts function does not append a newline, so the bedbug stuff @@ -33,7 +34,7 @@ int bedbug_puts (const char *str) printf ("%s\r\n", str); return 0; } /* bedbug_puts */ - + /* ====================================================================== @@ -65,7 +66,7 @@ void bedbug_init (void) return; } /* bedbug_init */ - + /* ====================================================================== @@ -106,7 +107,7 @@ int do_bedbug_dis (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD (ds, 3, 1, do_bedbug_dis, "disassemble memory", "ds <address> [# instructions]"); - + /* ====================================================================== * Entry point from the interpreter to the assembler. Assembles * instructions in consecutive memory locations until a '.' (period) is @@ -134,7 +135,7 @@ int do_bedbug_asm (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) F_RADHEX); sprintf (prompt, "%08lx: ", mem_addr); - readline (prompt); + cli_readline(prompt); if (console_buffer[0] && strcmp (console_buffer, ".")) { if ((instr = @@ -156,7 +157,7 @@ int do_bedbug_asm (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD (as, 2, 0, do_bedbug_asm, "assemble memory", "as <address>"); - + /* ====================================================================== * Used to set a break point from the interpreter. Simply calls into the * CPU-specific break point set routine. @@ -177,7 +178,7 @@ U_BOOT_CMD (break, 3, 0, do_bedbug_break, "break <address> - Break at an address\n" "break off <bp#> - Disable breakpoint.\n" "break show - List breakpoints."); - + /* ====================================================================== * Called from the debug interrupt routine. Simply calls the CPU-specific * breakpoint handling routine. @@ -192,7 +193,7 @@ void do_bedbug_breakpoint (struct pt_regs *regs) return; } /* do_bedbug_breakpoint */ - + /* ====================================================================== @@ -225,7 +226,7 @@ void bedbug_main_loop (unsigned long addr, struct pt_regs *regs) /* A miniature main loop */ while (bug_ctx.stopped) { - len = readline (prompt_str); + len = cli_readline(prompt_str); flag = 0; /* assume no special flags for now */ @@ -250,7 +251,7 @@ void bedbug_main_loop (unsigned long addr, struct pt_regs *regs) return; } /* bedbug_main_loop */ - + /* ====================================================================== @@ -274,7 +275,7 @@ int do_bedbug_continue (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv U_BOOT_CMD (continue, 1, 0, do_bedbug_continue, "continue from a breakpoint", ""); - + /* ====================================================================== * Interpreter command to continue to the next instruction, stepping into * subroutines. Works by calling the find_next_addr() routine to compute @@ -305,7 +306,7 @@ int do_bedbug_step (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD (step, 1, 1, do_bedbug_step, "single step execution.", ""); - + /* ====================================================================== * Interpreter command to continue to the next instruction, stepping over * subroutines. Works by calling the find_next_addr() routine to compute @@ -336,7 +337,7 @@ int do_bedbug_next (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD (next, 1, 1, do_bedbug_next, "single step execution, stepping over subroutines.", ""); - + /* ====================================================================== * Interpreter command to print the current stack. This assumes an EABI * architecture, so it starts with GPR R1 and works back up the stack. @@ -381,7 +382,7 @@ int do_bedbug_stack (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD (where, 1, 1, do_bedbug_stack, "Print the running stack.", ""); - + /* ====================================================================== * Interpreter command to dump the registers. Calls the CPU-specific * show registers routine. diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index e683af369..449bb363f 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -32,10 +32,6 @@ #include <usb.h> #endif -#ifdef CONFIG_SYS_HUSH_PARSER -#include <hush.h> -#endif - #if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> #include <fdt_support.h> @@ -222,6 +218,7 @@ static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { const void *os_hdr; + bool ep_found = false; /* get kernel image header, start address and length */ os_hdr = boot_get_kernel(cmdtp, flag, argc, argv, @@ -274,6 +271,18 @@ static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int argc, } break; #endif +#ifdef CONFIG_ANDROID_BOOT_IMAGE + case IMAGE_FORMAT_ANDROID: + images.os.type = IH_TYPE_KERNEL; + images.os.comp = IH_COMP_NONE; + images.os.os = IH_OS_LINUX; + images.ep = images.os.load; + ep_found = true; + + images.os.end = android_image_get_end(os_hdr); + images.os.load = android_image_get_kload(os_hdr); + break; +#endif default: puts("ERROR: unknown image format type!\n"); return 1; @@ -293,7 +302,7 @@ static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int argc, return 1; } #endif - } else { + } else if (!ep_found) { puts("Could not find kernel entry point!\n"); return 1; } @@ -1002,6 +1011,14 @@ static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc, images->fit_noffset_os = os_noffset; break; #endif +#ifdef CONFIG_ANDROID_BOOT_IMAGE + case IMAGE_FORMAT_ANDROID: + printf("## Booting Android Image at 0x%08lx ...\n", img_addr); + if (android_image_get_kernel((void *)img_addr, images->verify, + os_data, os_len)) + return NULL; + break; +#endif default: printf("Wrong Image Format for %s command\n", cmdtp->name); bootstage_error(BOOTSTAGE_ID_FIT_KERNEL_INFO); diff --git a/common/cmd_bootmenu.c b/common/cmd_bootmenu.c index 163d5b2e2..5879065c2 100644 --- a/common/cmd_bootmenu.c +++ b/common/cmd_bootmenu.c @@ -8,7 +8,6 @@ #include <command.h> #include <ansi.h> #include <menu.h> -#include <hush.h> #include <watchdog.h> #include <malloc.h> #include <linux/string.h> diff --git a/common/cmd_dcr.c b/common/cmd_dcr.c index 896f79f41..4fddd804a 100644 --- a/common/cmd_dcr.c +++ b/common/cmd_dcr.c @@ -10,6 +10,7 @@ */ #include <common.h> +#include <cli.h> #include <config.h> #include <command.h> @@ -62,7 +63,7 @@ int do_setdcr (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) do { value = get_dcr (dcrn); printf ("%04x: %08lx", dcrn, value); - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (nbytes == 0) { /* * <CR> pressed as only input, don't modify current diff --git a/common/cmd_demo.c b/common/cmd_demo.c index a3bba7fdf..652c61c70 100644 --- a/common/cmd_demo.c +++ b/common/cmd_demo.c @@ -11,7 +11,7 @@ #include <dm-demo.h> #include <asm/io.h> -struct device *demo_dev; +struct udevice *demo_dev; static int do_demo_hello(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -41,7 +41,7 @@ static int do_demo_status(cmd_tbl_t *cmdtp, int flag, int argc, int do_demo_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - struct device *dev; + struct udevice *dev; int i, ret; puts("Demo uclass entries:\n"); diff --git a/common/cmd_fastboot.c b/common/cmd_fastboot.c new file mode 100644 index 000000000..83fa7bdde --- /dev/null +++ b/common/cmd_fastboot.c @@ -0,0 +1,36 @@ +/* + * Copyright 2008 - 2009 Windriver, <www.windriver.com> + * Author: Tom Rix <Tom.Rix@windriver.com> + * + * (C) Copyright 2014 Linaro, Ltd. + * Rob Herring <robh@kernel.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <command.h> +#include <g_dnl.h> + +static int do_fastboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int ret; + + ret = g_dnl_register("usb_dnl_fastboot"); + if (ret) + return ret; + + while (1) { + if (ctrlc()) + break; + usb_gadget_handle_interrupts(); + } + + g_dnl_unregister(); + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD( + fastboot, 1, 1, do_fastboot, + "fastboot - enter USB Fastboot protocol", + "" +); diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index 010cd24e6..bda5c8f79 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -11,6 +11,7 @@ #include <common.h> #include <command.h> #include <fpga.h> +#include <fs.h> #include <malloc.h> /* Local functions */ @@ -23,6 +24,9 @@ static int fpga_get_op(char *opstr); #define FPGA_LOADB 2 #define FPGA_DUMP 3 #define FPGA_LOADMK 4 +#define FPGA_LOADP 5 +#define FPGA_LOADBP 6 +#define FPGA_LOADFS 7 /* ------------------------------------------------------------------------- */ /* command form: @@ -45,6 +49,10 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) const char *fit_uname = NULL; ulong fit_addr; #endif +#if defined(CONFIG_CMD_FPGA_LOADFS) + fpga_fs_info fpga_fsinfo; + fpga_fsinfo.fstype = FS_TYPE_ANY; +#endif if (devstr) dev = (int) simple_strtoul(devstr, NULL, 16); @@ -52,6 +60,14 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) fpga_data = (void *)simple_strtoul(datastr, NULL, 16); switch (argc) { +#if defined(CONFIG_CMD_FPGA_LOADFS) + case 9: + fpga_fsinfo.blocksize = (unsigned int) + simple_strtoul(argv[5], NULL, 16); + fpga_fsinfo.interface = argv[6]; + fpga_fsinfo.dev_part = argv[7]; + fpga_fsinfo.filename = argv[8]; +#endif case 5: /* fpga <op> <dev> <data> <datasize> */ data_size = simple_strtoul(argv[4], NULL, 16); @@ -120,16 +136,27 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) case FPGA_NONE: case FPGA_INFO: break; +#if defined(CONFIG_CMD_FPGA_LOADFS) + case FPGA_LOADFS: + /* Blocksize can be zero */ + if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part || + !fpga_fsinfo.filename) + wrong_parms = 1; +#endif case FPGA_LOAD: + case FPGA_LOADP: case FPGA_LOADB: + case FPGA_LOADBP: case FPGA_DUMP: if (!fpga_data || !data_size) wrong_parms = 1; break; +#if defined(CONFIG_CMD_FPGA_LOADMK) case FPGA_LOADMK: if (!fpga_data) wrong_parms = 1; break; +#endif } if (wrong_parms) { @@ -146,13 +173,32 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) break; case FPGA_LOAD: - rc = fpga_load(dev, fpga_data, data_size); + rc = fpga_load(dev, fpga_data, data_size, BIT_FULL); + break; + +#if defined(CONFIG_CMD_FPGA_LOADP) + case FPGA_LOADP: + rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL); break; +#endif case FPGA_LOADB: - rc = fpga_loadbitstream(dev, fpga_data, data_size); + rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL); + break; + +#if defined(CONFIG_CMD_FPGA_LOADBP) + case FPGA_LOADBP: + rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL); + break; +#endif + +#if defined(CONFIG_CMD_FPGA_LOADFS) + case FPGA_LOADFS: + rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo); break; +#endif +#if defined(CONFIG_CMD_FPGA_LOADMK) case FPGA_LOADMK: switch (genimg_get_format(fpga_data)) { case IMAGE_FORMAT_LEGACY: @@ -179,7 +225,8 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) data = (ulong)image_get_data(hdr); data_size = image_get_data_size(hdr); } - rc = fpga_load(dev, (void *)data, data_size); + rc = fpga_load(dev, (void *)data, data_size, + BIT_FULL); } break; #if defined(CONFIG_FIT) @@ -221,7 +268,8 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) return 1; } - rc = fpga_load(dev, fit_data, data_size); + rc = fpga_load(dev, fit_data, data_size, + BIT_FULL); } break; #endif @@ -231,6 +279,7 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) break; } break; +#endif case FPGA_DUMP: rc = fpga_dump(dev, fpga_data, data_size); @@ -257,8 +306,22 @@ static int fpga_get_op(char *opstr) op = FPGA_LOADB; else if (!strcmp("load", opstr)) op = FPGA_LOAD; +#if defined(CONFIG_CMD_FPGA_LOADP) + else if (!strcmp("loadp", opstr)) + op = FPGA_LOADP; +#endif +#if defined(CONFIG_CMD_FPGA_LOADBP) + else if (!strcmp("loadbp", opstr)) + op = FPGA_LOADBP; +#endif +#if defined(CONFIG_CMD_FPGA_LOADFS) + else if (!strcmp("loadfs", opstr)) + op = FPGA_LOADFS; +#endif +#if defined(CONFIG_CMD_FPGA_LOADMK) else if (!strcmp("loadmk", opstr)) op = FPGA_LOADMK; +#endif else if (!strcmp("dump", opstr)) op = FPGA_DUMP; @@ -268,19 +331,39 @@ static int fpga_get_op(char *opstr) return op; } +#if defined(CONFIG_CMD_FPGA_LOADFS) +U_BOOT_CMD(fpga, 9, 1, do_fpga, +#else U_BOOT_CMD(fpga, 6, 1, do_fpga, +#endif "loadable FPGA image support", "[operation type] [device number] [image address] [image size]\n" "fpga operations:\n" " dump\t[dev]\t\t\tLoad device to memory buffer\n" " info\t[dev]\t\t\tlist known device information\n" " load\t[dev] [address] [size]\tLoad device from memory buffer\n" +#if defined(CONFIG_CMD_FPGA_LOADP) + " loadp\t[dev] [address] [size]\t" + "Load device from memory buffer with partial bitstream\n" +#endif " loadb\t[dev] [address] [size]\t" "Load device from bitstream buffer (Xilinx only)\n" +#if defined(CONFIG_CMD_FPGA_LOADBP) + " loadbp\t[dev] [address] [size]\t" + "Load device from bitstream buffer with partial bitstream" + "(Xilinx only)\n" +#endif +#if defined(CONFIG_CMD_FPGA_LOADFS) + "Load device from filesystem (FAT by default) (Xilinx only)\n" + " loadfs [dev] [address] [image size] [blocksize] <interface>\n" + " [<dev[:part]>] <filename>\n" +#endif +#if defined(CONFIG_CMD_FPGA_LOADMK) " loadmk [dev] [address]\tLoad device generated with mkimage" #if defined(CONFIG_FIT) "\n" "\tFor loadmk operating on FIT format uImage address must include\n" "\tsubimage unit name in the form of addr:<subimg_uname>" #endif +#endif ); diff --git a/common/cmd_fuse.c b/common/cmd_fuse.c index 0df57dbc8..abab9789b 100644 --- a/common/cmd_fuse.c +++ b/common/cmd_fuse.c @@ -33,15 +33,8 @@ static int confirm_prog(void) "what you are doing!\n" "\nReally perform this fuse programming? <y/N>\n"); - if (getc() == 'y') { - int c; - - putc('y'); - c = getc(); - putc('\n'); - if (c == '\r') - return 1; - } + if (confirm_yesno()) + return 1; puts("Fuse programming aborted\n"); return 0; diff --git a/common/cmd_gpio.c b/common/cmd_gpio.c index aff044518..4634f914e 100644 --- a/common/cmd_gpio.c +++ b/common/cmd_gpio.c @@ -30,7 +30,7 @@ static const char * const gpio_function[] = { "unknown", }; -static void show_gpio(struct device *dev, const char *bank_name, int offset) +static void show_gpio(struct udevice *dev, const char *bank_name, int offset) { struct dm_gpio_ops *ops = gpio_get_ops(dev); char buf[80]; @@ -62,7 +62,7 @@ static void show_gpio(struct device *dev, const char *bank_name, int offset) static int do_gpio_status(const char *gpio_name) { - struct device *dev; + struct udevice *dev; int newline = 0; int ret; diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index ebce7d4c3..d714658d7 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -66,6 +66,8 @@ */ #include <common.h> +#include <bootretry.h> +#include <cli.h> #include <command.h> #include <edid.h> #include <environment.h> @@ -562,9 +564,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg if (argc != 3) return CMD_RET_USAGE; -#ifdef CONFIG_BOOT_RETRY_TIME - reset_cmd_timeout(); /* got a good command to get here */ -#endif + bootretry_reset_cmd_timeout(); /* got a good command to get here */ /* * We use the last specified parameters, unless new ones are * entered. @@ -612,7 +612,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg printf(" %08lx", data); } - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (nbytes == 0) { /* * <CR> pressed as only input, don't modify current @@ -621,9 +621,8 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg if (incrflag) addr += size; nbytes = size; -#ifdef CONFIG_BOOT_RETRY_TIME - reset_cmd_timeout(); /* good enough to not time out */ -#endif + /* good enough to not time out */ + bootretry_reset_cmd_timeout(); } #ifdef CONFIG_BOOT_RETRY_TIME else if (nbytes == -2) @@ -640,12 +639,10 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg data = be32_to_cpu(data); nbytes = endp - console_buffer; if (nbytes) { -#ifdef CONFIG_BOOT_RETRY_TIME /* * good enough to not time out */ - reset_cmd_timeout(); -#endif + bootretry_reset_cmd_timeout(); if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0) puts ("Error writing the chip.\n"); #ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 5b03c2d5b..1febddb91 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -12,6 +12,8 @@ */ #include <common.h> +#include <bootretry.h> +#include <cli.h> #include <command.h> #ifdef CONFIG_HAS_DATAFLASH #include <dataflash.h> @@ -1096,9 +1098,7 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[]) if (argc != 2) return CMD_RET_USAGE; -#ifdef CONFIG_BOOT_RETRY_TIME - reset_cmd_timeout(); /* got a good command to get here */ -#endif + bootretry_reset_cmd_timeout(); /* got a good command to get here */ /* We use the last specified parameters, unless new ones are * entered. */ @@ -1149,7 +1149,7 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[]) else printf(" %02x", *((u8 *)ptr)); - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) { /* <CR> pressed as only input, don't modify current * location and move to next. "-" pressed will go back. @@ -1157,9 +1157,8 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[]) if (incrflag) addr += nbytes ? -size : size; nbytes = 1; -#ifdef CONFIG_BOOT_RETRY_TIME - reset_cmd_timeout(); /* good enough to not time out */ -#endif + /* good enough to not time out */ + bootretry_reset_cmd_timeout(); } #ifdef CONFIG_BOOT_RETRY_TIME else if (nbytes == -2) { @@ -1175,11 +1174,9 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[]) #endif nbytes = endp - console_buffer; if (nbytes) { -#ifdef CONFIG_BOOT_RETRY_TIME /* good enough to not time out */ - reset_cmd_timeout(); -#endif + bootretry_reset_cmd_timeout(); if (size == 4) *((u32 *)ptr) = i; #ifdef CONFIG_SYS_SUPPORT_64BIT_DATA diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index c1916c9b5..eea337506 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -71,12 +71,6 @@ U_BOOT_CMD( ); #else /* !CONFIG_GENERIC_MMC */ -enum mmc_state { - MMC_INVALID, - MMC_READ, - MMC_WRITE, - MMC_ERASE, -}; static void print_mmcinfo(struct mmc *mmc) { printf("Device: %s\n", mmc->cfg->name); @@ -98,7 +92,18 @@ static void print_mmcinfo(struct mmc *mmc) printf("Bus Width: %d-bit\n", mmc->bus_width); } - +static struct mmc *init_mmc_device(int dev) +{ + struct mmc *mmc; + mmc = find_mmc_device(dev); + if (!mmc) { + printf("no mmc device at slot %x\n", dev); + return NULL; + } + if (mmc_init(mmc)) + return NULL; + return mmc; +} static int do_mmcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { struct mmc *mmc; @@ -112,351 +117,537 @@ static int do_mmcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } } - mmc = find_mmc_device(curr_device); + mmc = init_mmc_device(curr_device); + if (!mmc) + return CMD_RET_FAILURE; - if (mmc) { - mmc_init(mmc); + print_mmcinfo(mmc); + return CMD_RET_SUCCESS; +} - print_mmcinfo(mmc); - return 0; - } else { - printf("no mmc device at slot %x\n", curr_device); +#ifdef CONFIG_SUPPORT_EMMC_RPMB +static int confirm_key_prog(void) +{ + puts("Warning: Programming authentication key can be done only once !\n" + " Use this command only if you are sure of what you are doing,\n" + "Really perform the key programming? <y/N> "); + if (confirm_yesno()) return 1; + + puts("Authentication key programming aborted\n"); + return 0; +} +static int do_mmcrpmb_key(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + void *key_addr; + struct mmc *mmc = find_mmc_device(curr_device); + + if (argc != 2) + return CMD_RET_USAGE; + + key_addr = (void *)simple_strtoul(argv[1], NULL, 16); + if (!confirm_key_prog()) + return CMD_RET_FAILURE; + if (mmc_rpmb_set_key(mmc, key_addr)) { + printf("ERROR - Key already programmed ?\n"); + return CMD_RET_FAILURE; } + return CMD_RET_SUCCESS; } +static int do_mmcrpmb_read(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + u16 blk, cnt; + void *addr; + int n; + void *key_addr = NULL; + struct mmc *mmc = find_mmc_device(curr_device); -U_BOOT_CMD( - mmcinfo, 1, 0, do_mmcinfo, - "display MMC info", - "- display info of the current MMC device" -); + if (argc < 4) + return CMD_RET_USAGE; -static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) + addr = (void *)simple_strtoul(argv[1], NULL, 16); + blk = simple_strtoul(argv[2], NULL, 16); + cnt = simple_strtoul(argv[3], NULL, 16); + + if (argc == 5) + key_addr = (void *)simple_strtoul(argv[4], NULL, 16); + + printf("\nMMC RPMB read: dev # %d, block # %d, count %d ... ", + curr_device, blk, cnt); + n = mmc_rpmb_read(mmc, addr, blk, cnt, key_addr); + + printf("%d RPMB blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR"); + if (n != cnt) + return CMD_RET_FAILURE; + return CMD_RET_SUCCESS; +} +static int do_mmcrpmb_write(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) { - enum mmc_state state; + u16 blk, cnt; + void *addr; + int n; + void *key_addr; + struct mmc *mmc = find_mmc_device(curr_device); - if (argc < 2) + if (argc != 5) return CMD_RET_USAGE; - if (curr_device < 0) { - if (get_mmc_num() > 0) - curr_device = 0; - else { - puts("No MMC device available\n"); - return 1; - } + addr = (void *)simple_strtoul(argv[1], NULL, 16); + blk = simple_strtoul(argv[2], NULL, 16); + cnt = simple_strtoul(argv[3], NULL, 16); + key_addr = (void *)simple_strtoul(argv[4], NULL, 16); + + printf("\nMMC RPMB write: dev # %d, block # %d, count %d ... ", + curr_device, blk, cnt); + n = mmc_rpmb_write(mmc, addr, blk, cnt, key_addr); + + printf("%d RPMB blocks written: %s\n", n, (n == cnt) ? "OK" : "ERROR"); + if (n != cnt) + return CMD_RET_FAILURE; + return CMD_RET_SUCCESS; +} +static int do_mmcrpmb_counter(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + unsigned long counter; + struct mmc *mmc = find_mmc_device(curr_device); + + if (mmc_rpmb_get_counter(mmc, &counter)) + return CMD_RET_FAILURE; + printf("RPMB Write counter= %lx\n", counter); + return CMD_RET_SUCCESS; +} + +static cmd_tbl_t cmd_rpmb[] = { + U_BOOT_CMD_MKENT(key, 2, 0, do_mmcrpmb_key, "", ""), + U_BOOT_CMD_MKENT(read, 5, 1, do_mmcrpmb_read, "", ""), + U_BOOT_CMD_MKENT(write, 5, 0, do_mmcrpmb_write, "", ""), + U_BOOT_CMD_MKENT(counter, 1, 1, do_mmcrpmb_counter, "", ""), +}; + +static int do_mmcrpmb(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + cmd_tbl_t *cp; + struct mmc *mmc; + char original_part; + int ret; + + cp = find_cmd_tbl(argv[1], cmd_rpmb, ARRAY_SIZE(cmd_rpmb)); + + /* Drop the rpmb subcommand */ + argc--; + argv++; + + if (cp == NULL || argc > cp->maxargs) + return CMD_RET_USAGE; + if (flag == CMD_FLAG_REPEAT && !cp->repeatable) + return CMD_RET_SUCCESS; + + mmc = init_mmc_device(curr_device); + if (!mmc) + return CMD_RET_FAILURE; + + if (!(mmc->version & MMC_VERSION_MMC)) { + printf("It is not a EMMC device\n"); + return CMD_RET_FAILURE; + } + if (mmc->version < MMC_VERSION_4_41) { + printf("RPMB not supported before version 4.41\n"); + return CMD_RET_FAILURE; + } + /* Switch to the RPMB partition */ + original_part = mmc->part_num; + if (mmc->part_num != MMC_PART_RPMB) { + if (mmc_switch_part(curr_device, MMC_PART_RPMB) != 0) + return CMD_RET_FAILURE; + mmc->part_num = MMC_PART_RPMB; } + ret = cp->cmd(cmdtp, flag, argc, argv); - if (strcmp(argv[1], "rescan") == 0) { - struct mmc *mmc; + /* Return to original partition */ + if (mmc->part_num != original_part) { + if (mmc_switch_part(curr_device, original_part) != 0) + return CMD_RET_FAILURE; + mmc->part_num = original_part; + } + return ret; +} +#endif - if (argc != 2) - return CMD_RET_USAGE; +static int do_mmc_read(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + struct mmc *mmc; + u32 blk, cnt, n; + void *addr; - mmc = find_mmc_device(curr_device); - if (!mmc) { - printf("no mmc device at slot %x\n", curr_device); - return 1; - } + if (argc != 4) + return CMD_RET_USAGE; - mmc->has_init = 0; + addr = (void *)simple_strtoul(argv[1], NULL, 16); + blk = simple_strtoul(argv[2], NULL, 16); + cnt = simple_strtoul(argv[3], NULL, 16); - if (mmc_init(mmc)) - return 1; - else - return 0; - } else if (strcmp(argv[1], "part") == 0) { - block_dev_desc_t *mmc_dev; - struct mmc *mmc; + mmc = init_mmc_device(curr_device); + if (!mmc) + return CMD_RET_FAILURE; - if (argc != 2) - return CMD_RET_USAGE; + printf("\nMMC read: dev # %d, block # %d, count %d ... ", + curr_device, blk, cnt); - mmc = find_mmc_device(curr_device); - if (!mmc) { - printf("no mmc device at slot %x\n", curr_device); - return 1; - } - mmc_init(mmc); - mmc_dev = mmc_get_dev(curr_device); - if (mmc_dev != NULL && - mmc_dev->type != DEV_TYPE_UNKNOWN) { - print_part(mmc_dev); - return 0; - } + n = mmc->block_dev.block_read(curr_device, blk, cnt, addr); + /* flush cache after read */ + flush_cache((ulong)addr, cnt * 512); /* FIXME */ + printf("%d blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR"); - puts("get mmc type error!\n"); - return 1; - } else if (strcmp(argv[1], "list") == 0) { - if (argc != 2) - return CMD_RET_USAGE; - print_mmc_devices('\n'); - return 0; - } else if (strcmp(argv[1], "dev") == 0) { - int dev, part = -1; - struct mmc *mmc; - - if (argc == 2) - dev = curr_device; - else if (argc == 3) - dev = simple_strtoul(argv[2], NULL, 10); - else if (argc == 4) { - dev = (int)simple_strtoul(argv[2], NULL, 10); - part = (int)simple_strtoul(argv[3], NULL, 10); - if (part > PART_ACCESS_MASK) { - printf("#part_num shouldn't be larger" - " than %d\n", PART_ACCESS_MASK); - return 1; - } - } else - return CMD_RET_USAGE; + return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE; +} +static int do_mmc_write(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + struct mmc *mmc; + u32 blk, cnt, n; + void *addr; - mmc = find_mmc_device(dev); - if (!mmc) { - printf("no mmc device at slot %x\n", dev); - return 1; - } + if (argc != 4) + return CMD_RET_USAGE; - mmc_init(mmc); - if (part != -1) { - int ret; - if (mmc->part_config == MMCPART_NOAVAILABLE) { - printf("Card doesn't support part_switch\n"); - return 1; - } + addr = (void *)simple_strtoul(argv[1], NULL, 16); + blk = simple_strtoul(argv[2], NULL, 16); + cnt = simple_strtoul(argv[3], NULL, 16); - if (part != mmc->part_num) { - ret = mmc_switch_part(dev, part); - if (!ret) - mmc->part_num = part; + mmc = init_mmc_device(curr_device); + if (!mmc) + return CMD_RET_FAILURE; - printf("switch to partitions #%d, %s\n", - part, (!ret) ? "OK" : "ERROR"); - } - } - curr_device = dev; - if (mmc->part_config == MMCPART_NOAVAILABLE) - printf("mmc%d is current device\n", curr_device); - else - printf("mmc%d(part %d) is current device\n", - curr_device, mmc->part_num); + printf("\nMMC write: dev # %d, block # %d, count %d ... ", + curr_device, blk, cnt); - return 0; -#ifdef CONFIG_SUPPORT_EMMC_BOOT - } else if (strcmp(argv[1], "partconf") == 0) { - int dev; - struct mmc *mmc; - u8 ack, part_num, access; - - if (argc == 6) { - dev = simple_strtoul(argv[2], NULL, 10); - ack = simple_strtoul(argv[3], NULL, 10); - part_num = simple_strtoul(argv[4], NULL, 10); - access = simple_strtoul(argv[5], NULL, 10); - } else { - return CMD_RET_USAGE; - } + if (mmc_getwp(mmc) == 1) { + printf("Error: card is write protected!\n"); + return CMD_RET_FAILURE; + } + n = mmc->block_dev.block_write(curr_device, blk, cnt, addr); + printf("%d blocks written: %s\n", n, (n == cnt) ? "OK" : "ERROR"); - mmc = find_mmc_device(dev); - if (!mmc) { - printf("no mmc device at slot %x\n", dev); - return 1; - } + return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE; +} +static int do_mmc_erase(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + struct mmc *mmc; + u32 blk, cnt, n; - if (IS_SD(mmc)) { - puts("PARTITION_CONFIG only exists on eMMC\n"); - return 1; - } + if (argc != 3) + return CMD_RET_USAGE; - /* acknowledge to be sent during boot operation */ - return mmc_set_part_conf(mmc, ack, part_num, access); - } else if (strcmp(argv[1], "bootbus") == 0) { - int dev; - struct mmc *mmc; - u8 width, reset, mode; - - if (argc == 6) { - dev = simple_strtoul(argv[2], NULL, 10); - width = simple_strtoul(argv[3], NULL, 10); - reset = simple_strtoul(argv[4], NULL, 10); - mode = simple_strtoul(argv[5], NULL, 10); - } else { - return CMD_RET_USAGE; - } + blk = simple_strtoul(argv[1], NULL, 16); + cnt = simple_strtoul(argv[2], NULL, 16); - mmc = find_mmc_device(dev); - if (!mmc) { - printf("no mmc device at slot %x\n", dev); - return 1; - } + mmc = init_mmc_device(curr_device); + if (!mmc) + return CMD_RET_FAILURE; - if (IS_SD(mmc)) { - puts("BOOT_BUS_WIDTH only exists on eMMC\n"); - return 1; - } + printf("\nMMC erase: dev # %d, block # %d, count %d ... ", + curr_device, blk, cnt); - /* acknowledge to be sent during boot operation */ - return mmc_set_boot_bus_width(mmc, width, reset, mode); - } else if (strcmp(argv[1], "bootpart-resize") == 0) { - int dev; - struct mmc *mmc; - u32 bootsize, rpmbsize; - - if (argc == 5) { - dev = simple_strtoul(argv[2], NULL, 10); - bootsize = simple_strtoul(argv[3], NULL, 10); - rpmbsize = simple_strtoul(argv[4], NULL, 10); - } else { - return CMD_RET_USAGE; - } + if (mmc_getwp(mmc) == 1) { + printf("Error: card is write protected!\n"); + return CMD_RET_FAILURE; + } + n = mmc->block_dev.block_erase(curr_device, blk, cnt); + printf("%d blocks erased: %s\n", n, (n == cnt) ? "OK" : "ERROR"); - mmc = find_mmc_device(dev); - if (!mmc) { - printf("no mmc device at slot %x\n", dev); - return 1; - } + return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE; +} +static int do_mmc_rescan(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + struct mmc *mmc; - if (IS_SD(mmc)) { - printf("It is not a EMMC device\n"); - return 1; - } + mmc = find_mmc_device(curr_device); + if (!mmc) { + printf("no mmc device at slot %x\n", curr_device); + return CMD_RET_FAILURE; + } - if (0 == mmc_boot_partition_size_change(mmc, - bootsize, rpmbsize)) { - printf("EMMC boot partition Size %d MB\n", bootsize); - printf("EMMC RPMB partition Size %d MB\n", rpmbsize); - return 0; - } else { - printf("EMMC boot partition Size change Failed.\n"); - return 1; - } - } else if (strcmp(argv[1], "rst-function") == 0) { - /* - * Set the RST_n_ENABLE bit of RST_n_FUNCTION - * The only valid values are 0x0, 0x1 and 0x2 and writing - * a value of 0x1 or 0x2 sets the value permanently. - */ - int dev; - struct mmc *mmc; - u8 enable; - - if (argc == 4) { - dev = simple_strtoul(argv[2], NULL, 10); - enable = simple_strtoul(argv[3], NULL, 10); - } else { - return CMD_RET_USAGE; - } + mmc->has_init = 0; - if (enable > 2 || enable < 0) { - puts("Invalid RST_n_ENABLE value\n"); - return CMD_RET_USAGE; - } + if (mmc_init(mmc)) + return CMD_RET_FAILURE; + return CMD_RET_SUCCESS; +} +static int do_mmc_part(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + block_dev_desc_t *mmc_dev; + struct mmc *mmc; - mmc = find_mmc_device(dev); - if (!mmc) { - printf("no mmc device at slot %x\n", dev); - return 1; + mmc = init_mmc_device(curr_device); + if (!mmc) + return CMD_RET_FAILURE; + + mmc_dev = mmc_get_dev(curr_device); + if (mmc_dev != NULL && mmc_dev->type != DEV_TYPE_UNKNOWN) { + print_part(mmc_dev); + return CMD_RET_SUCCESS; + } + + puts("get mmc type error!\n"); + return CMD_RET_FAILURE; +} +static int do_mmc_dev(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + int dev, part = -1, ret; + struct mmc *mmc; + + if (argc == 1) { + dev = curr_device; + } else if (argc == 2) { + dev = simple_strtoul(argv[1], NULL, 10); + } else if (argc == 3) { + dev = (int)simple_strtoul(argv[1], NULL, 10); + part = (int)simple_strtoul(argv[2], NULL, 10); + if (part > PART_ACCESS_MASK) { + printf("#part_num shouldn't be larger than %d\n", + PART_ACCESS_MASK); + return CMD_RET_FAILURE; } + } else { + return CMD_RET_USAGE; + } + + mmc = init_mmc_device(dev); + if (!mmc) + return CMD_RET_FAILURE; - if (IS_SD(mmc)) { - puts("RST_n_FUNCTION only exists on eMMC\n"); + if (part != -1) { + ret = mmc_select_hwpart(dev, part); + printf("switch to partitions #%d, %s\n", + part, (!ret) ? "OK" : "ERROR"); + if (ret) return 1; - } + } + curr_device = dev; + if (mmc->part_config == MMCPART_NOAVAILABLE) + printf("mmc%d is current device\n", curr_device); + else + printf("mmc%d(part %d) is current device\n", + curr_device, mmc->part_num); - return mmc_set_rst_n_function(mmc, enable); -#endif /* CONFIG_SUPPORT_EMMC_BOOT */ + return CMD_RET_SUCCESS; +} +static int do_mmc_list(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + print_mmc_devices('\n'); + return CMD_RET_SUCCESS; +} +#ifdef CONFIG_SUPPORT_EMMC_BOOT +static int do_mmc_bootbus(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + int dev; + struct mmc *mmc; + u8 width, reset, mode; + + if (argc != 5) + return CMD_RET_USAGE; + dev = simple_strtoul(argv[1], NULL, 10); + width = simple_strtoul(argv[2], NULL, 10); + reset = simple_strtoul(argv[3], NULL, 10); + mode = simple_strtoul(argv[4], NULL, 10); + + mmc = init_mmc_device(dev); + if (!mmc) + return CMD_RET_FAILURE; + + if (IS_SD(mmc)) { + puts("BOOT_BUS_WIDTH only exists on eMMC\n"); + return CMD_RET_FAILURE; } - else if (argc == 3 && strcmp(argv[1], "setdsr") == 0) { - struct mmc *mmc = find_mmc_device(curr_device); - u32 val = simple_strtoul(argv[2], NULL, 16); - int ret; + /* acknowledge to be sent during boot operation */ + return mmc_set_boot_bus_width(mmc, width, reset, mode); +} +static int do_mmc_boot_resize(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + int dev; + struct mmc *mmc; + u32 bootsize, rpmbsize; + + if (argc != 4) + return CMD_RET_USAGE; + dev = simple_strtoul(argv[1], NULL, 10); + bootsize = simple_strtoul(argv[2], NULL, 10); + rpmbsize = simple_strtoul(argv[3], NULL, 10); - if (!mmc) { - printf("no mmc device at slot %x\n", curr_device); - return 1; - } - ret = mmc_set_dsr(mmc, val); - printf("set dsr %s\n", (!ret) ? "OK, force rescan" : "ERROR"); - if (!ret) { - mmc->has_init = 0; - if (mmc_init(mmc)) - return 1; - else - return 0; - } - return ret; + mmc = init_mmc_device(dev); + if (!mmc) + return CMD_RET_FAILURE; + + if (IS_SD(mmc)) { + printf("It is not a EMMC device\n"); + return CMD_RET_FAILURE; } - state = MMC_INVALID; - if (argc == 5 && strcmp(argv[1], "read") == 0) - state = MMC_READ; - else if (argc == 5 && strcmp(argv[1], "write") == 0) - state = MMC_WRITE; - else if (argc == 4 && strcmp(argv[1], "erase") == 0) - state = MMC_ERASE; - - if (state != MMC_INVALID) { - struct mmc *mmc = find_mmc_device(curr_device); - int idx = 2; - u32 blk, cnt, n; - void *addr; - - if (state != MMC_ERASE) { - addr = (void *)simple_strtoul(argv[idx], NULL, 16); - ++idx; - } else - addr = NULL; - blk = simple_strtoul(argv[idx], NULL, 16); - cnt = simple_strtoul(argv[idx + 1], NULL, 16); - - if (!mmc) { - printf("no mmc device at slot %x\n", curr_device); - return 1; - } + if (mmc_boot_partition_size_change(mmc, bootsize, rpmbsize)) { + printf("EMMC boot partition Size change Failed.\n"); + return CMD_RET_FAILURE; + } + + printf("EMMC boot partition Size %d MB\n", bootsize); + printf("EMMC RPMB partition Size %d MB\n", rpmbsize); + return CMD_RET_SUCCESS; +} +static int do_mmc_partconf(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + int dev; + struct mmc *mmc; + u8 ack, part_num, access; - printf("\nMMC %s: dev # %d, block # %d, count %d ... ", - argv[1], curr_device, blk, cnt); + if (argc != 5) + return CMD_RET_USAGE; - mmc_init(mmc); + dev = simple_strtoul(argv[1], NULL, 10); + ack = simple_strtoul(argv[2], NULL, 10); + part_num = simple_strtoul(argv[3], NULL, 10); + access = simple_strtoul(argv[4], NULL, 10); - if ((state == MMC_WRITE || state == MMC_ERASE)) { - if (mmc_getwp(mmc) == 1) { - printf("Error: card is write protected!\n"); - return 1; - } - } + mmc = init_mmc_device(dev); + if (!mmc) + return CMD_RET_FAILURE; - switch (state) { - case MMC_READ: - n = mmc->block_dev.block_read(curr_device, blk, - cnt, addr); - /* flush cache after read */ - flush_cache((ulong)addr, cnt * 512); /* FIXME */ - break; - case MMC_WRITE: - n = mmc->block_dev.block_write(curr_device, blk, - cnt, addr); - break; - case MMC_ERASE: - n = mmc->block_dev.block_erase(curr_device, blk, cnt); - break; - default: - BUG(); - } + if (IS_SD(mmc)) { + puts("PARTITION_CONFIG only exists on eMMC\n"); + return CMD_RET_FAILURE; + } + + /* acknowledge to be sent during boot operation */ + return mmc_set_part_conf(mmc, ack, part_num, access); +} +static int do_mmc_rst_func(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + int dev; + struct mmc *mmc; + u8 enable; + + /* + * Set the RST_n_ENABLE bit of RST_n_FUNCTION + * The only valid values are 0x0, 0x1 and 0x2 and writing + * a value of 0x1 or 0x2 sets the value permanently. + */ + if (argc != 3) + return CMD_RET_USAGE; + + dev = simple_strtoul(argv[1], NULL, 10); + enable = simple_strtoul(argv[2], NULL, 10); + + if (enable > 2 || enable < 0) { + puts("Invalid RST_n_ENABLE value\n"); + return CMD_RET_USAGE; + } + + mmc = init_mmc_device(dev); + if (!mmc) + return CMD_RET_FAILURE; + + if (IS_SD(mmc)) { + puts("RST_n_FUNCTION only exists on eMMC\n"); + return CMD_RET_FAILURE; + } - printf("%d blocks %s: %s\n", - n, argv[1], (n == cnt) ? "OK" : "ERROR"); - return (n == cnt) ? 0 : 1; + return mmc_set_rst_n_function(mmc, enable); +} +#endif +static int do_mmc_setdsr(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + struct mmc *mmc; + u32 val; + int ret; + + if (argc != 2) + return CMD_RET_USAGE; + val = simple_strtoul(argv[2], NULL, 16); + + mmc = find_mmc_device(curr_device); + if (!mmc) { + printf("no mmc device at slot %x\n", curr_device); + return CMD_RET_FAILURE; + } + ret = mmc_set_dsr(mmc, val); + printf("set dsr %s\n", (!ret) ? "OK, force rescan" : "ERROR"); + if (!ret) { + mmc->has_init = 0; + if (mmc_init(mmc)) + return CMD_RET_FAILURE; + else + return CMD_RET_SUCCESS; } + return ret; +} + +static cmd_tbl_t cmd_mmc[] = { + U_BOOT_CMD_MKENT(info, 1, 0, do_mmcinfo, "", ""), + U_BOOT_CMD_MKENT(read, 4, 1, do_mmc_read, "", ""), + U_BOOT_CMD_MKENT(write, 4, 0, do_mmc_write, "", ""), + U_BOOT_CMD_MKENT(erase, 3, 0, do_mmc_erase, "", ""), + U_BOOT_CMD_MKENT(rescan, 1, 1, do_mmc_rescan, "", ""), + U_BOOT_CMD_MKENT(part, 1, 1, do_mmc_part, "", ""), + U_BOOT_CMD_MKENT(dev, 3, 0, do_mmc_dev, "", ""), + U_BOOT_CMD_MKENT(list, 1, 1, do_mmc_list, "", ""), +#ifdef CONFIG_SUPPORT_EMMC_BOOT + U_BOOT_CMD_MKENT(bootbus, 5, 0, do_mmc_bootbus, "", ""), + U_BOOT_CMD_MKENT(bootpart-resize, 3, 0, do_mmc_boot_resize, "", ""), + U_BOOT_CMD_MKENT(partconf, 5, 0, do_mmc_partconf, "", ""), + U_BOOT_CMD_MKENT(rst-function, 3, 0, do_mmc_rst_func, "", ""), +#endif +#ifdef CONFIG_SUPPORT_EMMC_RPMB + U_BOOT_CMD_MKENT(rpmb, CONFIG_SYS_MAXARGS, 1, do_mmcrpmb, "", ""), +#endif + U_BOOT_CMD_MKENT(setdsr, 2, 0, do_mmc_setdsr, "", ""), +}; + +static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + cmd_tbl_t *cp; + + cp = find_cmd_tbl(argv[1], cmd_mmc, ARRAY_SIZE(cmd_mmc)); + + /* Drop the mmc command */ + argc--; + argv++; + + if (cp == NULL || argc > cp->maxargs) + return CMD_RET_USAGE; + if (flag == CMD_FLAG_REPEAT && !cp->repeatable) + return CMD_RET_SUCCESS; - return CMD_RET_USAGE; + if (curr_device < 0) { + if (get_mmc_num() > 0) { + curr_device = 0; + } else { + puts("No MMC device available\n"); + return CMD_RET_FAILURE; + } + } + return cp->cmd(cmdtp, flag, argc, argv); } U_BOOT_CMD( - mmc, 6, 1, do_mmcops, + mmc, 7, 1, do_mmcops, "MMC sub system", - "read addr blk# cnt\n" + "info - display info of the current MMC device\n" + "mmc read addr blk# cnt\n" "mmc write addr blk# cnt\n" "mmc erase blk# cnt\n" "mmc rescan\n" @@ -474,6 +665,20 @@ U_BOOT_CMD( " - Change the RST_n_FUNCTION field of the specified device\n" " WARNING: This is a write-once field and 0 / 1 / 2 are the only valid values.\n" #endif - "mmc setdsr - set DSR register value\n" +#ifdef CONFIG_SUPPORT_EMMC_RPMB + "mmc rpmb read addr blk# cnt [address of auth-key] - block size is 256 bytes\n" + "mmc rpmb write addr blk# cnt <address of auth-key> - block size is 256 bytes\n" + "mmc rpmb key <address of auth-key> - program the RPMB authentication key.\n" + "mmc rpmb counter - read the value of the write counter\n" +#endif + "mmc setdsr <value> - set DSR register value\n" ); + +/* Old command kept for compatibility. Same as 'mmc info' */ +U_BOOT_CMD( + mmcinfo, 1, 0, do_mmcinfo, + "display MMC info", + "- display info of the current MMC device" +); + #endif /* !CONFIG_GENERIC_MMC */ diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 04ab0f19b..a84f7dc2d 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -605,22 +605,16 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) opts.spread = spread; if (scrub) { - if (!scrub_yes) - puts(scrub_warn); - - if (scrub_yes) + if (scrub_yes) { opts.scrub = 1; - else if (getc() == 'y') { - puts("y"); - if (getc() == '\r') + } else { + puts(scrub_warn); + if (confirm_yesno()) { opts.scrub = 1; - else { + } else { puts("scrub aborted\n"); return 1; } - } else { - puts("scrub aborted\n"); - return 1; } } ret = nand_erase_opts(nand, &opts); diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index f4e306ceb..e6c33956e 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -25,6 +25,7 @@ */ #include <common.h> +#include <cli.h> #include <command.h> #include <environment.h> #include <search.h> @@ -408,7 +409,7 @@ int do_env_ask(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; /* prompt for input */ - len = readline(message); + len = cli_readline(message); if (size < len) console_buffer[size] = '\0'; @@ -591,7 +592,7 @@ static int do_env_edit(cmd_tbl_t *cmdtp, int flag, int argc, else buffer[0] = '\0'; - if (readline_into_buffer("edit: ", buffer, 0) < 0) + if (cli_readline_into_buffer("edit: ", buffer, 0) < 0) return 1; return setenv(argv[1], buffer); diff --git a/common/cmd_otp.c b/common/cmd_otp.c index 67808aa37..593bb8c65 100644 --- a/common/cmd_otp.c +++ b/common/cmd_otp.c @@ -158,21 +158,9 @@ int do_otp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) lowup(half + count - 1), page + (half + count - 1) / 2, half + count ); - - i = 0; - while (1) { - if (tstc()) { - const char exp_ans[] = "YES\r"; - char c; - putc(c = getc()); - if (exp_ans[i++] != c) { - printf(" Aborting\n"); - return 1; - } else if (!exp_ans[i]) { - puts("\n"); - break; - } - } + if (!confirm_yesno()) { + printf(" Aborting\n"); + return 1; } } diff --git a/common/cmd_part.c b/common/cmd_part.c index 14248548d..c84bc27b4 100644 --- a/common/cmd_part.c +++ b/common/cmd_part.c @@ -82,7 +82,7 @@ int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( part, 5, 1, do_part, "disk partition related commands", - "uuid <interface> <dev>:<part>\n" + "part uuid <interface> <dev>:<part>\n" " - print partition UUID\n" "part uuid <interface> <dev>:<part> <varname>\n" " - set environment variable to partition UUID\n" diff --git a/common/cmd_pci.c b/common/cmd_pci.c index d3e7c089b..a1ba42e2f 100644 --- a/common/cmd_pci.c +++ b/common/cmd_pci.c @@ -14,6 +14,8 @@ */ #include <common.h> +#include <bootretry.h> +#include <cli.h> #include <command.h> #include <asm/processor.h> #include <asm/io.h> @@ -345,7 +347,7 @@ pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag printf(" %02x", val1); } - nbytes = readline (" ? "); + nbytes = cli_readline(" ? "); if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) { /* <CR> pressed as only input, don't modify current * location and move to next. "-" pressed will go back. @@ -353,9 +355,8 @@ pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag if (incrflag) addr += nbytes ? -size : size; nbytes = 1; -#ifdef CONFIG_BOOT_RETRY_TIME - reset_cmd_timeout(); /* good enough to not time out */ -#endif + /* good enough to not time out */ + bootretry_reset_cmd_timeout(); } #ifdef CONFIG_BOOT_RETRY_TIME else if (nbytes == -2) { @@ -367,11 +368,9 @@ pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag i = simple_strtoul(console_buffer, &endp, 16); nbytes = endp - console_buffer; if (nbytes) { -#ifdef CONFIG_BOOT_RETRY_TIME /* good enough to not time out */ - reset_cmd_timeout(); -#endif + bootretry_reset_cmd_timeout(); pci_cfg_write (bdf, addr, size, i); if (incrflag) addr += size; diff --git a/common/cmd_usb_mass_storage.c b/common/cmd_usb_mass_storage.c index d8d9efd4f..2c879ea08 100644 --- a/common/cmd_usb_mass_storage.c +++ b/common/cmd_usb_mass_storage.c @@ -9,41 +9,107 @@ #include <common.h> #include <command.h> #include <g_dnl.h> +#include <part.h> #include <usb.h> #include <usb_mass_storage.h> +static int ums_read_sector(struct ums *ums_dev, + ulong start, lbaint_t blkcnt, void *buf) +{ + block_dev_desc_t *block_dev = ums_dev->block_dev; + lbaint_t blkstart = start + ums_dev->start_sector; + int dev_num = block_dev->dev; + + return block_dev->block_read(dev_num, blkstart, blkcnt, buf); +} + +static int ums_write_sector(struct ums *ums_dev, + ulong start, lbaint_t blkcnt, const void *buf) +{ + block_dev_desc_t *block_dev = ums_dev->block_dev; + lbaint_t blkstart = start + ums_dev->start_sector; + int dev_num = block_dev->dev; + + return block_dev->block_write(dev_num, blkstart, blkcnt, buf); +} + +static struct ums ums_dev = { + .read_sector = ums_read_sector, + .write_sector = ums_write_sector, + .name = "UMS disk", +}; + +struct ums *ums_init(const char *devtype, const char *devnum) +{ + block_dev_desc_t *block_dev; + int ret; + + ret = get_device(devtype, devnum, &block_dev); + if (ret < 0) + return NULL; + + /* f_mass_storage.c assumes SECTOR_SIZE sectors */ + if (block_dev->blksz != SECTOR_SIZE) + return NULL; + + ums_dev.block_dev = block_dev; + ums_dev.start_sector = 0; + ums_dev.num_sectors = block_dev->lba; + + printf("UMS: disk start sector: %#x, count: %#x\n", + ums_dev.start_sector, ums_dev.num_sectors); + + return &ums_dev; +} + int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + const char *usb_controller; + const char *devtype; + const char *devnum; + struct ums *ums; + unsigned int controller_index; + int rc; + int cable_ready_timeout __maybe_unused; + if (argc < 3) return CMD_RET_USAGE; - const char *usb_controller = argv[1]; - const char *mmc_devstring = argv[2]; - - unsigned int dev_num = simple_strtoul(mmc_devstring, NULL, 0); + usb_controller = argv[1]; + if (argc >= 4) { + devtype = argv[2]; + devnum = argv[3]; + } else { + devtype = "mmc"; + devnum = argv[2]; + } - struct ums *ums = ums_init(dev_num); + ums = ums_init(devtype, devnum); if (!ums) return CMD_RET_FAILURE; - unsigned int controller_index = (unsigned int)(simple_strtoul( - usb_controller, NULL, 0)); + controller_index = (unsigned int)(simple_strtoul( + usb_controller, NULL, 0)); if (board_usb_init(controller_index, USB_INIT_DEVICE)) { error("Couldn't init USB controller."); return CMD_RET_FAILURE; } - int rc = fsg_init(ums); + rc = fsg_init(ums); if (rc) { error("fsg_init failed"); return CMD_RET_FAILURE; } - g_dnl_register("usb_dnl_ums"); + rc = g_dnl_register("usb_dnl_ums"); + if (rc) { + error("g_dnl_register failed"); + return CMD_RET_FAILURE; + } /* Timeout unit: seconds */ - int cable_ready_timeout = UMS_CABLE_READY_TIMEOUT; + cable_ready_timeout = UMS_CABLE_READY_TIMEOUT; if (!g_dnl_board_usb_cable_connected()) { /* @@ -91,7 +157,8 @@ exit: return CMD_RET_SUCCESS; } -U_BOOT_CMD(ums, CONFIG_SYS_MAXARGS, 1, do_usb_mass_storage, +U_BOOT_CMD(ums, 4, 1, do_usb_mass_storage, "Use the UMS [User Mass Storage]", - "ums <USB_controller> <mmc_dev> e.g. ums 0 0" + "ums <USB_controller> [<devtype>] <devnum> e.g. ums 0 mmc 0\n" + " devtype defaults to mmc" ); diff --git a/common/console.c b/common/console.c index 2dfb78888..5453726f6 100644 --- a/common/console.c +++ b/common/console.c @@ -537,7 +537,33 @@ int ctrlc(void) } return 0; } - +/* Reads user's confirmation. + Returns 1 if user's input is "y", "Y", "yes" or "YES" +*/ +int confirm_yesno(void) +{ + int i; + char str_input[5]; + + /* Flush input */ + while (tstc()) + getc(); + i = 0; + while (i < sizeof(str_input)) { + str_input[i] = getc(); + putc(str_input[i]); + if (str_input[i] == '\r') + break; + i++; + } + putc('\n'); + if (strncmp(str_input, "y\r", 2) == 0 || + strncmp(str_input, "Y\r", 2) == 0 || + strncmp(str_input, "yes\r", 4) == 0 || + strncmp(str_input, "YES\r", 4) == 0) + return 1; + return 0; +} /* pass 1 to disable ctrlc() checking, 0 to enable. * returns previous state */ diff --git a/common/image-android.c b/common/image-android.c new file mode 100644 index 000000000..6ded7e2c9 --- /dev/null +++ b/common/image-android.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2011 Sebastian Andrzej Siewior <bigeasy@linutronix.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <image.h> +#include <android_image.h> + +static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1]; + +int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, + ulong *os_data, ulong *os_len) +{ + /* + * Not all Android tools use the id field for signing the image with + * sha1 (or anything) so we don't check it. It is not obvious that the + * string is null terminated so we take care of this. + */ + strncpy(andr_tmp_str, hdr->name, ANDR_BOOT_NAME_SIZE); + andr_tmp_str[ANDR_BOOT_NAME_SIZE] = '\0'; + if (strlen(andr_tmp_str)) + printf("Android's image name: %s\n", andr_tmp_str); + + printf("Kernel load addr 0x%08x size %u KiB\n", + hdr->kernel_addr, DIV_ROUND_UP(hdr->kernel_size, 1024)); + strncpy(andr_tmp_str, hdr->cmdline, ANDR_BOOT_ARGS_SIZE); + andr_tmp_str[ANDR_BOOT_ARGS_SIZE] = '\0'; + if (strlen(andr_tmp_str)) { + printf("Kernel command line: %s\n", andr_tmp_str); + setenv("bootargs", andr_tmp_str); + } + if (hdr->ramdisk_size) + printf("RAM disk load addr 0x%08x size %u KiB\n", + hdr->ramdisk_addr, + DIV_ROUND_UP(hdr->ramdisk_size, 1024)); + + if (os_data) { + *os_data = (ulong)hdr; + *os_data += hdr->page_size; + } + if (os_len) + *os_len = hdr->kernel_size; + return 0; +} + +int android_image_check_header(const struct andr_img_hdr *hdr) +{ + return memcmp(ANDR_BOOT_MAGIC, hdr->magic, ANDR_BOOT_MAGIC_SIZE); +} + +ulong android_image_get_end(const struct andr_img_hdr *hdr) +{ + u32 size = 0; + /* + * The header takes a full page, the remaining components are aligned + * on page boundary + */ + size += hdr->page_size; + size += ALIGN(hdr->kernel_size, hdr->page_size); + size += ALIGN(hdr->ramdisk_size, hdr->page_size); + size += ALIGN(hdr->second_size, hdr->page_size); + + return size; +} + +ulong android_image_get_kload(const struct andr_img_hdr *hdr) +{ + return hdr->kernel_addr; +} + +int android_image_get_ramdisk(const struct andr_img_hdr *hdr, + ulong *rd_data, ulong *rd_len) +{ + if (!hdr->ramdisk_size) + return -1; + *rd_data = (unsigned long)hdr; + *rd_data += hdr->page_size; + *rd_data += ALIGN(hdr->kernel_size, hdr->page_size); + + *rd_len = hdr->ramdisk_size; + return 0; +} diff --git a/common/image.c b/common/image.c index fcc5a9c3e..26eb89a2b 100644 --- a/common/image.c +++ b/common/image.c @@ -139,6 +139,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, { IH_TYPE_UBLIMAGE, "ublimage", "Davinci UBL image",}, { IH_TYPE_MXSIMAGE, "mxsimage", "Freescale MXS Boot Image",}, + { IH_TYPE_ATMELIMAGE, "atmelimage", "ATMEL ROM-Boot Image",}, { -1, "", "", }, }; @@ -660,10 +661,12 @@ int genimg_get_format(const void *img_addr) if (image_check_magic(hdr)) format = IMAGE_FORMAT_LEGACY; #if defined(CONFIG_FIT) || defined(CONFIG_OF_LIBFDT) - else { - if (fdt_check_header(img_addr) == 0) - format = IMAGE_FORMAT_FIT; - } + else if (fdt_check_header(img_addr) == 0) + format = IMAGE_FORMAT_FIT; +#endif +#ifdef CONFIG_ANDROID_BOOT_IMAGE + else if (android_image_check_header(img_addr) == 0) + format = IMAGE_FORMAT_ANDROID; #endif return format; @@ -933,7 +936,15 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images, (ulong)images->legacy_hdr_os); image_multi_getimg(images->legacy_hdr_os, 1, &rd_data, &rd_len); - } else { + } +#ifdef CONFIG_ANDROID_BOOT_IMAGE + else if ((genimg_get_format(images) == IMAGE_FORMAT_ANDROID) && + (!android_image_get_ramdisk((void *)images->os.start, + &rd_data, &rd_len))) { + /* empty */ + } +#endif + else { /* * no initrd image */ diff --git a/common/main.c b/common/main.c index 9bee7bdc6..32618f139 100644 --- a/common/main.c +++ b/common/main.c @@ -2,25 +2,15 @@ * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Add to readline cmdline-editing by - * (C) Copyright 2005 - * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com> - * * SPDX-License-Identifier: GPL-2.0+ */ /* #define DEBUG */ #include <common.h> -#include <command.h> -#include <fdtdec.h> -#include <hush.h> -#include <malloc.h> -#include <menu.h> -#include <post.h> +#include <autoboot.h> +#include <cli.h> #include <version.h> -#include <watchdog.h> -#include <linux/ctype.h> DECLARE_GLOBAL_DATA_PTR; @@ -30,400 +20,43 @@ DECLARE_GLOBAL_DATA_PTR; void inline __show_boot_progress (int val) {} void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress"))); -#define MAX_DELAY_STOP_STR 32 - -#define DEBUG_PARSER 0 /* set to 1 to debug */ - -#define debug_parser(fmt, args...) \ - debug_cond(DEBUG_PARSER, fmt, ##args) - -#ifndef DEBUG_BOOTKEYS -#define DEBUG_BOOTKEYS 0 -#endif -#define debug_bootkeys(fmt, args...) \ - debug_cond(DEBUG_BOOTKEYS, fmt, ##args) - -char console_buffer[CONFIG_SYS_CBSIZE + 1]; /* console I/O buffer */ - -static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen); -static const char erase_seq[] = "\b \b"; /* erase sequence */ -static const char tab_seq[] = " "; /* used to expand TABs */ - -#ifdef CONFIG_BOOT_RETRY_TIME -static uint64_t endtime = 0; /* must be set, default is instant timeout */ -static int retry_time = -1; /* -1 so can call readline before main_loop */ -#endif - -#define endtick(seconds) (get_ticks() + (uint64_t)(seconds) * get_tbclk()) - -#ifndef CONFIG_BOOT_RETRY_MIN -#define CONFIG_BOOT_RETRY_MIN CONFIG_BOOT_RETRY_TIME -#endif - -#ifdef CONFIG_MODEM_SUPPORT -int do_mdm_init = 0; -extern void mdm_init(void); /* defined in board.c */ -#endif - -/*************************************************************************** - * Watch for 'delay' seconds for autoboot stop or autoboot delay string. - * returns: 0 - no key string, allow autoboot 1 - got key string, abort - */ -#if defined(CONFIG_BOOTDELAY) -# if defined(CONFIG_AUTOBOOT_KEYED) -static int abortboot_keyed(int bootdelay) -{ - int abort = 0; - uint64_t etime = endtick(bootdelay); - struct { - char* str; - u_int len; - int retry; - } - delaykey [] = { - { str: getenv ("bootdelaykey"), retry: 1 }, - { str: getenv ("bootdelaykey2"), retry: 1 }, - { str: getenv ("bootstopkey"), retry: 0 }, - { str: getenv ("bootstopkey2"), retry: 0 }, - }; - - char presskey [MAX_DELAY_STOP_STR]; - u_int presskey_len = 0; - u_int presskey_max = 0; - u_int i; - -#ifndef CONFIG_ZERO_BOOTDELAY_CHECK - if (bootdelay == 0) - return 0; -#endif - -# ifdef CONFIG_AUTOBOOT_PROMPT - printf(CONFIG_AUTOBOOT_PROMPT); -# endif - -# ifdef CONFIG_AUTOBOOT_DELAY_STR - if (delaykey[0].str == NULL) - delaykey[0].str = CONFIG_AUTOBOOT_DELAY_STR; -# endif -# ifdef CONFIG_AUTOBOOT_DELAY_STR2 - if (delaykey[1].str == NULL) - delaykey[1].str = CONFIG_AUTOBOOT_DELAY_STR2; -# endif -# ifdef CONFIG_AUTOBOOT_STOP_STR - if (delaykey[2].str == NULL) - delaykey[2].str = CONFIG_AUTOBOOT_STOP_STR; -# endif -# ifdef CONFIG_AUTOBOOT_STOP_STR2 - if (delaykey[3].str == NULL) - delaykey[3].str = CONFIG_AUTOBOOT_STOP_STR2; -# endif - - for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i ++) { - delaykey[i].len = delaykey[i].str == NULL ? - 0 : strlen (delaykey[i].str); - delaykey[i].len = delaykey[i].len > MAX_DELAY_STOP_STR ? - MAX_DELAY_STOP_STR : delaykey[i].len; - - presskey_max = presskey_max > delaykey[i].len ? - presskey_max : delaykey[i].len; - - debug_bootkeys("%s key:<%s>\n", - delaykey[i].retry ? "delay" : "stop", - delaykey[i].str ? delaykey[i].str : "NULL"); - } - - /* In order to keep up with incoming data, check timeout only - * when catch up. - */ - do { - if (tstc()) { - if (presskey_len < presskey_max) { - presskey [presskey_len ++] = getc(); - } - else { - for (i = 0; i < presskey_max - 1; i ++) - presskey [i] = presskey [i + 1]; - - presskey [i] = getc(); - } - } - - for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i ++) { - if (delaykey[i].len > 0 && - presskey_len >= delaykey[i].len && - memcmp (presskey + presskey_len - delaykey[i].len, - delaykey[i].str, - delaykey[i].len) == 0) { - debug_bootkeys("got %skey\n", - delaykey[i].retry ? "delay" : - "stop"); - -# ifdef CONFIG_BOOT_RETRY_TIME - /* don't retry auto boot */ - if (! delaykey[i].retry) - retry_time = -1; -# endif - abort = 1; - } - } - } while (!abort && get_ticks() <= etime); - - if (!abort) - debug_bootkeys("key timeout\n"); - -#ifdef CONFIG_SILENT_CONSOLE - if (abort) - gd->flags &= ~GD_FLG_SILENT; -#endif - - return abort; -} - -# else /* !defined(CONFIG_AUTOBOOT_KEYED) */ - -#ifdef CONFIG_MENUKEY -static int menukey = 0; -#endif - -static int abortboot_normal(int bootdelay) +static void modem_init(void) { - int abort = 0; - unsigned long ts; - -#ifdef CONFIG_MENUPROMPT - printf(CONFIG_MENUPROMPT); -#else - if (bootdelay >= 0) - printf("Hit any key to stop autoboot: %2d ", bootdelay); -#endif - -#if defined CONFIG_ZERO_BOOTDELAY_CHECK - /* - * Check if key already pressed - * Don't check if bootdelay < 0 - */ - if (bootdelay >= 0) { - if (tstc()) { /* we got a key press */ - (void) getc(); /* consume input */ - puts ("\b\b\b 0"); - abort = 1; /* don't auto boot */ - } - } -#endif - - while ((bootdelay > 0) && (!abort)) { - --bootdelay; - /* delay 1000 ms */ - ts = get_timer(0); - do { - if (tstc()) { /* we got a key press */ - abort = 1; /* don't auto boot */ - bootdelay = 0; /* no more delay */ -# ifdef CONFIG_MENUKEY - menukey = getc(); -# else - (void) getc(); /* consume input */ -# endif - break; - } - udelay(10000); - } while (!abort && get_timer(ts) < 1000); - - printf("\b\b\b%2d ", bootdelay); - } - - putc('\n'); - -#ifdef CONFIG_SILENT_CONSOLE - if (abort) - gd->flags &= ~GD_FLG_SILENT; -#endif - - return abort; -} -# endif /* CONFIG_AUTOBOOT_KEYED */ - -static int abortboot(int bootdelay) -{ -#ifdef CONFIG_AUTOBOOT_KEYED - return abortboot_keyed(bootdelay); -#else - return abortboot_normal(bootdelay); -#endif -} -#endif /* CONFIG_BOOTDELAY */ - -/* - * Runs the given boot command securely. Specifically: - * - Doesn't run the command with the shell (run_command or parse_string_outer), - * since that's a lot of code surface that an attacker might exploit. - * Because of this, we don't do any argument parsing--the secure boot command - * has to be a full-fledged u-boot command. - * - Doesn't check for keypresses before booting, since that could be a - * security hole; also disables Ctrl-C. - * - Doesn't allow the command to return. - * - * Upon any failures, this function will drop into an infinite loop after - * printing the error message to console. - */ - -#if defined(CONFIG_BOOTDELAY) && defined(CONFIG_OF_CONTROL) -static void secure_boot_cmd(char *cmd) -{ - cmd_tbl_t *cmdtp; - int rc; - - if (!cmd) { - printf("## Error: Secure boot command not specified\n"); - goto err; - } - - /* Disable Ctrl-C just in case some command is used that checks it. */ - disable_ctrlc(1); +#ifdef CONFIG_MODEM_SUPPORT + debug("DEBUG: main_loop: gd->do_mdm_init=%lu\n", gd->do_mdm_init); + if (gd->do_mdm_init) { + char *str = getenv("mdm_cmd"); - /* Find the command directly. */ - cmdtp = find_cmd(cmd); - if (!cmdtp) { - printf("## Error: \"%s\" not defined\n", cmd); - goto err; + setenv("preboot", str); /* set or delete definition */ + mdm_init(); /* wait for modem connection */ } - - /* Run the command, forcing no flags and faking argc and argv. */ - rc = (cmdtp->cmd)(cmdtp, 0, 1, &cmd); - - /* Shouldn't ever return from boot command. */ - printf("## Error: \"%s\" returned (code %d)\n", cmd, rc); - -err: - /* - * Not a whole lot to do here. Rebooting won't help much, since we'll - * just end up right back here. Just loop. - */ - hang(); -} - -static void process_fdt_options(const void *blob) -{ - ulong addr; - - /* Add an env variable to point to a kernel payload, if available */ - addr = fdtdec_get_config_int(gd->fdt_blob, "kernel-offset", 0); - if (addr) - setenv_addr("kernaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr)); - - /* Add an env variable to point to a root disk, if available */ - addr = fdtdec_get_config_int(gd->fdt_blob, "rootdisk-offset", 0); - if (addr) - setenv_addr("rootaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr)); +#endif /* CONFIG_MODEM_SUPPORT */ } -#endif /* CONFIG_OF_CONTROL */ -#ifdef CONFIG_BOOTDELAY -static void process_boot_delay(void) +static void run_preboot_environment_command(void) { -#ifdef CONFIG_OF_CONTROL - char *env; -#endif - char *s; - int bootdelay; -#ifdef CONFIG_BOOTCOUNT_LIMIT - unsigned long bootcount = 0; - unsigned long bootlimit = 0; -#endif /* CONFIG_BOOTCOUNT_LIMIT */ - -#ifdef CONFIG_BOOTCOUNT_LIMIT - bootcount = bootcount_load(); - bootcount++; - bootcount_store (bootcount); - setenv_ulong("bootcount", bootcount); - bootlimit = getenv_ulong("bootlimit", 10, 0); -#endif /* CONFIG_BOOTCOUNT_LIMIT */ - - s = getenv ("bootdelay"); - bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY; - -#ifdef CONFIG_OF_CONTROL - bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay", - bootdelay); -#endif - - debug ("### main_loop entered: bootdelay=%d\n\n", bootdelay); - -#if defined(CONFIG_MENU_SHOW) - bootdelay = menu_show(bootdelay); -#endif -# ifdef CONFIG_BOOT_RETRY_TIME - init_cmd_timeout (); -# endif /* CONFIG_BOOT_RETRY_TIME */ - -#ifdef CONFIG_POST - if (gd->flags & GD_FLG_POSTFAIL) { - s = getenv("failbootcmd"); - } - else -#endif /* CONFIG_POST */ -#ifdef CONFIG_BOOTCOUNT_LIMIT - if (bootlimit && (bootcount > bootlimit)) { - printf ("Warning: Bootlimit (%u) exceeded. Using altbootcmd.\n", - (unsigned)bootlimit); - s = getenv ("altbootcmd"); - } - else -#endif /* CONFIG_BOOTCOUNT_LIMIT */ - s = getenv ("bootcmd"); -#ifdef CONFIG_OF_CONTROL - /* Allow the fdt to override the boot command */ - env = fdtdec_get_config_string(gd->fdt_blob, "bootcmd"); - if (env) - s = env; - - process_fdt_options(gd->fdt_blob); - - /* - * If the bootsecure option was chosen, use secure_boot_cmd(). - * Always use 'env' in this case, since bootsecure requres that the - * bootcmd was specified in the FDT too. - */ - if (fdtdec_get_config_int(gd->fdt_blob, "bootsecure", 0)) - secure_boot_cmd(env); - -#endif /* CONFIG_OF_CONTROL */ - - debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>"); +#ifdef CONFIG_PREBOOT + char *p; - if (bootdelay != -1 && s && !abortboot(bootdelay)) { -#if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC) + p = getenv("preboot"); + if (p != NULL) { +# ifdef CONFIG_AUTOBOOT_KEYED int prev = disable_ctrlc(1); /* disable Control C checking */ -#endif +# endif - run_command_list(s, -1, 0); + run_command_list(p, -1, 0); -#if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC) +# ifdef CONFIG_AUTOBOOT_KEYED disable_ctrlc(prev); /* restore Control C checking */ -#endif - } - -#ifdef CONFIG_MENUKEY - if (menukey == CONFIG_MENUKEY) { - s = getenv("menucmd"); - if (s) - run_command_list(s, -1, 0); +# endif } -#endif /* CONFIG_MENUKEY */ +#endif /* CONFIG_PREBOOT */ } -#endif /* CONFIG_BOOTDELAY */ +/* We come here after U-Boot is initialised and ready to process commands */ void main_loop(void) { -#ifndef CONFIG_SYS_HUSH_PARSER - static char lastcommand[CONFIG_SYS_CBSIZE] = { 0, }; - int len; - int rc = 1; - int flag; -#endif -#ifdef CONFIG_PREBOOT - char *p; -#endif + const char *s; bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop"); @@ -433,1126 +66,24 @@ void main_loop(void) puts("upgraded by the late 2014 may break or be removed.\n"); #endif -#ifdef CONFIG_MODEM_SUPPORT - debug("DEBUG: main_loop: do_mdm_init=%d\n", do_mdm_init); - if (do_mdm_init) { - char *str = strdup(getenv("mdm_cmd")); - setenv("preboot", str); /* set or delete definition */ - if (str != NULL) - free(str); - mdm_init(); /* wait for modem connection */ - } -#endif /* CONFIG_MODEM_SUPPORT */ - + modem_init(); #ifdef CONFIG_VERSION_VARIABLE - { - setenv("ver", version_string); /* set version variable */ - } + setenv("ver", version_string); /* set version variable */ #endif /* CONFIG_VERSION_VARIABLE */ -#ifdef CONFIG_SYS_HUSH_PARSER - u_boot_hush_start(); -#endif - -#if defined(CONFIG_HUSH_INIT_VAR) - hush_init_var(); -#endif - -#ifdef CONFIG_PREBOOT - p = getenv("preboot"); - if (p != NULL) { -# ifdef CONFIG_AUTOBOOT_KEYED - int prev = disable_ctrlc(1); /* disable Control C checking */ -# endif + cli_init(); - run_command_list(p, -1, 0); - -# ifdef CONFIG_AUTOBOOT_KEYED - disable_ctrlc(prev); /* restore Control C checking */ -# endif - } -#endif /* CONFIG_PREBOOT */ + run_preboot_environment_command(); #if defined(CONFIG_UPDATE_TFTP) update_tftp(0UL); #endif /* CONFIG_UPDATE_TFTP */ -#ifdef CONFIG_BOOTDELAY - process_boot_delay(); -#endif - /* - * Main Loop for Monitor Command Processing - */ -#ifdef CONFIG_SYS_HUSH_PARSER - parse_file_outer(); - /* This point is never reached */ - for (;;); -#else - for (;;) { -#ifdef CONFIG_BOOT_RETRY_TIME - if (rc >= 0) { - /* Saw enough of a valid command to - * restart the timeout. - */ - reset_cmd_timeout(); - } -#endif - len = readline (CONFIG_SYS_PROMPT); - - flag = 0; /* assume no special flags for now */ - if (len > 0) - strcpy (lastcommand, console_buffer); - else if (len == 0) - flag |= CMD_FLAG_REPEAT; -#ifdef CONFIG_BOOT_RETRY_TIME - else if (len == -2) { - /* -2 means timed out, retry autoboot - */ - puts ("\nTimed out waiting for command\n"); -# ifdef CONFIG_RESET_TO_RETRY - /* Reinit board to run initialization code again */ - do_reset (NULL, 0, 0, NULL); -# else - return; /* retry autoboot */ -# endif - } -#endif - - if (len == -1) - puts ("<INTERRUPT>\n"); - else - rc = run_command(lastcommand, flag); - - if (rc <= 0) { - /* invalid command or not repeatable, forget it */ - lastcommand[0] = 0; - } - } -#endif /*CONFIG_SYS_HUSH_PARSER*/ -} - -#ifdef CONFIG_BOOT_RETRY_TIME -/*************************************************************************** - * initialize command line timeout - */ -void init_cmd_timeout(void) -{ - char *s = getenv ("bootretry"); - - if (s != NULL) - retry_time = (int)simple_strtol(s, NULL, 10); - else - retry_time = CONFIG_BOOT_RETRY_TIME; - - if (retry_time >= 0 && retry_time < CONFIG_BOOT_RETRY_MIN) - retry_time = CONFIG_BOOT_RETRY_MIN; -} - -/*************************************************************************** - * reset command line timeout to retry_time seconds - */ -void reset_cmd_timeout(void) -{ - endtime = endtick(retry_time); -} -#endif - -#ifdef CONFIG_CMDLINE_EDITING - -/* - * cmdline-editing related codes from vivi. - * Author: Janghoon Lyu <nandy@mizi.com> - */ - -#define putnstr(str,n) do { \ - printf ("%.*s", (int)n, str); \ - } while (0) - -#define CTL_CH(c) ((c) - 'a' + 1) -#define CTL_BACKSPACE ('\b') -#define DEL ((char)255) -#define DEL7 ((char)127) -#define CREAD_HIST_CHAR ('!') - -#define getcmd_putch(ch) putc(ch) -#define getcmd_getch() getc() -#define getcmd_cbeep() getcmd_putch('\a') - -#define HIST_MAX 20 -#define HIST_SIZE CONFIG_SYS_CBSIZE - -static int hist_max; -static int hist_add_idx; -static int hist_cur = -1; -static unsigned hist_num; - -static char *hist_list[HIST_MAX]; -static char hist_lines[HIST_MAX][HIST_SIZE + 1]; /* Save room for NULL */ - -#define add_idx_minus_one() ((hist_add_idx == 0) ? hist_max : hist_add_idx-1) - -static void hist_init(void) -{ - int i; - - hist_max = 0; - hist_add_idx = 0; - hist_cur = -1; - hist_num = 0; - - for (i = 0; i < HIST_MAX; i++) { - hist_list[i] = hist_lines[i]; - hist_list[i][0] = '\0'; - } -} - -static void cread_add_to_hist(char *line) -{ - strcpy(hist_list[hist_add_idx], line); - - if (++hist_add_idx >= HIST_MAX) - hist_add_idx = 0; - - if (hist_add_idx > hist_max) - hist_max = hist_add_idx; - - hist_num++; -} - -static char* hist_prev(void) -{ - char *ret; - int old_cur; - - if (hist_cur < 0) - return NULL; - - old_cur = hist_cur; - if (--hist_cur < 0) - hist_cur = hist_max; - - if (hist_cur == hist_add_idx) { - hist_cur = old_cur; - ret = NULL; - } else - ret = hist_list[hist_cur]; - - return (ret); -} - -static char* hist_next(void) -{ - char *ret; - - if (hist_cur < 0) - return NULL; - - if (hist_cur == hist_add_idx) - return NULL; - - if (++hist_cur > hist_max) - hist_cur = 0; - - if (hist_cur == hist_add_idx) { - ret = ""; - } else - ret = hist_list[hist_cur]; - - return (ret); -} - -#ifndef CONFIG_CMDLINE_EDITING -static void cread_print_hist_list(void) -{ - int i; - unsigned long n; - - n = hist_num - hist_max; - - i = hist_add_idx + 1; - while (1) { - if (i > hist_max) - i = 0; - if (i == hist_add_idx) - break; - printf("%s\n", hist_list[i]); - n++; - i++; - } -} -#endif /* CONFIG_CMDLINE_EDITING */ - -#define BEGINNING_OF_LINE() { \ - while (num) { \ - getcmd_putch(CTL_BACKSPACE); \ - num--; \ - } \ -} - -#define ERASE_TO_EOL() { \ - if (num < eol_num) { \ - printf("%*s", (int)(eol_num - num), ""); \ - do { \ - getcmd_putch(CTL_BACKSPACE); \ - } while (--eol_num > num); \ - } \ -} - -#define REFRESH_TO_EOL() { \ - if (num < eol_num) { \ - wlen = eol_num - num; \ - putnstr(buf + num, wlen); \ - num = eol_num; \ - } \ -} - -static void cread_add_char(char ichar, int insert, unsigned long *num, - unsigned long *eol_num, char *buf, unsigned long len) -{ - unsigned long wlen; - - /* room ??? */ - if (insert || *num == *eol_num) { - if (*eol_num > len - 1) { - getcmd_cbeep(); - return; - } - (*eol_num)++; - } - - if (insert) { - wlen = *eol_num - *num; - if (wlen > 1) { - memmove(&buf[*num+1], &buf[*num], wlen-1); - } + s = bootdelay_process(); + if (cli_process_fdt(&s)) + cli_secure_boot_cmd(s); - buf[*num] = ichar; - putnstr(buf + *num, wlen); - (*num)++; - while (--wlen) { - getcmd_putch(CTL_BACKSPACE); - } - } else { - /* echo the character */ - wlen = 1; - buf[*num] = ichar; - putnstr(buf + *num, wlen); - (*num)++; - } -} + autoboot_command(s); -static void cread_add_str(char *str, int strsize, int insert, unsigned long *num, - unsigned long *eol_num, char *buf, unsigned long len) -{ - while (strsize--) { - cread_add_char(*str, insert, num, eol_num, buf, len); - str++; - } + cli_loop(); } - -static int cread_line(const char *const prompt, char *buf, unsigned int *len, - int timeout) -{ - unsigned long num = 0; - unsigned long eol_num = 0; - unsigned long wlen; - char ichar; - int insert = 1; - int esc_len = 0; - char esc_save[8]; - int init_len = strlen(buf); - int first = 1; - - if (init_len) - cread_add_str(buf, init_len, 1, &num, &eol_num, buf, *len); - - while (1) { -#ifdef CONFIG_BOOT_RETRY_TIME - while (!tstc()) { /* while no incoming data */ - if (retry_time >= 0 && get_ticks() > endtime) - return (-2); /* timed out */ - WATCHDOG_RESET(); - } -#endif - if (first && timeout) { - uint64_t etime = endtick(timeout); - - while (!tstc()) { /* while no incoming data */ - if (get_ticks() >= etime) - return -2; /* timed out */ - WATCHDOG_RESET(); - } - first = 0; - } - - ichar = getcmd_getch(); - - if ((ichar == '\n') || (ichar == '\r')) { - putc('\n'); - break; - } - - /* - * handle standard linux xterm esc sequences for arrow key, etc. - */ - if (esc_len != 0) { - if (esc_len == 1) { - if (ichar == '[') { - esc_save[esc_len] = ichar; - esc_len = 2; - } else { - cread_add_str(esc_save, esc_len, insert, - &num, &eol_num, buf, *len); - esc_len = 0; - } - continue; - } - - switch (ichar) { - - case 'D': /* <- key */ - ichar = CTL_CH('b'); - esc_len = 0; - break; - case 'C': /* -> key */ - ichar = CTL_CH('f'); - esc_len = 0; - break; /* pass off to ^F handler */ - case 'H': /* Home key */ - ichar = CTL_CH('a'); - esc_len = 0; - break; /* pass off to ^A handler */ - case 'A': /* up arrow */ - ichar = CTL_CH('p'); - esc_len = 0; - break; /* pass off to ^P handler */ - case 'B': /* down arrow */ - ichar = CTL_CH('n'); - esc_len = 0; - break; /* pass off to ^N handler */ - default: - esc_save[esc_len++] = ichar; - cread_add_str(esc_save, esc_len, insert, - &num, &eol_num, buf, *len); - esc_len = 0; - continue; - } - } - - switch (ichar) { - case 0x1b: - if (esc_len == 0) { - esc_save[esc_len] = ichar; - esc_len = 1; - } else { - puts("impossible condition #876\n"); - esc_len = 0; - } - break; - - case CTL_CH('a'): - BEGINNING_OF_LINE(); - break; - case CTL_CH('c'): /* ^C - break */ - *buf = '\0'; /* discard input */ - return (-1); - case CTL_CH('f'): - if (num < eol_num) { - getcmd_putch(buf[num]); - num++; - } - break; - case CTL_CH('b'): - if (num) { - getcmd_putch(CTL_BACKSPACE); - num--; - } - break; - case CTL_CH('d'): - if (num < eol_num) { - wlen = eol_num - num - 1; - if (wlen) { - memmove(&buf[num], &buf[num+1], wlen); - putnstr(buf + num, wlen); - } - - getcmd_putch(' '); - do { - getcmd_putch(CTL_BACKSPACE); - } while (wlen--); - eol_num--; - } - break; - case CTL_CH('k'): - ERASE_TO_EOL(); - break; - case CTL_CH('e'): - REFRESH_TO_EOL(); - break; - case CTL_CH('o'): - insert = !insert; - break; - case CTL_CH('x'): - case CTL_CH('u'): - BEGINNING_OF_LINE(); - ERASE_TO_EOL(); - break; - case DEL: - case DEL7: - case 8: - if (num) { - wlen = eol_num - num; - num--; - memmove(&buf[num], &buf[num+1], wlen); - getcmd_putch(CTL_BACKSPACE); - putnstr(buf + num, wlen); - getcmd_putch(' '); - do { - getcmd_putch(CTL_BACKSPACE); - } while (wlen--); - eol_num--; - } - break; - case CTL_CH('p'): - case CTL_CH('n'): - { - char * hline; - - esc_len = 0; - - if (ichar == CTL_CH('p')) - hline = hist_prev(); - else - hline = hist_next(); - - if (!hline) { - getcmd_cbeep(); - continue; - } - - /* nuke the current line */ - /* first, go home */ - BEGINNING_OF_LINE(); - - /* erase to end of line */ - ERASE_TO_EOL(); - - /* copy new line into place and display */ - strcpy(buf, hline); - eol_num = strlen(buf); - REFRESH_TO_EOL(); - continue; - } -#ifdef CONFIG_AUTO_COMPLETE - case '\t': { - int num2, col; - - /* do not autocomplete when in the middle */ - if (num < eol_num) { - getcmd_cbeep(); - break; - } - - buf[num] = '\0'; - col = strlen(prompt) + eol_num; - num2 = num; - if (cmd_auto_complete(prompt, buf, &num2, &col)) { - col = num2 - num; - num += col; - eol_num += col; - } - break; - } -#endif - default: - cread_add_char(ichar, insert, &num, &eol_num, buf, *len); - break; - } - } - *len = eol_num; - buf[eol_num] = '\0'; /* lose the newline */ - - if (buf[0] && buf[0] != CREAD_HIST_CHAR) - cread_add_to_hist(buf); - hist_cur = hist_add_idx; - - return 0; -} - -#endif /* CONFIG_CMDLINE_EDITING */ - -/****************************************************************************/ - -/* - * Prompt for input and read a line. - * If CONFIG_BOOT_RETRY_TIME is defined and retry_time >= 0, - * time out when time goes past endtime (timebase time in ticks). - * Return: number of read characters - * -1 if break - * -2 if timed out - */ -int readline (const char *const prompt) -{ - /* - * If console_buffer isn't 0-length the user will be prompted to modify - * it instead of entering it from scratch as desired. - */ - console_buffer[0] = '\0'; - - return readline_into_buffer(prompt, console_buffer, 0); -} - - -int readline_into_buffer(const char *const prompt, char *buffer, int timeout) -{ - char *p = buffer; -#ifdef CONFIG_CMDLINE_EDITING - unsigned int len = CONFIG_SYS_CBSIZE; - int rc; - static int initted = 0; - - /* - * History uses a global array which is not - * writable until after relocation to RAM. - * Revert to non-history version if still - * running from flash. - */ - if (gd->flags & GD_FLG_RELOC) { - if (!initted) { - hist_init(); - initted = 1; - } - - if (prompt) - puts (prompt); - - rc = cread_line(prompt, p, &len, timeout); - return rc < 0 ? rc : len; - - } else { -#endif /* CONFIG_CMDLINE_EDITING */ - char * p_buf = p; - int n = 0; /* buffer index */ - int plen = 0; /* prompt length */ - int col; /* output column cnt */ - char c; - - /* print prompt */ - if (prompt) { - plen = strlen (prompt); - puts (prompt); - } - col = plen; - - for (;;) { -#ifdef CONFIG_BOOT_RETRY_TIME - while (!tstc()) { /* while no incoming data */ - if (retry_time >= 0 && get_ticks() > endtime) - return (-2); /* timed out */ - WATCHDOG_RESET(); - } -#endif - WATCHDOG_RESET(); /* Trigger watchdog, if needed */ - -#ifdef CONFIG_SHOW_ACTIVITY - while (!tstc()) { - show_activity(0); - WATCHDOG_RESET(); - } -#endif - c = getc(); - - /* - * Special character handling - */ - switch (c) { - case '\r': /* Enter */ - case '\n': - *p = '\0'; - puts ("\r\n"); - return p - p_buf; - - case '\0': /* nul */ - continue; - - case 0x03: /* ^C - break */ - p_buf[0] = '\0'; /* discard input */ - return -1; - - case 0x15: /* ^U - erase line */ - while (col > plen) { - puts (erase_seq); - --col; - } - p = p_buf; - n = 0; - continue; - - case 0x17: /* ^W - erase word */ - p=delete_char(p_buf, p, &col, &n, plen); - while ((n > 0) && (*p != ' ')) { - p=delete_char(p_buf, p, &col, &n, plen); - } - continue; - - case 0x08: /* ^H - backspace */ - case 0x7F: /* DEL - backspace */ - p=delete_char(p_buf, p, &col, &n, plen); - continue; - - default: - /* - * Must be a normal character then - */ - if (n < CONFIG_SYS_CBSIZE-2) { - if (c == '\t') { /* expand TABs */ -#ifdef CONFIG_AUTO_COMPLETE - /* if auto completion triggered just continue */ - *p = '\0'; - if (cmd_auto_complete(prompt, console_buffer, &n, &col)) { - p = p_buf + n; /* reset */ - continue; - } -#endif - puts (tab_seq+(col&07)); - col += 8 - (col&07); - } else { - char buf[2]; - - /* - * Echo input using puts() to force an - * LCD flush if we are using an LCD - */ - ++col; - buf[0] = c; - buf[1] = '\0'; - puts(buf); - } - *p++ = c; - ++n; - } else { /* Buffer full */ - putc ('\a'); - } - } - } -#ifdef CONFIG_CMDLINE_EDITING - } -#endif -} - -/****************************************************************************/ - -static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen) -{ - char *s; - - if (*np == 0) { - return (p); - } - - if (*(--p) == '\t') { /* will retype the whole line */ - while (*colp > plen) { - puts (erase_seq); - (*colp)--; - } - for (s=buffer; s<p; ++s) { - if (*s == '\t') { - puts (tab_seq+((*colp) & 07)); - *colp += 8 - ((*colp) & 07); - } else { - ++(*colp); - putc (*s); - } - } - } else { - puts (erase_seq); - (*colp)--; - } - (*np)--; - return (p); -} - -/****************************************************************************/ - -int parse_line (char *line, char *argv[]) -{ - int nargs = 0; - - debug_parser("parse_line: \"%s\"\n", line); - while (nargs < CONFIG_SYS_MAXARGS) { - - /* skip any white space */ - while (isblank(*line)) - ++line; - - if (*line == '\0') { /* end of line, no more args */ - argv[nargs] = NULL; - debug_parser("parse_line: nargs=%d\n", nargs); - return nargs; - } - - argv[nargs++] = line; /* begin of argument string */ - - /* find end of string */ - while (*line && !isblank(*line)) - ++line; - - if (*line == '\0') { /* end of line, no more args */ - argv[nargs] = NULL; - debug_parser("parse_line: nargs=%d\n", nargs); - return nargs; - } - - *line++ = '\0'; /* terminate current arg */ - } - - printf ("** Too many args (max. %d) **\n", CONFIG_SYS_MAXARGS); - - debug_parser("parse_line: nargs=%d\n", nargs); - return (nargs); -} - -/****************************************************************************/ - -#ifndef CONFIG_SYS_HUSH_PARSER -static void process_macros (const char *input, char *output) -{ - char c, prev; - const char *varname_start = NULL; - int inputcnt = strlen (input); - int outputcnt = CONFIG_SYS_CBSIZE; - int state = 0; /* 0 = waiting for '$' */ - - /* 1 = waiting for '(' or '{' */ - /* 2 = waiting for ')' or '}' */ - /* 3 = waiting for ''' */ - char *output_start = output; - - debug_parser("[PROCESS_MACROS] INPUT len %zd: \"%s\"\n", strlen(input), - input); - - prev = '\0'; /* previous character */ - - while (inputcnt && outputcnt) { - c = *input++; - inputcnt--; - - if (state != 3) { - /* remove one level of escape characters */ - if ((c == '\\') && (prev != '\\')) { - if (inputcnt-- == 0) - break; - prev = c; - c = *input++; - } - } - - switch (state) { - case 0: /* Waiting for (unescaped) $ */ - if ((c == '\'') && (prev != '\\')) { - state = 3; - break; - } - if ((c == '$') && (prev != '\\')) { - state++; - } else { - *(output++) = c; - outputcnt--; - } - break; - case 1: /* Waiting for ( */ - if (c == '(' || c == '{') { - state++; - varname_start = input; - } else { - state = 0; - *(output++) = '$'; - outputcnt--; - - if (outputcnt) { - *(output++) = c; - outputcnt--; - } - } - break; - case 2: /* Waiting for ) */ - if (c == ')' || c == '}') { - int i; - char envname[CONFIG_SYS_CBSIZE], *envval; - int envcnt = input - varname_start - 1; /* Varname # of chars */ - - /* Get the varname */ - for (i = 0; i < envcnt; i++) { - envname[i] = varname_start[i]; - } - envname[i] = 0; - - /* Get its value */ - envval = getenv (envname); - - /* Copy into the line if it exists */ - if (envval != NULL) - while ((*envval) && outputcnt) { - *(output++) = *(envval++); - outputcnt--; - } - /* Look for another '$' */ - state = 0; - } - break; - case 3: /* Waiting for ' */ - if ((c == '\'') && (prev != '\\')) { - state = 0; - } else { - *(output++) = c; - outputcnt--; - } - break; - } - prev = c; - } - - if (outputcnt) - *output = 0; - else - *(output - 1) = 0; - - debug_parser("[PROCESS_MACROS] OUTPUT len %zd: \"%s\"\n", - strlen(output_start), output_start); -} - -/**************************************************************************** - * returns: - * 1 - command executed, repeatable - * 0 - command executed but not repeatable, interrupted commands are - * always considered not repeatable - * -1 - not executed (unrecognized, bootd recursion or too many args) - * (If cmd is NULL or "" or longer than CONFIG_SYS_CBSIZE-1 it is - * considered unrecognized) - * - * WARNING: - * - * We must create a temporary copy of the command since the command we get - * may be the result from getenv(), which returns a pointer directly to - * the environment data, which may change magicly when the command we run - * creates or modifies environment variables (like "bootp" does). - */ -static int builtin_run_command(const char *cmd, int flag) -{ - char cmdbuf[CONFIG_SYS_CBSIZE]; /* working copy of cmd */ - char *token; /* start of token in cmdbuf */ - char *sep; /* end of token (separator) in cmdbuf */ - char finaltoken[CONFIG_SYS_CBSIZE]; - char *str = cmdbuf; - char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */ - int argc, inquotes; - int repeatable = 1; - int rc = 0; - - debug_parser("[RUN_COMMAND] cmd[%p]=\"", cmd); - if (DEBUG_PARSER) { - /* use puts - string may be loooong */ - puts(cmd ? cmd : "NULL"); - puts("\"\n"); - } - clear_ctrlc(); /* forget any previous Control C */ - - if (!cmd || !*cmd) { - return -1; /* empty command */ - } - - if (strlen(cmd) >= CONFIG_SYS_CBSIZE) { - puts ("## Command too long!\n"); - return -1; - } - - strcpy (cmdbuf, cmd); - - /* Process separators and check for invalid - * repeatable commands - */ - - debug_parser("[PROCESS_SEPARATORS] %s\n", cmd); - while (*str) { - - /* - * Find separator, or string end - * Allow simple escape of ';' by writing "\;" - */ - for (inquotes = 0, sep = str; *sep; sep++) { - if ((*sep=='\'') && - (*(sep-1) != '\\')) - inquotes=!inquotes; - - if (!inquotes && - (*sep == ';') && /* separator */ - ( sep != str) && /* past string start */ - (*(sep-1) != '\\')) /* and NOT escaped */ - break; - } - - /* - * Limit the token to data between separators - */ - token = str; - if (*sep) { - str = sep + 1; /* start of command for next pass */ - *sep = '\0'; - } - else - str = sep; /* no more commands for next pass */ - debug_parser("token: \"%s\"\n", token); - - /* find macros in this token and replace them */ - process_macros (token, finaltoken); - - /* Extract arguments */ - if ((argc = parse_line (finaltoken, argv)) == 0) { - rc = -1; /* no command at all */ - continue; - } - - if (cmd_process(flag, argc, argv, &repeatable, NULL)) - rc = -1; - - /* Did the user stop this? */ - if (had_ctrlc ()) - return -1; /* if stopped then not repeatable */ - } - - return rc ? rc : repeatable; -} -#endif - -/* - * Run a command using the selected parser. - * - * @param cmd Command to run - * @param flag Execution flags (CMD_FLAG_...) - * @return 0 on success, or != 0 on error. - */ -int run_command(const char *cmd, int flag) -{ -#ifndef CONFIG_SYS_HUSH_PARSER - /* - * builtin_run_command can return 0 or 1 for success, so clean up - * its result. - */ - if (builtin_run_command(cmd, flag) == -1) - return 1; - - return 0; -#else - return parse_string_outer(cmd, - FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP); -#endif -} - -#ifndef CONFIG_SYS_HUSH_PARSER -/** - * Execute a list of command separated by ; or \n using the built-in parser. - * - * This function cannot take a const char * for the command, since if it - * finds newlines in the string, it replaces them with \0. - * - * @param cmd String containing list of commands - * @param flag Execution flags (CMD_FLAG_...) - * @return 0 on success, or != 0 on error. - */ -static int builtin_run_command_list(char *cmd, int flag) -{ - char *line, *next; - int rcode = 0; - - /* - * Break into individual lines, and execute each line; terminate on - * error. - */ - line = next = cmd; - while (*next) { - if (*next == '\n') { - *next = '\0'; - /* run only non-empty commands */ - if (*line) { - debug("** exec: \"%s\"\n", line); - if (builtin_run_command(line, 0) < 0) { - rcode = 1; - break; - } - } - line = next + 1; - } - ++next; - } - if (rcode == 0 && *line) - rcode = (builtin_run_command(line, 0) >= 0); - - return rcode; -} -#endif - -int run_command_list(const char *cmd, int len, int flag) -{ - int need_buff = 1; - char *buff = (char *)cmd; /* cast away const */ - int rcode = 0; - - if (len == -1) { - len = strlen(cmd); -#ifdef CONFIG_SYS_HUSH_PARSER - /* hush will never change our string */ - need_buff = 0; -#else - /* the built-in parser will change our string if it sees \n */ - need_buff = strchr(cmd, '\n') != NULL; -#endif - } - if (need_buff) { - buff = malloc(len + 1); - if (!buff) - return 1; - memcpy(buff, cmd, len); - buff[len] = '\0'; - } -#ifdef CONFIG_SYS_HUSH_PARSER - rcode = parse_string_outer(buff, FLAG_PARSE_SEMICOLON); -#else - /* - * This function will overwrite any \n it sees with a \0, which - * is why it can't work with a const char *. Here we are making - * using of internal knowledge of this function, to avoid always - * doing a malloc() which is actually required only in a case that - * is pretty rare. - */ - rcode = builtin_run_command_list(buff, flag); - if (need_buff) - free(buff); -#endif - - return rcode; -} - -/****************************************************************************/ - -#if defined(CONFIG_CMD_RUN) -int do_run (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - int i; - - if (argc < 2) - return CMD_RET_USAGE; - - for (i=1; i<argc; ++i) { - char *arg; - - if ((arg = getenv (argv[i])) == NULL) { - printf ("## Error: \"%s\" not defined\n", argv[i]); - return 1; - } - - if (run_command_list(arg, -1, flag) != 0) - return 1; - } - return 0; -} -#endif diff --git a/common/menu.c b/common/menu.c index ba393adc3..94afeb290 100644 --- a/common/menu.c +++ b/common/menu.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <cli.h> #include <malloc.h> #include <errno.h> #include <linux/list.h> @@ -196,8 +197,9 @@ static inline int menu_interactive_choice(struct menu *m, void **choice) menu_display(m); if (!m->item_choice) { - readret = readline_into_buffer("Enter choice: ", cbuf, - m->timeout / 10); + readret = cli_readline_into_buffer("Enter choice: ", + cbuf, + m->timeout / 10); if (readret >= 0) { choice_item = menu_item_by_key(m, cbuf); diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 9da021862..062461b2b 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -76,7 +76,7 @@ void spl_nand_load_image(void) #endif /* Load u-boot */ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); + sizeof(*header), (void *)header); spl_parse_image_header(header); nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, spl_image.size, (void *)spl_image.load_addr); diff --git a/disk/part.c b/disk/part.c index b8c6aac80..2827089d8 100644 --- a/disk/part.c +++ b/disk/part.c @@ -22,6 +22,7 @@ struct block_drvr { char *name; block_dev_desc_t* (*get_dev)(int dev); + int (*select_hwpart)(int dev_num, int hwpart); }; static const struct block_drvr block_drvr[] = { @@ -38,7 +39,11 @@ static const struct block_drvr block_drvr[] = { { .name = "usb", .get_dev = usb_stor_get_dev, }, #endif #if defined(CONFIG_MMC) - { .name = "mmc", .get_dev = mmc_get_dev, }, + { + .name = "mmc", + .get_dev = mmc_get_dev, + .select_hwpart = mmc_select_hwpart, + }, #endif #if defined(CONFIG_SYSTEMACE) { .name = "ace", .get_dev = systemace_get_dev, }, @@ -52,11 +57,13 @@ static const struct block_drvr block_drvr[] = { DECLARE_GLOBAL_DATA_PTR; #ifdef HAVE_BLOCK_DEVICE -block_dev_desc_t *get_dev(const char *ifname, int dev) +block_dev_desc_t *get_dev_hwpart(const char *ifname, int dev, int hwpart) { const struct block_drvr *drvr = block_drvr; block_dev_desc_t* (*reloc_get_dev)(int dev); + int (*select_hwpart)(int dev_num, int hwpart); char *name; + int ret; if (!ifname) return NULL; @@ -68,17 +75,41 @@ block_dev_desc_t *get_dev(const char *ifname, int dev) while (drvr->name) { name = drvr->name; reloc_get_dev = drvr->get_dev; + select_hwpart = drvr->select_hwpart; #ifdef CONFIG_NEEDS_MANUAL_RELOC name += gd->reloc_off; reloc_get_dev += gd->reloc_off; -#endif - if (strncmp(ifname, name, strlen(name)) == 0) - return reloc_get_dev(dev); + if (select_hwpart) + select_hwpart += gd->reloc_off; +#endif + if (strncmp(ifname, name, strlen(name)) == 0) { + block_dev_desc_t *dev_desc = reloc_get_dev(dev); + if (!dev_desc) + return NULL; + if (hwpart == -1) + return dev_desc; + if (!select_hwpart) + return NULL; + ret = select_hwpart(dev_desc->dev, hwpart); + if (ret < 0) + return NULL; + return dev_desc; + } drvr++; } return NULL; } + +block_dev_desc_t *get_dev(const char *ifname, int dev) +{ + return get_dev_hwpart(ifname, dev, -1); +} #else +block_dev_desc_t *get_dev_hwpart(const char *ifname, int dev, int hwpart) +{ + return NULL; +} + block_dev_desc_t *get_dev(const char *ifname, int dev) { return NULL; @@ -413,25 +444,52 @@ int get_partition_info(block_dev_desc_t *dev_desc, int part return -1; } -int get_device(const char *ifname, const char *dev_str, +int get_device(const char *ifname, const char *dev_hwpart_str, block_dev_desc_t **dev_desc) { char *ep; - int dev; + char *dup_str = NULL; + const char *dev_str, *hwpart_str; + int dev, hwpart; + + hwpart_str = strchr(dev_hwpart_str, '.'); + if (hwpart_str) { + dup_str = strdup(dev_hwpart_str); + dup_str[hwpart_str - dev_hwpart_str] = 0; + dev_str = dup_str; + hwpart_str++; + } else { + dev_str = dev_hwpart_str; + hwpart = -1; + } dev = simple_strtoul(dev_str, &ep, 16); if (*ep) { printf("** Bad device specification %s %s **\n", ifname, dev_str); - return -1; + dev = -1; + goto cleanup; + } + + if (hwpart_str) { + hwpart = simple_strtoul(hwpart_str, &ep, 16); + if (*ep) { + printf("** Bad HW partition specification %s %s **\n", + ifname, hwpart_str); + dev = -1; + goto cleanup; + } } - *dev_desc = get_dev(ifname, dev); + *dev_desc = get_dev_hwpart(ifname, dev, hwpart); if (!(*dev_desc) || ((*dev_desc)->type == DEV_TYPE_UNKNOWN)) { - printf("** Bad device %s %s **\n", ifname, dev_str); - return -1; + printf("** Bad device %s %s **\n", ifname, dev_hwpart_str); + dev = -1; + goto cleanup; } +cleanup: + free(dup_str); return dev; } diff --git a/doc/README.android-fastboot b/doc/README.android-fastboot new file mode 100644 index 000000000..f1d128caa --- /dev/null +++ b/doc/README.android-fastboot @@ -0,0 +1,91 @@ +Android Fastboot +~~~~~~~~~~~~~~~~ + +Overview +======== +The protocol that is used over USB is described in +README.android-fastboot-protocol in same directory. + +The current implementation does not yet support the flash and erase +commands. + +Client installation +=================== +The counterpart to this gadget is the fastboot client which can +be found in Android's platform/system/core repository in the fastboot +folder. It runs on Windows, Linux and even OSX. Linux user are lucky since +they only need libusb. +Windows users need to bring some time until they have Android SDK (currently +http://dl.google.com/android/installer_r12-windows.exe) installed. You +need to install ADB package which contains the required glue libraries for +accessing USB. Also you need "Google USB driver package" and "SDK platform +tools". Once installed the usb driver is placed in your SDK folder under +extras\google\usb_driver. The android_winusb.inf needs a line like + + %SingleBootLoaderInterface% = USB_Install, USB\VID_0451&PID_D022 + +either in the [Google.NTx86] section for 32bit Windows or [Google.NTamd64] +for 64bit Windows. VID and PID should match whatever the fastboot is +advertising. + +Board specific +============== +The fastboot gadget relies on the USB download gadget, so the following +options must be configured: + +CONFIG_USBDOWNLOAD_GADGET +CONFIG_G_DNL_VENDOR_NUM +CONFIG_G_DNL_PRODUCT_NUM +CONFIG_G_DNL_MANUFACTURER + +The fastboot function is enabled by defining CONFIG_CMD_FASTBOOT and +CONFIG_ANDROID_BOOT_IMAGE. + +The fastboot protocol requires a large memory buffer for downloads. This +buffer should be as large as possible for a platform. The location of the +buffer and size are set with CONFIG_USB_FASTBOOT_BUF_ADDR and +CONFIG_USB_FASTBOOT_BUF_SIZE. + +In Action +========= +Enter into fastboot by executing the fastboot command in u-boot and you +should see: +|GADGET DRIVER: usb_dnl_fastboot + +On the client side you can fetch the bootloader version for instance: +|>fastboot getvar bootloader-version +|bootloader-version: U-Boot 2014.04-00005-gd24cabc +|finished. total time: 0.000s + +or initiate a reboot: +|>fastboot reboot + +and once the client comes back, the board should reset. + +You can also specify a kernel image to boot. You have to either specify +the an image in Android format _or_ pass a binary kernel and let the +fastboot client wrap the Android suite around it. On OMAP for instance you +take zImage kernel and pass it to the fastboot client: + +|>fastboot -b 0x80000000 -c "console=ttyO2 earlyprintk root=/dev/ram0 +| mem=128M" boot zImage +|creating boot image... +|creating boot image - 1847296 bytes +|downloading 'boot.img'... +|OKAY [ 2.766s] +|booting... +|OKAY [ -0.000s] +|finished. total time: 2.766s + +and on the gadget side you should see: +|Starting download of 1847296 bytes +|........................................................ +|downloading of 1847296 bytes finished +|Booting kernel.. +|## Booting Android Image at 0x81000000 ... +|Kernel load addr 0x80008000 size 1801 KiB +|Kernel command line: console=ttyO2 earlyprintk root=/dev/ram0 mem=128M +| Loading Kernel Image ... OK +|OK +| +|Starting kernel ... diff --git a/doc/README.android-fastboot-protocol b/doc/README.android-fastboot-protocol new file mode 100644 index 000000000..e9e7166a2 --- /dev/null +++ b/doc/README.android-fastboot-protocol @@ -0,0 +1,170 @@ +FastBoot Version 0.4 +---------------------- + +The fastboot protocol is a mechanism for communicating with bootloaders +over USB. It is designed to be very straightforward to implement, to +allow it to be used across a wide range of devices and from hosts running +Linux, Windows, or OSX. + + +Basic Requirements +------------------ + +* Two bulk endpoints (in, out) are required +* Max packet size must be 64 bytes for full-speed and 512 bytes for + high-speed USB +* The protocol is entirely host-driven and synchronous (unlike the + multi-channel, bi-directional, asynchronous ADB protocol) + + +Transport and Framing +--------------------- + +1. Host sends a command, which is an ascii string in a single + packet no greater than 64 bytes. + +2. Client response with a single packet no greater than 64 bytes. + The first four bytes of the response are "OKAY", "FAIL", "DATA", + or "INFO". Additional bytes may contain an (ascii) informative + message. + + a. INFO -> the remaining 60 bytes are an informative message + (providing progress or diagnostic messages). They should + be displayed and then step #2 repeats + + b. FAIL -> the requested command failed. The remaining 60 bytes + of the response (if present) provide a textual failure message + to present to the user. Stop. + + c. OKAY -> the requested command completed successfully. Go to #5 + + d. DATA -> the requested command is ready for the data phase. + A DATA response packet will be 12 bytes long, in the form of + DATA00000000 where the 8 digit hexidecimal number represents + the total data size to transfer. + +3. Data phase. Depending on the command, the host or client will + send the indicated amount of data. Short packets are always + acceptable and zero-length packets are ignored. This phase continues + until the client has sent or received the number of bytes indicated + in the "DATA" response above. + +4. Client responds with a single packet no greater than 64 bytes. + The first four bytes of the response are "OKAY", "FAIL", or "INFO". + Similar to #2: + + a. INFO -> display the remaining 60 bytes and return to #4 + + b. FAIL -> display the remaining 60 bytes (if present) as a failure + reason and consider the command failed. Stop. + + c. OKAY -> success. Go to #5 + +5. Success. Stop. + + +Example Session +--------------- + +Host: "getvar:version" request version variable + +Client: "OKAY0.4" return version "0.4" + +Host: "getvar:nonexistant" request some undefined variable + +Client: "OKAY" return value "" + +Host: "download:00001234" request to send 0x1234 bytes of data + +Client: "DATA00001234" ready to accept data + +Host: < 0x1234 bytes > send data + +Client: "OKAY" success + +Host: "flash:bootloader" request to flash the data to the bootloader + +Client: "INFOerasing flash" indicate status / progress + "INFOwriting flash" + "OKAY" indicate success + +Host: "powerdown" send a command + +Client: "FAILunknown command" indicate failure + + +Command Reference +----------------- + +* Command parameters are indicated by printf-style escape sequences. + +* Commands are ascii strings and sent without the quotes (which are + for illustration only here) and without a trailing 0 byte. + +* Commands that begin with a lowercase letter are reserved for this + specification. OEM-specific commands should not begin with a + lowercase letter, to prevent incompatibilities with future specs. + + "getvar:%s" Read a config/version variable from the bootloader. + The variable contents will be returned after the + OKAY response. + + "download:%08x" Write data to memory which will be later used + by "boot", "ramdisk", "flash", etc. The client + will reply with "DATA%08x" if it has enough + space in RAM or "FAIL" if not. The size of + the download is remembered. + + "verify:%08x" Send a digital signature to verify the downloaded + data. Required if the bootloader is "secure" + otherwise "flash" and "boot" will be ignored. + + "flash:%s" Write the previously downloaded image to the + named partition (if possible). + + "erase:%s" Erase the indicated partition (clear to 0xFFs) + + "boot" The previously downloaded data is a boot.img + and should be booted according to the normal + procedure for a boot.img + + "continue" Continue booting as normal (if possible) + + "reboot" Reboot the device. + + "reboot-bootloader" Reboot back into the bootloader. + Useful for upgrade processes that require upgrading + the bootloader and then upgrading other partitions + using the new bootloader. + + "powerdown" Power off the device. + + + +Client Variables +---------------- + +The "getvar:%s" command is used to read client variables which +represent various information about the device and the software +on it. + +The various currently defined names are: + + version Version of FastBoot protocol supported. + It should be "0.3" for this document. + + version-bootloader Version string for the Bootloader. + + version-baseband Version string of the Baseband Software + + product Name of the product + + serialno Product serial number + + secure If the value is "yes", this is a secure + bootloader requiring a signature before + it will install or boot images. + +Names starting with a lowercase character are reserved by this +specification. OEM-specific names should not start with lowercase +characters. diff --git a/doc/README.atmel_pmecc b/doc/README.atmel_pmecc index cf8373b54..cc0f73db8 100644 --- a/doc/README.atmel_pmecc +++ b/doc/README.atmel_pmecc @@ -27,3 +27,24 @@ Take AT91SAM9X5EK as an example, the board definition file likes: #define CONFIG_ATMEL_NAND_HW_PMECC 1 #define CONFIG_PMECC_CAP 2 #define CONFIG_PMECC_SECTOR_SIZE 512 + +How to enable PMECC header for direct programmable boot.bin +----------------------------------------------------------- +2014-05-19 Andreas Bießmann <andreas.devel@googlemail.com> + +The usual way to program SPL into NAND flash is to use the SAM-BA Atmel tool. +This however is often not usable when doing field updates. To be able to +program a SPL binary into NAND flash we need to add the PMECC header to the +binary before. Chapter '12.4.4.1 NAND Flash Boot: NAND Flash Detection' in +sama5d3 SoC spec (as of 03. April 2014) defines how this PMECC header has to +look like. In order to do so we have a new image type added to mkimage to +generate this PMECC header and integrated this into the build process of SPL. + +To enable the generation of atmel PMECC header for SPL one need to define +CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER. The required parameters are taken from +board configuration and compiled into the host tools atmel_pmecc_params. This +tool will be called in build process to parametrize mkimage for atmelimage +type. The mkimage tool has intentionally _not_ compiled in those parameters. + +The mkimage image type atmelimage also set the 6'th interrupt vector to the +correct value. This feature can also be used to setup a boot.bin for MMC boot. diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt index e0b395a61..dcecb9a8c 100644 --- a/doc/driver-model/README.txt +++ b/doc/driver-model/README.txt @@ -122,7 +122,7 @@ What is going on? Let's start at the top. The demo command is in common/cmd_demo.c. It does the usual command procesing and then: - struct device *demo_dev; + struct udevice *demo_dev; ret = uclass_get_device(UCLASS_DEMO, devnum, &demo_dev); @@ -147,7 +147,7 @@ this particular device may use one or other of them. The code for demo_hello() is in drivers/demo/demo-uclass.c: -int demo_hello(struct device *dev, int ch) +int demo_hello(struct udevice *dev, int ch) { const struct demo_ops *ops = device_get_ops(dev); @@ -160,7 +160,7 @@ int demo_hello(struct device *dev, int ch) As you can see it just calls the relevant driver method. One of these is in drivers/demo/demo-simple.c: -static int simple_hello(struct device *dev, int ch) +static int simple_hello(struct udevice *dev, int ch) { const struct dm_demo_pdata *pdata = dev_get_platdata(dev); @@ -321,7 +321,7 @@ instead of struct instance, struct platdata, etc.) this concept relates to a class of drivers (or a subsystem). We shouldn't use 'class' since it is a C++ reserved word, so U-Boot class (uclass) seems better than 'core'. -- Remove 'struct driver_instance' and just use a single 'struct device'. +- Remove 'struct driver_instance' and just use a single 'struct udevice'. This removes a level of indirection that doesn't seem necessary. - Built in device tree support, to avoid the need for platdata - Removed the concept of driver relocation, and just make it possible for diff --git a/doc/git-mailrc b/doc/git-mailrc index 251586e05..e53c88835 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -22,6 +22,7 @@ alias jagan Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> alias jasonjin Jason Jin <jason.jin@freescale.com> alias jhersh Joe Hershberger <joe.hershberger@gmail.com> alias kimphill Kim Phillips <kim.phillips@freescale.com> +alias lukma Lukasz Majewski <l.majewski@samsung.com> alias macpaul Macpaul Lin <macpaul@andestech.com> alias marex Marek Vasut <marex@denx.de> alias monstr Michal Simek <monstr@monstr.eu> @@ -101,6 +102,7 @@ alias x86 uboot, sjg, gruss # Subsystem aliases alias cfi uboot, stroese +alias dfu uboot, lukma alias kerneldoc uboot, marex alias fdt uboot, Jerry Van Baren <vanbaren@cideas.com> alias i2c uboot, hs diff --git a/drivers/core/device.c b/drivers/core/device.c index 55ba281be..c73c339d1 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -30,9 +30,9 @@ * @dev: The device that is to be stripped of its children * @return 0 on success, -ve on error */ -static int device_chld_unbind(struct device *dev) +static int device_chld_unbind(struct udevice *dev) { - struct device *pos, *n; + struct udevice *pos, *n; int ret, saved_ret = 0; assert(dev); @@ -51,9 +51,9 @@ static int device_chld_unbind(struct device *dev) * @dev: The device whose children are to be removed * @return 0 on success, -ve on error */ -static int device_chld_remove(struct device *dev) +static int device_chld_remove(struct udevice *dev) { - struct device *pos, *n; + struct udevice *pos, *n; int ret; assert(dev); @@ -67,10 +67,10 @@ static int device_chld_remove(struct device *dev) return 0; } -int device_bind(struct device *parent, struct driver *drv, const char *name, - void *platdata, int of_offset, struct device **devp) +int device_bind(struct udevice *parent, struct driver *drv, const char *name, + void *platdata, int of_offset, struct udevice **devp) { - struct device *dev; + struct udevice *dev; struct uclass *uc; int ret = 0; @@ -82,7 +82,7 @@ int device_bind(struct device *parent, struct driver *drv, const char *name, if (ret) return ret; - dev = calloc(1, sizeof(struct device)); + dev = calloc(1, sizeof(struct udevice)); if (!dev) return -ENOMEM; @@ -129,8 +129,8 @@ fail_bind: return ret; } -int device_bind_by_name(struct device *parent, const struct driver_info *info, - struct device **devp) +int device_bind_by_name(struct udevice *parent, const struct driver_info *info, + struct udevice **devp) { struct driver *drv; @@ -142,7 +142,7 @@ int device_bind_by_name(struct device *parent, const struct driver_info *info, -1, devp); } -int device_unbind(struct device *dev) +int device_unbind(struct udevice *dev) { struct driver *drv; int ret; @@ -181,7 +181,7 @@ int device_unbind(struct device *dev) * device_free() - Free memory buffers allocated by a device * @dev: Device that is to be started */ -static void device_free(struct device *dev) +static void device_free(struct udevice *dev) { int size; @@ -200,7 +200,7 @@ static void device_free(struct device *dev) } } -int device_probe(struct device *dev) +int device_probe(struct udevice *dev) { struct driver *drv; int size = 0; @@ -279,7 +279,7 @@ fail: return ret; } -int device_remove(struct device *dev) +int device_remove(struct udevice *dev) { struct driver *drv; int ret; @@ -327,7 +327,7 @@ err: return ret; } -void *dev_get_platdata(struct device *dev) +void *dev_get_platdata(struct udevice *dev) { if (!dev) { dm_warn("%s: null device", __func__); @@ -337,7 +337,7 @@ void *dev_get_platdata(struct device *dev) return dev->platdata; } -void *dev_get_priv(struct device *dev) +void *dev_get_priv(struct udevice *dev) { if (!dev) { dm_warn("%s: null device", __func__); diff --git a/drivers/core/lists.c b/drivers/core/lists.c index 4f2c12631..205b140ef 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -60,13 +60,13 @@ struct uclass_driver *lists_uclass_lookup(enum uclass_id id) return NULL; } -int lists_bind_drivers(struct device *parent) +int lists_bind_drivers(struct udevice *parent) { struct driver_info *info = ll_entry_start(struct driver_info, driver_info); const int n_ents = ll_entry_count(struct driver_info, driver_info); struct driver_info *entry; - struct device *dev; + struct udevice *dev; int result = 0; int ret; @@ -116,12 +116,12 @@ static int driver_check_compatible(const void *blob, int offset, return -ENOENT; } -int lists_bind_fdt(struct device *parent, const void *blob, int offset) +int lists_bind_fdt(struct udevice *parent, const void *blob, int offset) { struct driver *driver = ll_entry_start(struct driver, driver); const int n_ents = ll_entry_count(struct driver, driver); struct driver *entry; - struct device *dev; + struct udevice *dev; const char *name; int result = 0; int ret; diff --git a/drivers/core/root.c b/drivers/core/root.c index 407bc0d04..4977875c7 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -24,7 +24,7 @@ static const struct driver_info root_info = { .name = "root_driver", }; -struct device *dm_root(void) +struct udevice *dm_root(void) { if (!gd->dm_root) { dm_warn("Virtual root driver does not exist!\n"); diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index 4df5a8bd3..f6867e4a2 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -101,7 +101,7 @@ fail_mem: int uclass_destroy(struct uclass *uc) { struct uclass_driver *uc_drv; - struct device *dev, *tmp; + struct udevice *dev, *tmp; int ret; list_for_each_entry_safe(dev, tmp, &uc->dev_head, uclass_node) { @@ -137,10 +137,10 @@ int uclass_get(enum uclass_id id, struct uclass **ucp) return 0; } -int uclass_find_device(enum uclass_id id, int index, struct device **devp) +int uclass_find_device(enum uclass_id id, int index, struct udevice **devp) { struct uclass *uc; - struct device *dev; + struct udevice *dev; int ret; *devp = NULL; @@ -158,9 +158,9 @@ int uclass_find_device(enum uclass_id id, int index, struct device **devp) return -ENODEV; } -int uclass_get_device(enum uclass_id id, int index, struct device **devp) +int uclass_get_device(enum uclass_id id, int index, struct udevice **devp) { - struct device *dev; + struct udevice *dev; int ret; *devp = NULL; @@ -177,10 +177,10 @@ int uclass_get_device(enum uclass_id id, int index, struct device **devp) return 0; } -int uclass_first_device(enum uclass_id id, struct device **devp) +int uclass_first_device(enum uclass_id id, struct udevice **devp) { struct uclass *uc; - struct device *dev; + struct udevice *dev; int ret; *devp = NULL; @@ -190,7 +190,7 @@ int uclass_first_device(enum uclass_id id, struct device **devp) if (list_empty(&uc->dev_head)) return 0; - dev = list_first_entry(&uc->dev_head, struct device, uclass_node); + dev = list_first_entry(&uc->dev_head, struct udevice, uclass_node); ret = device_probe(dev); if (ret) return ret; @@ -199,16 +199,17 @@ int uclass_first_device(enum uclass_id id, struct device **devp) return 0; } -int uclass_next_device(struct device **devp) +int uclass_next_device(struct udevice **devp) { - struct device *dev = *devp; + struct udevice *dev = *devp; int ret; *devp = NULL; if (list_is_last(&dev->uclass_node, &dev->uclass->dev_head)) return 0; - dev = list_entry(dev->uclass_node.next, struct device, uclass_node); + dev = list_entry(dev->uclass_node.next, struct udevice, + uclass_node); ret = device_probe(dev); if (ret) return ret; @@ -217,7 +218,7 @@ int uclass_next_device(struct device **devp) return 0; } -int uclass_bind_device(struct device *dev) +int uclass_bind_device(struct udevice *dev) { struct uclass *uc; int ret; @@ -237,7 +238,7 @@ int uclass_bind_device(struct device *dev) return 0; } -int uclass_unbind_device(struct device *dev) +int uclass_unbind_device(struct udevice *dev) { struct uclass *uc; int ret; @@ -253,7 +254,7 @@ int uclass_unbind_device(struct device *dev) return 0; } -int uclass_post_probe_device(struct device *dev) +int uclass_post_probe_device(struct udevice *dev) { struct uclass_driver *uc_drv = dev->uclass->uc_drv; @@ -263,7 +264,7 @@ int uclass_post_probe_device(struct device *dev) return 0; } -int uclass_pre_remove_device(struct device *dev) +int uclass_pre_remove_device(struct udevice *dev) { struct uclass_driver *uc_drv; struct uclass *uc; diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index cfe1e1f55..c9f86302d 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -12,6 +12,7 @@ */ #include <common.h> +#include <cli.h> #include <linux/ctype.h> #include <asm/types.h> #include <asm/io.h> @@ -1864,11 +1865,12 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set) } else { /* * No need to worry for buffer overflow here in - * this function; readline() maxes out at CFG_CBSIZE + * this function; cli_readline() maxes out at + * CFG_CBSIZE */ - readline_into_buffer(prompt, buffer, 0); + cli_readline_into_buffer(prompt, buffer, 0); } - argc = parse_line(buffer, argv); + argc = cli_simple_parse_line(buffer, argv); if (argc == 0) continue; diff --git a/drivers/demo/demo-shape.c b/drivers/demo/demo-shape.c index 2f0eb96bb..a68cc1092 100644 --- a/drivers/demo/demo-shape.c +++ b/drivers/demo/demo-shape.c @@ -23,7 +23,7 @@ struct shape_data { }; /* Crazy little function to draw shapes on the console */ -static int shape_hello(struct device *dev, int ch) +static int shape_hello(struct udevice *dev, int ch) { const struct dm_demo_pdata *pdata = dev_get_platdata(dev); struct shape_data *data = dev_get_priv(dev); @@ -81,7 +81,7 @@ static int shape_hello(struct device *dev, int ch) return 0; } -static int shape_status(struct device *dev, int *status) +static int shape_status(struct udevice *dev, int *status) { struct shape_data *data = dev_get_priv(dev); @@ -94,7 +94,7 @@ static const struct demo_ops shape_ops = { .status = shape_status, }; -static int shape_ofdata_to_platdata(struct device *dev) +static int shape_ofdata_to_platdata(struct udevice *dev) { struct dm_demo_pdata *pdata = dev_get_platdata(dev); int ret; diff --git a/drivers/demo/demo-simple.c b/drivers/demo/demo-simple.c index 6ba813172..11def8603 100644 --- a/drivers/demo/demo-simple.c +++ b/drivers/demo/demo-simple.c @@ -12,7 +12,7 @@ #include <dm-demo.h> #include <asm/io.h> -static int simple_hello(struct device *dev, int ch) +static int simple_hello(struct udevice *dev, int ch) { const struct dm_demo_pdata *pdata = dev_get_platdata(dev); @@ -26,7 +26,7 @@ static const struct demo_ops simple_ops = { .hello = simple_hello, }; -static int demo_shape_ofdata_to_platdata(struct device *dev) +static int demo_shape_ofdata_to_platdata(struct udevice *dev) { /* Parse the data that is common with all demo devices */ return demo_parse_dt(dev); diff --git a/drivers/demo/demo-uclass.c b/drivers/demo/demo-uclass.c index 48588be90..636fd8831 100644 --- a/drivers/demo/demo-uclass.c +++ b/drivers/demo/demo-uclass.c @@ -22,7 +22,7 @@ UCLASS_DRIVER(demo) = { .id = UCLASS_DEMO, }; -int demo_hello(struct device *dev, int ch) +int demo_hello(struct udevice *dev, int ch) { const struct demo_ops *ops = device_get_ops(dev); @@ -32,7 +32,7 @@ int demo_hello(struct device *dev, int ch) return ops->hello(dev, ch); } -int demo_status(struct device *dev, int *status) +int demo_status(struct udevice *dev, int *status) { const struct demo_ops *ops = device_get_ops(dev); @@ -42,7 +42,7 @@ int demo_status(struct device *dev, int *status) return ops->status(dev, status); } -int demo_parse_dt(struct device *dev) +int demo_parse_dt(struct udevice *dev) { struct dm_demo_pdata *pdata = dev_get_platdata(dev); int dn = dev->of_offset; diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 51b10263b..a93810934 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -131,6 +131,10 @@ int dfu_flush(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) { int ret = 0; + ret = dfu_write_buffer_drain(dfu); + if (ret) + return ret; + if (dfu->flush_medium) ret = dfu->flush_medium(dfu); diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index 5e10ea7e6..63cc87661 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -18,11 +18,29 @@ static unsigned char __aligned(CONFIG_SYS_CACHELINE_SIZE) dfu_file_buf[CONFIG_SYS_DFU_MAX_FILE_SIZE]; static long dfu_file_buf_len; +static int mmc_access_part(struct dfu_entity *dfu, struct mmc *mmc, int part) +{ + int ret; + + if (part == mmc->part_num) + return 0; + + ret = mmc_switch_part(dfu->dev_num, part); + if (ret) { + error("Cannot switch to partition %d\n", part); + return ret; + } + mmc->part_num = part; + + return 0; +} + static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, u64 offset, void *buf, long *len) { struct mmc *mmc = find_mmc_device(dfu->dev_num); u32 blk_start, blk_count, n = 0; + int ret, part_num_bkp = 0; /* * We must ensure that we work in lba_blk_size chunks, so ALIGN @@ -39,6 +57,13 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, return -EINVAL; } + if (dfu->data.mmc.hw_partition >= 0) { + part_num_bkp = mmc->part_num; + ret = mmc_access_part(dfu, mmc, dfu->data.mmc.hw_partition); + if (ret) + return ret; + } + debug("%s: %s dev: %d start: %d cnt: %d buf: 0x%p\n", __func__, op == DFU_OP_READ ? "MMC READ" : "MMC WRITE", dfu->dev_num, blk_start, blk_count, buf); @@ -57,9 +82,17 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, if (n != blk_count) { error("MMC operation failed"); + if (dfu->data.mmc.hw_partition >= 0) + mmc_access_part(dfu, mmc, part_num_bkp); return -EIO; } + if (dfu->data.mmc.hw_partition >= 0) { + ret = mmc_access_part(dfu, mmc, part_num_bkp); + if (ret) + return ret; + } + return 0; } @@ -194,6 +227,8 @@ int dfu_read_medium_mmc(struct dfu_entity *dfu, u64 offset, void *buf, * 2nd and 3rd: * lba_start and lba_size, for raw write * mmc_dev and mmc_part, for filesystems and part + * 4th (optional): + * mmcpart <num> (access to HW eMMC partitions) */ int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s) { @@ -233,11 +268,22 @@ int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s) return -ENODEV; } + dfu->data.mmc.hw_partition = -EINVAL; if (!strcmp(entity_type, "raw")) { dfu->layout = DFU_RAW_ADDR; dfu->data.mmc.lba_start = second_arg; dfu->data.mmc.lba_size = third_arg; dfu->data.mmc.lba_blk_size = mmc->read_bl_len; + + /* + * Check for an extra entry at dfu_alt_info env variable + * specifying the mmc HW defined partition number + */ + if (s) + if (!strcmp(strsep(&s, " "), "mmcpart")) + dfu->data.mmc.hw_partition = + simple_strtoul(s, NULL, 0); + } else if (!strcmp(entity_type, "part")) { disk_partition_t partinfo; block_dev_desc_t *blk_dev = &mmc->block_dev; diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c index 2d07097e8..ccdbef6b7 100644 --- a/drivers/dfu/dfu_nand.c +++ b/drivers/dfu/dfu_nand.c @@ -163,6 +163,18 @@ static int dfu_flush_medium_nand(struct dfu_entity *dfu) return ret; } +unsigned int dfu_polltimeout_nand(struct dfu_entity *dfu) +{ + /* + * Currently, Poll Timeout != 0 is only needed on nand + * ubi partition, as the not used sectors need an erase + */ + if (dfu->data.nand.ubi) + return DFU_MANIFEST_POLL_TIMEOUT; + + return DFU_DEFAULT_POLL_TIMEOUT; +} + int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s) { char *st; @@ -211,6 +223,7 @@ int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s) dfu->read_medium = dfu_read_medium_nand; dfu->write_medium = dfu_write_medium_nand; dfu->flush_medium = dfu_flush_medium_nand; + dfu->poll_timeout = dfu_polltimeout_nand; /* initial state */ dfu->inited = 0; diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index b940d9b31..37946d5e1 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -173,16 +173,45 @@ int fpga_add(fpga_type devtype, void *desc) /* * Convert bitstream data and load into the fpga */ -int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size) +int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype) { printf("Bitstream support not implemented for this FPGA device\n"); return FPGA_FAIL; } +#if defined(CONFIG_CMD_FPGA_LOADFS) +int fpga_fsload(int devnum, const void *buf, size_t size, + fpga_fs_info *fpga_fsinfo) +{ + int ret_val = FPGA_FAIL; /* assume failure */ + const fpga_desc *desc = fpga_validate(devnum, buf, size, + (char *)__func__); + + if (desc) { + switch (desc->devtype) { + case fpga_xilinx: +#if defined(CONFIG_FPGA_XILINX) + ret_val = xilinx_loadfs(desc->devdesc, buf, size, + fpga_fsinfo); +#else + fpga_no_sup((char *)__func__, "Xilinx devices"); +#endif + break; + default: + printf("%s: Invalid or unsupported device type %d\n", + __func__, desc->devtype); + } + } + + return ret_val; +} +#endif + /* * Generic multiplexing code */ -int fpga_load(int devnum, const void *buf, size_t bsize) +int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype) { int ret_val = FPGA_FAIL; /* assume failure */ const fpga_desc *desc = fpga_validate(devnum, buf, bsize, @@ -192,7 +221,8 @@ int fpga_load(int devnum, const void *buf, size_t bsize) switch (desc->devtype) { case fpga_xilinx: #if defined(CONFIG_FPGA_XILINX) - ret_val = xilinx_load(desc->devdesc, buf, bsize); + ret_val = xilinx_load(desc->devdesc, buf, bsize, + bstype); #else fpga_no_sup((char *)__func__, "Xilinx devices"); #endif diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 705405614..859fb3c77 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -41,7 +41,8 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { int ret_val = FPGA_FAIL; diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 5c9412c2f..b0213e699 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -45,7 +45,8 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { int ret_val = FPGA_FAIL; diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index e092147ed..0d2d9a469 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -90,7 +90,8 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize); static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); -static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { int ret_val = FPGA_FAIL; diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 8837f5c12..3795c1aff 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -24,7 +24,8 @@ static int xilinx_validate(xilinx_desc *desc, char *fn); /* ------------------------------------------------------------------------- */ -int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) +int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype) { unsigned int length; unsigned int swapsize; @@ -127,19 +128,36 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) dataptr += 4; printf(" bytes in bitstream = %d\n", swapsize); - return fpga_load(devnum, dataptr, swapsize); + return fpga_load(devnum, dataptr, swapsize, bstype); } -int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize) +int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { if (!xilinx_validate (desc, (char *)__FUNCTION__)) { printf ("%s: Invalid device descriptor\n", __FUNCTION__); return FPGA_FAIL; } - return desc->operations->load(desc, buf, bsize); + return desc->operations->load(desc, buf, bsize, bstype); } +#if defined(CONFIG_CMD_FPGA_LOADFS) +int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, + fpga_fs_info *fpga_fsinfo) +{ + if (!xilinx_validate(desc, (char *)__func__)) { + printf("%s: Invalid device descriptor\n", __func__); + return FPGA_FAIL; + } + + if (!desc->operations->loadfs) + return FPGA_FAIL; + + return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo); +} +#endif + int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) { if (!xilinx_validate (desc, (char *)__FUNCTION__)) { diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index c066f21d7..68fe0f3b0 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -9,6 +9,7 @@ #include <common.h> #include <asm/io.h> +#include <fs.h> #include <zynqpl.h> #include <linux/sizes.h> #include <asm/arch/hardware.h> @@ -194,7 +195,7 @@ static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen) return FPGA_SUCCESS; } -static int zynq_dma_xfer_init(u32 partialbit) +static int zynq_dma_xfer_init(bitstream_type bstype) { u32 status, control, isr_status; unsigned long ts; @@ -202,7 +203,7 @@ static int zynq_dma_xfer_init(u32 partialbit) /* Clear loopback bit */ clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); - if (!partialbit) { + if (bstype != BIT_PARTIAL) { zynq_slcr_devcfg_disable(); /* Setting PCFG_PROG_B signal to high */ @@ -322,16 +323,11 @@ static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap) static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf, size_t bsize, u32 blocksize, u32 *swap, - u32 *partialbit) + bitstream_type *bstype) { u32 *buf_start; u32 diff; - /* Detect if we are going working with partial or full bitstream */ - if (bsize != desc->size) { - printf("%s: Working with partial bitstream\n", __func__); - *partialbit = 1; - } buf_start = check_data((u8 *)buf, blocksize, swap); if (!buf_start) @@ -351,17 +347,16 @@ static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf, return FPGA_FAIL; } - if (zynq_dma_xfer_init(*partialbit)) + if (zynq_dma_xfer_init(*bstype)) return FPGA_FAIL; return 0; } - -static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { unsigned long ts; /* Timestamp */ - u32 partialbit = 0; u32 isr_status, swap; /* @@ -369,7 +364,7 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) * in chunks */ if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap, - &partialbit)) + &bstype)) return FPGA_FAIL; buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap); @@ -398,11 +393,92 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) debug("%s: FPGA config done\n", __func__); + if (bstype != BIT_PARTIAL) + zynq_slcr_devcfg_enable(); + + return FPGA_SUCCESS; +} + +#if defined(CONFIG_CMD_FPGA_LOADFS) +static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, + fpga_fs_info *fsinfo) +{ + unsigned long ts; /* Timestamp */ + u32 isr_status, swap; + u32 partialbit = 0; + u32 blocksize; + u32 pos = 0; + int fstype; + char *interface, *dev_part, *filename; + + blocksize = fsinfo->blocksize; + interface = fsinfo->interface; + dev_part = fsinfo->dev_part; + filename = fsinfo->filename; + fstype = fsinfo->fstype; + + if (fs_set_blk_dev(interface, dev_part, fstype)) + return FPGA_FAIL; + + if (fs_read(filename, (u32) buf, pos, blocksize) < 0) + return FPGA_FAIL; + + if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap, + &partialbit)) + return FPGA_FAIL; + + dcache_disable(); + + do { + buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap); + + if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2, + 0xffffffff, 0)) + return FPGA_FAIL; + + bsize -= blocksize; + pos += blocksize; + + if (fs_set_blk_dev(interface, dev_part, fstype)) + return FPGA_FAIL; + + if (bsize > blocksize) { + if (fs_read(filename, (u32) buf, pos, blocksize) < 0) + return FPGA_FAIL; + } else { + if (fs_read(filename, (u32) buf, pos, bsize) < 0) + return FPGA_FAIL; + } + } while (bsize > blocksize); + + buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap); + + if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0)) + return FPGA_FAIL; + + dcache_enable(); + + isr_status = readl(&devcfg_base->int_sts); + + /* Check FPGA configuration completion */ + ts = get_timer(0); + while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + printf("%s: Timeout wait for FPGA to config\n", + __func__); + return FPGA_FAIL; + } + isr_status = readl(&devcfg_base->int_sts); + } + + debug("%s: FPGA config done\n", __func__); + if (!partialbit) zynq_slcr_devcfg_enable(); return FPGA_SUCCESS; } +#endif static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) { @@ -411,6 +487,9 @@ static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) struct xilinx_fpga_op zynq_op = { .load = zynq_load, +#if defined(CONFIG_CMD_FPGA_LOADFS) + .loadfs = zynq_loadfs, +#endif .dump = zynq_dump, .info = zynq_info, }; diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index 0b7007187..6517af162 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -34,6 +34,7 @@ static struct at91_port *at91_pio_get_port(unsigned port) #endif #endif default: + printf("Error: at91_gpio: Fail to get PIO base!\n"); return NULL; } } @@ -200,7 +201,7 @@ int at91_set_pio_output(unsigned port, u32 pin, int value) struct at91_port *at91_port = at91_pio_get_port(port); u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if (at91_port && (port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; writel(mask, &at91_port->idr); writel(mask, &at91_port->pudr); diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 56bfd1146..fa2c2fb7c 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -17,11 +17,11 @@ * or GPIO blocks registered with the GPIO controller. Returns * entry on success, NULL on error. */ -static int gpio_to_device(unsigned int gpio, struct device **devp, +static int gpio_to_device(unsigned int gpio, struct udevice **devp, unsigned int *offset) { struct gpio_dev_priv *uc_priv; - struct device *dev; + struct udevice *dev; int ret; for (ret = uclass_first_device(UCLASS_GPIO, &dev); @@ -40,11 +40,11 @@ static int gpio_to_device(unsigned int gpio, struct device **devp, return ret ? ret : -EINVAL; } -int gpio_lookup_name(const char *name, struct device **devp, +int gpio_lookup_name(const char *name, struct udevice **devp, unsigned int *offsetp, unsigned int *gpiop) { struct gpio_dev_priv *uc_priv; - struct device *dev; + struct udevice *dev; int ret; if (devp) @@ -86,7 +86,7 @@ int gpio_lookup_name(const char *name, struct device **devp, int gpio_request(unsigned gpio, const char *label) { unsigned int offset; - struct device *dev; + struct udevice *dev; int ret; ret = gpio_to_device(gpio, &dev, &offset); @@ -110,7 +110,7 @@ int gpio_request(unsigned gpio, const char *label) int gpio_free(unsigned gpio) { unsigned int offset; - struct device *dev; + struct udevice *dev; int ret; ret = gpio_to_device(gpio, &dev, &offset); @@ -133,7 +133,7 @@ int gpio_free(unsigned gpio) int gpio_direction_input(unsigned gpio) { unsigned int offset; - struct device *dev; + struct udevice *dev; int ret; ret = gpio_to_device(gpio, &dev, &offset); @@ -155,7 +155,7 @@ int gpio_direction_input(unsigned gpio) int gpio_direction_output(unsigned gpio, int value) { unsigned int offset; - struct device *dev; + struct udevice *dev; int ret; ret = gpio_to_device(gpio, &dev, &offset); @@ -177,7 +177,7 @@ int gpio_direction_output(unsigned gpio, int value) int gpio_get_value(unsigned gpio) { unsigned int offset; - struct device *dev; + struct udevice *dev; int ret; ret = gpio_to_device(gpio, &dev, &offset); @@ -199,7 +199,7 @@ int gpio_get_value(unsigned gpio) int gpio_set_value(unsigned gpio, int value) { unsigned int offset; - struct device *dev; + struct udevice *dev; int ret; ret = gpio_to_device(gpio, &dev, &offset); @@ -209,7 +209,7 @@ int gpio_set_value(unsigned gpio, int value) return gpio_get_ops(dev)->set_value(dev, offset, value); } -const char *gpio_get_bank_info(struct device *dev, int *bit_count) +const char *gpio_get_bank_info(struct udevice *dev, int *bit_count) { struct gpio_dev_priv *priv; @@ -225,7 +225,7 @@ const char *gpio_get_bank_info(struct device *dev, int *bit_count) static int gpio_renumber(void) { struct gpio_dev_priv *uc_priv; - struct device *dev; + struct udevice *dev; struct uclass *uc; unsigned base; int ret; @@ -247,12 +247,12 @@ static int gpio_renumber(void) return 0; } -static int gpio_post_probe(struct device *dev) +static int gpio_post_probe(struct udevice *dev) { return gpio_renumber(); } -static int gpio_pre_remove(struct device *dev) +static int gpio_pre_remove(struct udevice *dev) { return gpio_renumber(); } diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index 11a0472c6..db7b67373 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -8,11 +8,9 @@ #include <common.h> #include <asm/io.h> #include <asm/gpio.h> +#include <asm/arch/gpio.h> -#define S5P_GPIO_GET_BANK(x) ((x >> S5P_GPIO_BANK_SHIFT) \ - & S5P_GPIO_BANK_MASK) - -#define S5P_GPIO_GET_PIN(x) (x & S5P_GPIO_PIN_MASK) +#define S5P_GPIO_GET_PIN(x) (x % GPIO_PER_BANK) #define CON_MASK(x) (0xf << ((x) << 2)) #define CON_SFR(x, v) ((v) << ((x) << 2)) @@ -28,7 +26,103 @@ #define RATE_MASK(x) (0x1 << (x + 16)) #define RATE_SET(x) (0x1 << (x + 16)) -void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg) +#define name_to_gpio(n) s5p_name_to_gpio(n) +static inline int s5p_name_to_gpio(const char *name) +{ + unsigned num, irregular_set_number, irregular_bank_base; + const struct gpio_name_num_table *tabp; + char this_bank, bank_name, irregular_bank_name; + char *endp; + + /* + * The gpio name starts with either 'g' or 'gp' followed by the bank + * name character. Skip one or two characters depending on the prefix. + */ + if (name[0] == 'g' && name[1] == 'p') + name += 2; + else if (name[0] == 'g') + name++; + else + return -1; /* Name must start with 'g' */ + + bank_name = *name++; + if (!*name) + return -1; /* At least one digit is required/expected. */ + + /* + * On both exynos5 and exynos5420 architectures there is a bank of + * GPIOs which does not fall into the regular address pattern. Those + * banks are c4 on Exynos5 and y7 on Exynos5420. The rest of the below + * assignments help to handle these irregularities. + */ +#if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) { + tabp = exynos5420_gpio_table; + irregular_bank_name = 'y'; + irregular_set_number = '7'; + irregular_bank_base = EXYNOS5420_GPIO_Y70; + } else { + tabp = exynos5_gpio_table; + irregular_bank_name = 'c'; + irregular_set_number = '4'; + irregular_bank_base = EXYNOS5_GPIO_C40; + } + } else { + if (proid_is_exynos4412()) + tabp = exynos4x12_gpio_table; + else + tabp = exynos4_gpio_table; + irregular_bank_name = 0; + irregular_set_number = 0; + irregular_bank_base = 0; + } +#else + if (cpu_is_s5pc110()) + tabp = s5pc110_gpio_table; + else + tabp = s5pc100_gpio_table; + irregular_bank_name = 0; + irregular_set_number = 0; + irregular_bank_base = 0; +#endif + + this_bank = tabp->bank; + do { + if (bank_name == this_bank) { + unsigned pin_index; /* pin number within the bank */ + if ((bank_name == irregular_bank_name) && + (name[0] == irregular_set_number)) { + pin_index = name[1] - '0'; + /* Irregular sets have 8 pins. */ + if (pin_index >= GPIO_PER_BANK) + return -1; + num = irregular_bank_base + pin_index; + } else { + pin_index = simple_strtoul(name, &endp, 8); + pin_index -= tabp->bank_offset; + /* + * Sanity check: bunk 'z' has no set number, + * for all other banks there must be exactly + * two octal digits, and the resulting number + * should not exceed the number of pins in the + * bank. + */ + if (((bank_name != 'z') && !name[1]) || + *endp || + (pin_index >= tabp->bank_size)) + return -1; + num = tabp->base + pin_index; + } + return num; + } + this_bank = (++tabp)->bank; + } while (this_bank); + + return -1; +} + +static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg) { unsigned int value; @@ -38,18 +132,7 @@ void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg) writel(value, &bank->con); } -void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en) -{ - s5p_gpio_cfg_pin(bank, gpio, GPIO_OUTPUT); - s5p_gpio_set_value(bank, gpio, en); -} - -void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio) -{ - s5p_gpio_cfg_pin(bank, gpio, GPIO_INPUT); -} - -void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en) +static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en) { unsigned int value; @@ -60,7 +143,19 @@ void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en) writel(value, &bank->dat); } -unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio) +static void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, + int gpio, int en) +{ + s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_OUTPUT); + s5p_gpio_set_value(bank, gpio, en); +} + +static void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio) +{ + s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_INPUT); +} + +static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio) { unsigned int value; @@ -68,7 +163,7 @@ unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio) return !!(value & DAT_MASK(gpio)); } -void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) +static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) { unsigned int value; @@ -76,8 +171,8 @@ void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) value &= ~PULL_MASK(gpio); switch (mode) { - case GPIO_PULL_DOWN: - case GPIO_PULL_UP: + case S5P_GPIO_PULL_DOWN: + case S5P_GPIO_PULL_UP: value |= PULL_MODE(gpio, mode); break; default: @@ -87,7 +182,7 @@ void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) writel(value, &bank->pull); } -void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) +static void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) { unsigned int value; @@ -95,10 +190,10 @@ void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) value &= ~DRV_MASK(gpio); switch (mode) { - case GPIO_DRV_1X: - case GPIO_DRV_2X: - case GPIO_DRV_3X: - case GPIO_DRV_4X: + case S5P_GPIO_DRV_1X: + case S5P_GPIO_DRV_2X: + case S5P_GPIO_DRV_3X: + case S5P_GPIO_DRV_4X: value |= DRV_SET(gpio, mode); break; default: @@ -108,7 +203,7 @@ void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) writel(value, &bank->drv); } -void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) +static void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) { unsigned int value; @@ -116,8 +211,8 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) value &= ~RATE_MASK(gpio); switch (mode) { - case GPIO_DRV_FAST: - case GPIO_DRV_SLOW: + case S5P_GPIO_DRV_FAST: + case S5P_GPIO_DRV_SLOW: value |= RATE_SET(gpio); break; default: @@ -127,12 +222,31 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) writel(value, &bank->drv); } -struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio) +struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio) { - unsigned bank = S5P_GPIO_GET_BANK(gpio); - unsigned base = s5p_gpio_base(gpio); + const struct gpio_info *data; + unsigned int upto; + int i, count; + + data = get_gpio_data(); + count = get_bank_num(); + upto = 0; + + for (i = 0; i < count; i++) { + debug("i=%d, upto=%d\n", i, upto); + if (gpio < data->max_gpio) { + struct s5p_gpio_bank *bank; + bank = (struct s5p_gpio_bank *)data->reg_addr; + bank += (gpio - upto) / GPIO_PER_BANK; + debug("gpio=%d, bank=%p\n", gpio, bank); + return bank; + } + + upto = data->max_gpio; + data++; + } - return (struct s5p_gpio_bank *)(base + bank); + return NULL; } int s5p_gpio_get_pin(unsigned gpio) @@ -179,3 +293,27 @@ int gpio_set_value(unsigned gpio, int value) return 0; } + +void gpio_set_pull(int gpio, int mode) +{ + s5p_gpio_set_pull(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), mode); +} + +void gpio_set_drv(int gpio, int mode) +{ + s5p_gpio_set_drv(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), mode); +} + +void gpio_cfg_pin(int gpio, int cfg) +{ + s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), cfg); +} + +void gpio_set_rate(int gpio, int mode) +{ + s5p_gpio_set_rate(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), mode); +} diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c index 22b6a5f79..09cebe228 100644 --- a/drivers/gpio/sandbox.c +++ b/drivers/gpio/sandbox.c @@ -22,7 +22,7 @@ struct gpio_state { }; /* Access routines for GPIO state */ -static u8 *get_gpio_flags(struct device *dev, unsigned offset) +static u8 *get_gpio_flags(struct udevice *dev, unsigned offset) { struct gpio_dev_priv *uc_priv = dev->uclass_priv; struct gpio_state *state = dev_get_priv(dev); @@ -36,12 +36,12 @@ static u8 *get_gpio_flags(struct device *dev, unsigned offset) return &state[offset].flags; } -static int get_gpio_flag(struct device *dev, unsigned offset, int flag) +static int get_gpio_flag(struct udevice *dev, unsigned offset, int flag) { return (*get_gpio_flags(dev, offset) & flag) != 0; } -static int set_gpio_flag(struct device *dev, unsigned offset, int flag, +static int set_gpio_flag(struct udevice *dev, unsigned offset, int flag, int value) { u8 *gpio = get_gpio_flags(dev, offset); @@ -54,7 +54,7 @@ static int set_gpio_flag(struct device *dev, unsigned offset, int flag, return 0; } -static int check_reserved(struct device *dev, unsigned offset, +static int check_reserved(struct udevice *dev, unsigned offset, const char *func) { if (!get_gpio_flag(dev, offset, GPIOF_RESERVED)) { @@ -70,24 +70,24 @@ static int check_reserved(struct device *dev, unsigned offset, * Back-channel sandbox-internal-only access to GPIO state */ -int sandbox_gpio_get_value(struct device *dev, unsigned offset) +int sandbox_gpio_get_value(struct udevice *dev, unsigned offset) { if (get_gpio_flag(dev, offset, GPIOF_OUTPUT)) debug("sandbox_gpio: get_value on output gpio %u\n", offset); return get_gpio_flag(dev, offset, GPIOF_HIGH); } -int sandbox_gpio_set_value(struct device *dev, unsigned offset, int value) +int sandbox_gpio_set_value(struct udevice *dev, unsigned offset, int value) { return set_gpio_flag(dev, offset, GPIOF_HIGH, value); } -int sandbox_gpio_get_direction(struct device *dev, unsigned offset) +int sandbox_gpio_get_direction(struct udevice *dev, unsigned offset) { return get_gpio_flag(dev, offset, GPIOF_OUTPUT); } -int sandbox_gpio_set_direction(struct device *dev, unsigned offset, int output) +int sandbox_gpio_set_direction(struct udevice *dev, unsigned offset, int output) { return set_gpio_flag(dev, offset, GPIOF_OUTPUT, output); } @@ -97,7 +97,7 @@ int sandbox_gpio_set_direction(struct device *dev, unsigned offset, int output) */ /* set GPIO port 'offset' as an input */ -static int sb_gpio_direction_input(struct device *dev, unsigned offset) +static int sb_gpio_direction_input(struct udevice *dev, unsigned offset) { debug("%s: offset:%u\n", __func__, offset); @@ -108,7 +108,7 @@ static int sb_gpio_direction_input(struct device *dev, unsigned offset) } /* set GPIO port 'offset' as an output, with polarity 'value' */ -static int sb_gpio_direction_output(struct device *dev, unsigned offset, +static int sb_gpio_direction_output(struct udevice *dev, unsigned offset, int value) { debug("%s: offset:%u, value = %d\n", __func__, offset, value); @@ -121,7 +121,7 @@ static int sb_gpio_direction_output(struct device *dev, unsigned offset, } /* read GPIO IN value of port 'offset' */ -static int sb_gpio_get_value(struct device *dev, unsigned offset) +static int sb_gpio_get_value(struct udevice *dev, unsigned offset) { debug("%s: offset:%u\n", __func__, offset); @@ -132,7 +132,7 @@ static int sb_gpio_get_value(struct device *dev, unsigned offset) } /* write GPIO OUT value to port 'offset' */ -static int sb_gpio_set_value(struct device *dev, unsigned offset, int value) +static int sb_gpio_set_value(struct udevice *dev, unsigned offset, int value) { debug("%s: offset:%u, value = %d\n", __func__, offset, value); @@ -148,7 +148,7 @@ static int sb_gpio_set_value(struct device *dev, unsigned offset, int value) return sandbox_gpio_set_value(dev, offset, value); } -static int sb_gpio_request(struct device *dev, unsigned offset, +static int sb_gpio_request(struct udevice *dev, unsigned offset, const char *label) { struct gpio_dev_priv *uc_priv = dev->uclass_priv; @@ -171,7 +171,7 @@ static int sb_gpio_request(struct device *dev, unsigned offset, return set_gpio_flag(dev, offset, GPIOF_RESERVED, 1); } -static int sb_gpio_free(struct device *dev, unsigned offset) +static int sb_gpio_free(struct udevice *dev, unsigned offset) { struct gpio_state *state = dev_get_priv(dev); @@ -184,7 +184,7 @@ static int sb_gpio_free(struct device *dev, unsigned offset) return set_gpio_flag(dev, offset, GPIOF_RESERVED, 0); } -static int sb_gpio_get_state(struct device *dev, unsigned int offset, +static int sb_gpio_get_state(struct udevice *dev, unsigned int offset, char *buf, int bufsize) { struct gpio_dev_priv *uc_priv = dev->uclass_priv; @@ -213,7 +213,7 @@ static const struct dm_gpio_ops gpio_sandbox_ops = { .get_state = sb_gpio_get_state, }; -static int sandbox_gpio_ofdata_to_platdata(struct device *dev) +static int sandbox_gpio_ofdata_to_platdata(struct udevice *dev) { struct gpio_dev_priv *uc_priv = dev->uclass_priv; @@ -225,7 +225,7 @@ static int sandbox_gpio_ofdata_to_platdata(struct device *dev) return 0; } -static int gpio_sandbox_probe(struct device *dev) +static int gpio_sandbox_probe(struct udevice *dev) { struct gpio_dev_priv *uc_priv = dev->uclass_priv; diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 82b30d5ab..fea9d17f8 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -221,6 +221,26 @@ int gpio_set_value(unsigned gpio, int value) return 0; } +void gpio_config_table(const struct tegra_gpio_config *config, int len) +{ + int i; + + for (i = 0; i < len; i++) { + switch (config[i].init) { + case TEGRA_GPIO_INIT_IN: + gpio_direction_input(config[i].gpio); + break; + case TEGRA_GPIO_INIT_OUT0: + gpio_direction_output(config[i].gpio, 0); + break; + case TEGRA_GPIO_INIT_OUT1: + gpio_direction_output(config[i].gpio, 1); + break; + } + set_config(config[i].gpio, 1); + } +} + /* * Display Tegra GPIO information */ diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 931922bc4..34febf52f 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -28,8 +28,10 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o obj-$(CONFIG_DWMMC) += dw_mmc.o obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o +obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o +obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o else diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 50cba64d9..55416136a 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -174,7 +174,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) int timeout; struct fsl_esdhc_cfg *cfg = mmc->priv; struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; -#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO + uint wml_value; wml_value = data->blocksize/4; @@ -184,12 +184,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) wml_value = WML_RD_WML_MAX_VAL; esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); +#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO esdhc_write32(®s->dsaddr, (u32)data->dest); +#endif } else { +#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO flush_dcache_range((ulong)data->src, (ulong)data->src+data->blocks *data->blocksize); - +#endif if (wml_value > WML_WR_WML_MAX) wml_value = WML_WR_WML_MAX_VAL; if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { @@ -199,19 +202,10 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, wml_value << 16); +#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO esdhc_write32(®s->dsaddr, (u32)data->src); +#endif } -#else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ - if (!(data->flags & MMC_DATA_READ)) { - if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { - printf("\nThe SD card is locked. " - "Can not write to a locked card.\n\n"); - return TIMEOUT; - } - esdhc_write32(®s->dsaddr, (u32)data->src); - } else - esdhc_write32(®s->dsaddr, (u32)data->dest); -#endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); @@ -252,6 +246,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) return 0; } +#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO static void check_and_invalidate_dcache_range (struct mmc_cmd *cmd, struct mmc_data *data) { @@ -261,6 +256,8 @@ static void check_and_invalidate_dcache_range unsigned end = start+size ; invalidate_dcache_range(start, end); } +#endif + /* * Sends a command out on the bus. Takes the mmc pointer, * a command pointer, and an optional data pointer. @@ -388,9 +385,10 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) goto out; } } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); -#endif + if (data->flags & MMC_DATA_READ) check_and_invalidate_dcache_range(cmd, data); +#endif } out: diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index acca0269e..a57a9b1fa 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -243,9 +243,10 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) #ifdef DEBUG if (data->flags & MMC_DATA_READ) { + u32 cnt = word_count * 4; printf("Read Data:\n"); - print_buffer(0, data->dest, 1, - word_count*4, 0); + print_buffer(0, data->dest + cnt * block_count, + 1, cnt, 0); } #endif #ifdef DEBUG diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 0d7d7522e..25db32fcf 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -150,6 +150,8 @@ int mmc_send_status(struct mmc *mmc, int timeout) #endif return TIMEOUT; } + if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR) + return SWITCH_ERR; return 0; } @@ -501,7 +503,7 @@ static int mmc_change_freq(struct mmc *mmc) err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); if (err) - return err; + return err == SWITCH_ERR ? 0 : err; /* Now check to see that it worked */ err = mmc_send_ext_csd(mmc, ext_csd); @@ -550,6 +552,32 @@ static int mmc_set_capacity(struct mmc *mmc, int part_num) return 0; } +int mmc_select_hwpart(int dev_num, int hwpart) +{ + struct mmc *mmc = find_mmc_device(dev_num); + int ret; + + if (!mmc) + return -1; + + if (mmc->part_num == hwpart) + return 0; + + if (mmc->part_config == MMCPART_NOAVAILABLE) { + printf("Card doesn't support part_switch\n"); + return -1; + } + + ret = mmc_switch_part(dev_num, hwpart); + if (ret) + return -1; + + mmc->part_num = hwpart; + + return 0; +} + + int mmc_switch_part(int dev_num, unsigned int part_num) { struct mmc *mmc = find_mmc_device(dev_num); @@ -1313,10 +1341,13 @@ static int mmc_complete_init(struct mmc *mmc) int mmc_init(struct mmc *mmc) { int err = IN_PROGRESS; - unsigned start = get_timer(0); + unsigned start; if (mmc->has_init) return 0; + + start = get_timer(0); + if (!mmc->init_in_progress) err = mmc_start_init(mmc); diff --git a/drivers/mmc/rpmb.c b/drivers/mmc/rpmb.c new file mode 100644 index 000000000..05936f5d1 --- /dev/null +++ b/drivers/mmc/rpmb.c @@ -0,0 +1,323 @@ +/* + * Copyright 2014, Staubli Faverges + * Pierre Aubert + * + * eMMC- Replay Protected Memory Block + * According to JEDEC Standard No. 84-A441 + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <mmc.h> +#include <sha256.h> +#include "mmc_private.h" + +/* Request codes */ +#define RPMB_REQ_KEY 1 +#define RPMB_REQ_WCOUNTER 2 +#define RPMB_REQ_WRITE_DATA 3 +#define RPMB_REQ_READ_DATA 4 +#define RPMB_REQ_STATUS 5 + +/* Response code */ +#define RPMB_RESP_KEY 0x0100 +#define RPMB_RESP_WCOUNTER 0x0200 +#define RPMB_RESP_WRITE_DATA 0x0300 +#define RPMB_RESP_READ_DATA 0x0400 + +/* Error codes */ +#define RPMB_OK 0 +#define RPMB_ERR_GENERAL 1 +#define RPMB_ERR_AUTH 2 +#define RPMB_ERR_COUNTER 3 +#define RPMB_ERR_ADDRESS 4 +#define RPMB_ERR_WRITE 5 +#define RPMB_ERR_READ 6 +#define RPMB_ERR_KEY 7 +#define RPMB_ERR_CNT_EXPIRED 0x80 +#define RPMB_ERR_MSK 0x7 + +/* Sizes of RPMB data frame */ +#define RPMB_SZ_STUFF 196 +#define RPMB_SZ_MAC 32 +#define RPMB_SZ_DATA 256 +#define RPMB_SZ_NONCE 16 + +#define SHA256_BLOCK_SIZE 64 + +/* Error messages */ +static const char * const rpmb_err_msg[] = { + "", + "General failure", + "Authentication failure", + "Counter failure", + "Address failure", + "Write failure", + "Read failure", + "Authentication key not yet programmed", +}; + + +/* Structure of RPMB data frame. */ +struct s_rpmb { + unsigned char stuff[RPMB_SZ_STUFF]; + unsigned char mac[RPMB_SZ_MAC]; + unsigned char data[RPMB_SZ_DATA]; + unsigned char nonce[RPMB_SZ_NONCE]; + unsigned long write_counter; + unsigned short address; + unsigned short block_count; + unsigned short result; + unsigned short request; +}; + +static int mmc_set_blockcount(struct mmc *mmc, unsigned int blockcount, + bool is_rel_write) +{ + struct mmc_cmd cmd = {0}; + + cmd.cmdidx = MMC_CMD_SET_BLOCK_COUNT; + cmd.cmdarg = blockcount & 0x0000FFFF; + if (is_rel_write) + cmd.cmdarg |= 1 << 31; + cmd.resp_type = MMC_RSP_R1; + + return mmc_send_cmd(mmc, &cmd, NULL); +} +static int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s, + unsigned int count, bool is_rel_write) +{ + struct mmc_cmd cmd = {0}; + struct mmc_data data; + int ret; + + ret = mmc_set_blockcount(mmc, count, is_rel_write); + if (ret) { +#ifdef CONFIG_MMC_RPMB_TRACE + printf("%s:mmc_set_blockcount-> %d\n", __func__, ret); +#endif + return 1; + } + + cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_R1b; + + data.src = (const char *)s; + data.blocks = 1; + data.blocksize = MMC_MAX_BLOCK_LEN; + data.flags = MMC_DATA_WRITE; + + ret = mmc_send_cmd(mmc, &cmd, &data); + if (ret) { +#ifdef CONFIG_MMC_RPMB_TRACE + printf("%s:mmc_send_cmd-> %d\n", __func__, ret); +#endif + return 1; + } + return 0; +} +static int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s, + unsigned short expected) +{ + struct mmc_cmd cmd = {0}; + struct mmc_data data; + int ret; + + ret = mmc_set_blockcount(mmc, 1, false); + if (ret) { +#ifdef CONFIG_MMC_RPMB_TRACE + printf("%s:mmc_set_blockcount-> %d\n", __func__, ret); +#endif + return -1; + } + cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; + cmd.cmdarg = 0; + cmd.resp_type = MMC_RSP_R1; + + data.dest = (char *)s; + data.blocks = 1; + data.blocksize = MMC_MAX_BLOCK_LEN; + data.flags = MMC_DATA_READ; + + ret = mmc_send_cmd(mmc, &cmd, &data); + if (ret) { +#ifdef CONFIG_MMC_RPMB_TRACE + printf("%s:mmc_send_cmd-> %d\n", __func__, ret); +#endif + return -1; + } + /* Check the response and the status */ + if (be16_to_cpu(s->request) != expected) { +#ifdef CONFIG_MMC_RPMB_TRACE + printf("%s:response= %x\n", __func__, + be16_to_cpu(s->request)); +#endif + return -1; + } + ret = be16_to_cpu(s->result); + if (ret) { + printf("%s %s\n", rpmb_err_msg[ret & RPMB_ERR_MSK], + (ret & RPMB_ERR_CNT_EXPIRED) ? + "Write counter has expired" : ""); + } + + /* Return the status of the command */ + return ret; +} +static int mmc_rpmb_status(struct mmc *mmc, unsigned short expected) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1); + + memset(rpmb_frame, 0, sizeof(struct s_rpmb)); + rpmb_frame->request = cpu_to_be16(RPMB_REQ_STATUS); + if (mmc_rpmb_request(mmc, rpmb_frame, 1, false)) + return -1; + + /* Read the result */ + return mmc_rpmb_response(mmc, rpmb_frame, expected); +} +static void rpmb_hmac(unsigned char *key, unsigned char *buff, int len, + unsigned char *output) +{ + sha256_context ctx; + int i; + unsigned char k_ipad[SHA256_BLOCK_SIZE]; + unsigned char k_opad[SHA256_BLOCK_SIZE]; + + sha256_starts(&ctx); + + /* According to RFC 4634, the HMAC transform looks like: + SHA(K XOR opad, SHA(K XOR ipad, text)) + + where K is an n byte key. + ipad is the byte 0x36 repeated blocksize times + opad is the byte 0x5c repeated blocksize times + and text is the data being protected. + */ + + for (i = 0; i < RPMB_SZ_MAC; i++) { + k_ipad[i] = key[i] ^ 0x36; + k_opad[i] = key[i] ^ 0x5c; + } + /* remaining pad bytes are '\0' XOR'd with ipad and opad values */ + for ( ; i < SHA256_BLOCK_SIZE; i++) { + k_ipad[i] = 0x36; + k_opad[i] = 0x5c; + } + sha256_update(&ctx, k_ipad, SHA256_BLOCK_SIZE); + sha256_update(&ctx, buff, len); + sha256_finish(&ctx, output); + + /* Init context for second pass */ + sha256_starts(&ctx); + + /* start with outer pad */ + sha256_update(&ctx, k_opad, SHA256_BLOCK_SIZE); + + /* then results of 1st hash */ + sha256_update(&ctx, output, RPMB_SZ_MAC); + + /* finish up 2nd pass */ + sha256_finish(&ctx, output); +} +int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *pcounter) +{ + int ret; + ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1); + + /* Fill the request */ + memset(rpmb_frame, 0, sizeof(struct s_rpmb)); + rpmb_frame->request = cpu_to_be16(RPMB_REQ_WCOUNTER); + if (mmc_rpmb_request(mmc, rpmb_frame, 1, false)) + return -1; + + /* Read the result */ + ret = mmc_rpmb_response(mmc, rpmb_frame, RPMB_RESP_WCOUNTER); + if (ret) + return ret; + + *pcounter = be32_to_cpu(rpmb_frame->write_counter); + return 0; +} +int mmc_rpmb_set_key(struct mmc *mmc, void *key) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1); + /* Fill the request */ + memset(rpmb_frame, 0, sizeof(struct s_rpmb)); + rpmb_frame->request = cpu_to_be16(RPMB_REQ_KEY); + memcpy(rpmb_frame->mac, key, RPMB_SZ_MAC); + + if (mmc_rpmb_request(mmc, rpmb_frame, 1, true)) + return -1; + + /* read the operation status */ + return mmc_rpmb_status(mmc, RPMB_RESP_KEY); +} +int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, + unsigned short cnt, unsigned char *key) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1); + int i; + + for (i = 0; i < cnt; i++) { + /* Fill the request */ + memset(rpmb_frame, 0, sizeof(struct s_rpmb)); + rpmb_frame->address = cpu_to_be16(blk + i); + rpmb_frame->request = cpu_to_be16(RPMB_REQ_READ_DATA); + if (mmc_rpmb_request(mmc, rpmb_frame, 1, false)) + break; + + /* Read the result */ + if (mmc_rpmb_response(mmc, rpmb_frame, RPMB_RESP_READ_DATA)) + break; + + /* Check the HMAC if key is provided */ + if (key) { + unsigned char ret_hmac[RPMB_SZ_MAC]; + + rpmb_hmac(key, rpmb_frame->data, 284, ret_hmac); + if (memcmp(ret_hmac, rpmb_frame->mac, RPMB_SZ_MAC)) { + printf("MAC error on block #%d\n", i); + break; + } + } + /* Copy data */ + memcpy(addr + i * RPMB_SZ_DATA, rpmb_frame->data, RPMB_SZ_DATA); + } + return i; +} +int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, + unsigned short cnt, unsigned char *key) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct s_rpmb, rpmb_frame, 1); + unsigned long wcount; + int i; + + for (i = 0; i < cnt; i++) { + if (mmc_rpmb_get_counter(mmc, &wcount)) { + printf("Cannot read RPMB write counter\n"); + break; + } + + /* Fill the request */ + memset(rpmb_frame, 0, sizeof(struct s_rpmb)); + memcpy(rpmb_frame->data, addr + i * RPMB_SZ_DATA, RPMB_SZ_DATA); + rpmb_frame->address = cpu_to_be16(blk + i); + rpmb_frame->block_count = cpu_to_be16(1); + rpmb_frame->write_counter = cpu_to_be32(wcount); + rpmb_frame->request = cpu_to_be16(RPMB_REQ_WRITE_DATA); + /* Computes HMAC */ + rpmb_hmac(key, rpmb_frame->data, 284, rpmb_frame->mac); + + if (mmc_rpmb_request(mmc, rpmb_frame, 1, true)) + break; + + /* Get status */ + if (mmc_rpmb_status(mmc, RPMB_RESP_WRITE_DATA)) + break; + } + return i; +} diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c new file mode 100644 index 000000000..eb7b1158d --- /dev/null +++ b/drivers/mmc/sunxi_mmc.c @@ -0,0 +1,503 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Aaron <leafy.myeh@allwinnertech.com> + * + * MMC driver for allwinner sunxi platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <mmc.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cpu.h> +#include <asm/arch/mmc.h> + +struct sunxi_mmc_des { + u32 reserved1_1:1; + u32 dic:1; /* disable interrupt on completion */ + u32 last_des:1; /* 1-this data buffer is the last buffer */ + u32 first_des:1; /* 1-data buffer is the first buffer, + 0-data buffer contained in the next + descriptor is 1st buffer */ + u32 des_chain:1; /* 1-the 2nd address in the descriptor is the + next descriptor address */ + u32 end_of_ring:1; /* 1-last descriptor flag when using dual + data buffer in descriptor */ + u32 reserved1_2:24; + u32 card_err_sum:1; /* transfer error flag */ + u32 own:1; /* des owner:1-idma owns it, 0-host owns it */ +#define SDXC_DES_NUM_SHIFT 16 +#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT) + u32 data_buf1_sz:16; + u32 data_buf2_sz:16; + u32 buf_addr_ptr1; + u32 buf_addr_ptr2; +}; + +struct sunxi_mmc_host { + unsigned mmc_no; + uint32_t *mclkreg; + unsigned database; + unsigned fatal_err; + unsigned mod_clk; + struct sunxi_mmc *reg; + struct mmc_config cfg; +}; + +/* support 4 mmc hosts */ +struct sunxi_mmc_host mmc_host[4]; + +static int mmc_resource_init(int sdc_no) +{ + struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + debug("init mmc %d resource\n", sdc_no); + + switch (sdc_no) { + case 0: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE; + mmchost->mclkreg = &ccm->sd0_clk_cfg; + break; + case 1: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE; + mmchost->mclkreg = &ccm->sd1_clk_cfg; + break; + case 2: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE; + mmchost->mclkreg = &ccm->sd2_clk_cfg; + break; + case 3: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE; + mmchost->mclkreg = &ccm->sd3_clk_cfg; + break; + default: + printf("Wrong mmc number %d\n", sdc_no); + return -1; + } + mmchost->database = (unsigned int)mmchost->reg + 0x100; + mmchost->mmc_no = sdc_no; + + return 0; +} + +static int mmc_clk_io_on(int sdc_no) +{ + unsigned int pll_clk; + unsigned int divider; + struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + debug("init mmc %d clock and io\n", sdc_no); + + /* config ahb clock */ + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); + + /* config mod clock */ + pll_clk = clock_get_pll6(); + /* should be close to 100 MHz but no more, so round up */ + divider = ((pll_clk + 99999999) / 100000000) - 1; + writel(CCM_MMC_CTRL_ENABLE | CCM_MMC_CTRL_PLL6 | divider, + mmchost->mclkreg); + mmchost->mod_clk = pll_clk / (divider + 1); + + return 0; +} + +static int mmc_update_clk(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned int cmd; + unsigned timeout_msecs = 2000; + + cmd = SUNXI_MMC_CMD_START | + SUNXI_MMC_CMD_UPCLK_ONLY | + SUNXI_MMC_CMD_WAIT_PRE_OVER; + writel(cmd, &mmchost->reg->cmd); + while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) { + if (!timeout_msecs--) + return -1; + udelay(1000); + } + + /* clock update sets various irq status bits, clear these */ + writel(readl(&mmchost->reg->rint), &mmchost->reg->rint); + + return 0; +} + +static int mmc_config_clock(struct mmc *mmc, unsigned div) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned rval = readl(&mmchost->reg->clkcr); + + /* Disable Clock */ + rval &= ~SUNXI_MMC_CLK_ENABLE; + writel(rval, &mmchost->reg->clkcr); + if (mmc_update_clk(mmc)) + return -1; + + /* Change Divider Factor */ + rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; + rval |= div; + writel(rval, &mmchost->reg->clkcr); + if (mmc_update_clk(mmc)) + return -1; + /* Re-enable Clock */ + rval |= SUNXI_MMC_CLK_ENABLE; + writel(rval, &mmchost->reg->clkcr); + + if (mmc_update_clk(mmc)) + return -1; + + return 0; +} + +static void mmc_set_ios(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned int clkdiv = 0; + + debug("set ios: bus_width: %x, clock: %d, mod_clk: %d\n", + mmc->bus_width, mmc->clock, mmchost->mod_clk); + + /* Change clock first */ + clkdiv = (mmchost->mod_clk + (mmc->clock >> 1)) / mmc->clock / 2; + if (mmc->clock) { + if (mmc_config_clock(mmc, clkdiv)) { + mmchost->fatal_err = 1; + return; + } + } + + /* Change bus width */ + if (mmc->bus_width == 8) + writel(0x2, &mmchost->reg->width); + else if (mmc->bus_width == 4) + writel(0x1, &mmchost->reg->width); + else + writel(0x0, &mmchost->reg->width); +} + +static int mmc_core_init(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + + /* Reset controller */ + writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); + + return 0; +} + +static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + const int reading = !!(data->flags & MMC_DATA_READ); + const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY : + SUNXI_MMC_STATUS_FIFO_FULL; + unsigned i; + unsigned byte_cnt = data->blocksize * data->blocks; + unsigned timeout_msecs = 2000; + unsigned *buff = (unsigned int *)(reading ? data->dest : data->src); + + for (i = 0; i < (byte_cnt >> 2); i++) { + while (readl(&mmchost->reg->status) & status_bit) { + if (!timeout_msecs--) + return -1; + udelay(1000); + } + + if (reading) + buff[i] = readl(mmchost->database); + else + writel(buff[i], mmchost->database); + } + + return 0; +} + +static int mmc_trans_data_by_dma(struct mmc *mmc, struct mmc_data *data) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned byte_cnt = data->blocksize * data->blocks; + unsigned char *buff; + unsigned des_idx = 0; + unsigned buff_frag_num = + (byte_cnt + SDXC_DES_BUFFER_MAX_LEN - 1) >> SDXC_DES_NUM_SHIFT; + unsigned remain; + unsigned i, rval; + ALLOC_CACHE_ALIGN_BUFFER(struct sunxi_mmc_des, pdes, buff_frag_num); + + buff = data->flags & MMC_DATA_READ ? + (unsigned char *)data->dest : (unsigned char *)data->src; + remain = byte_cnt & (SDXC_DES_BUFFER_MAX_LEN - 1); + + flush_cache((unsigned long)buff, (unsigned long)byte_cnt); + for (i = 0; i < buff_frag_num; i++, des_idx++) { + memset((void *)&pdes[des_idx], 0, sizeof(struct sunxi_mmc_des)); + pdes[des_idx].des_chain = 1; + pdes[des_idx].own = 1; + pdes[des_idx].dic = 1; + if (buff_frag_num > 1 && i != buff_frag_num - 1) + pdes[des_idx].data_buf1_sz = 0; /* 0 == max_len */ + else + pdes[des_idx].data_buf1_sz = remain; + + pdes[des_idx].buf_addr_ptr1 = + (u32) buff + i * SDXC_DES_BUFFER_MAX_LEN; + if (i == 0) + pdes[des_idx].first_des = 1; + + if (i == buff_frag_num - 1) { + pdes[des_idx].dic = 0; + pdes[des_idx].last_des = 1; + pdes[des_idx].end_of_ring = 1; + pdes[des_idx].buf_addr_ptr2 = 0; + } else { + pdes[des_idx].buf_addr_ptr2 = (u32)&pdes[des_idx + 1]; + } + } + flush_cache((unsigned long)pdes, + sizeof(struct sunxi_mmc_des) * (des_idx + 1)); + + rval = readl(&mmchost->reg->gctrl); + /* Enable DMA */ + writel(rval | SUNXI_MMC_GCTRL_DMA_RESET | SUNXI_MMC_GCTRL_DMA_ENABLE, + &mmchost->reg->gctrl); + /* Reset iDMA */ + writel(SUNXI_MMC_IDMAC_RESET, &mmchost->reg->dmac); + /* Enable iDMA */ + writel(SUNXI_MMC_IDMAC_FIXBURST | SUNXI_MMC_IDMAC_ENABLE, + &mmchost->reg->dmac); + rval = readl(&mmchost->reg->idie) & + ~(SUNXI_MMC_IDIE_TXIRQ|SUNXI_MMC_IDIE_RXIRQ); + if (data->flags & MMC_DATA_WRITE) + rval |= SUNXI_MMC_IDIE_TXIRQ; + else + rval |= SUNXI_MMC_IDIE_RXIRQ; + writel(rval, &mmchost->reg->idie); + writel((u32) pdes, &mmchost->reg->dlba); + writel((0x2 << 28) | (0x7 << 16) | (0x01 << 3), + &mmchost->reg->ftrglevel); + + return 0; +} + +static void mmc_enable_dma_accesses(struct mmc *mmc, int dma) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + + unsigned int gctrl = readl(&mmchost->reg->gctrl); + if (dma) + gctrl &= ~SUNXI_MMC_GCTRL_ACCESS_BY_AHB; + else + gctrl |= SUNXI_MMC_GCTRL_ACCESS_BY_AHB; + writel(gctrl, &mmchost->reg->gctrl); +} + +static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs, + unsigned int done_bit, const char *what) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned int status; + + do { + status = readl(&mmchost->reg->rint); + if (!timeout_msecs-- || + (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) { + debug("%s timeout %x\n", what, + status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT); + return TIMEOUT; + } + udelay(1000); + } while (!(status & done_bit)); + + return 0; +} + +static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned int cmdval = SUNXI_MMC_CMD_START; + unsigned int timeout_msecs; + int error = 0; + unsigned int status = 0; + unsigned int usedma = 0; + unsigned int bytecnt = 0; + + if (mmchost->fatal_err) + return -1; + if (cmd->resp_type & MMC_RSP_BUSY) + debug("mmc cmd %d check rsp busy\n", cmd->cmdidx); + if (cmd->cmdidx == 12) + return 0; + + if (!cmd->cmdidx) + cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; + if (cmd->resp_type & MMC_RSP_PRESENT) + cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE; + if (cmd->resp_type & MMC_RSP_136) + cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE; + if (cmd->resp_type & MMC_RSP_CRC) + cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC; + + if (data) { + if ((u32) data->dest & 0x3) { + error = -1; + goto out; + } + + cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER; + if (data->flags & MMC_DATA_WRITE) + cmdval |= SUNXI_MMC_CMD_WRITE; + if (data->blocks > 1) + cmdval |= SUNXI_MMC_CMD_AUTO_STOP; + writel(data->blocksize, &mmchost->reg->blksz); + writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt); + } + + debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no, + cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg); + writel(cmd->cmdarg, &mmchost->reg->arg); + + if (!data) + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); + + /* + * transfer data and check status + * STATREG[2] : FIFO empty + * STATREG[3] : FIFO full + */ + if (data) { + int ret = 0; + + bytecnt = data->blocksize * data->blocks; + debug("trans data %d bytes\n", bytecnt); +#if defined(CONFIG_MMC_SUNXI_USE_DMA) && !defined(CONFIG_SPL_BUILD) + if (bytecnt > 64) { +#else + if (0) { +#endif + usedma = 1; + mmc_enable_dma_accesses(mmc, 1); + ret = mmc_trans_data_by_dma(mmc, data); + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); + } else { + mmc_enable_dma_accesses(mmc, 0); + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); + ret = mmc_trans_data_by_cpu(mmc, data); + } + if (ret) { + error = readl(&mmchost->reg->rint) & \ + SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT; + error = TIMEOUT; + goto out; + } + } + + error = mmc_rint_wait(mmc, 0xfffff, SUNXI_MMC_RINT_COMMAND_DONE, "cmd"); + if (error) + goto out; + + if (data) { + timeout_msecs = usedma ? 120 * bytecnt : 120; + debug("cacl timeout %x msec\n", timeout_msecs); + error = mmc_rint_wait(mmc, timeout_msecs, + data->blocks > 1 ? + SUNXI_MMC_RINT_AUTO_COMMAND_DONE : + SUNXI_MMC_RINT_DATA_OVER, + "data"); + if (error) + goto out; + } + + if (cmd->resp_type & MMC_RSP_BUSY) { + timeout_msecs = 2000; + do { + status = readl(&mmchost->reg->status); + if (!timeout_msecs--) { + debug("busy timeout\n"); + error = TIMEOUT; + goto out; + } + udelay(1000); + } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY); + } + + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[0] = readl(&mmchost->reg->resp3); + cmd->response[1] = readl(&mmchost->reg->resp2); + cmd->response[2] = readl(&mmchost->reg->resp1); + cmd->response[3] = readl(&mmchost->reg->resp0); + debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n", + cmd->response[3], cmd->response[2], + cmd->response[1], cmd->response[0]); + } else { + cmd->response[0] = readl(&mmchost->reg->resp0); + debug("mmc resp 0x%08x\n", cmd->response[0]); + } +out: + if (data && usedma) { + /* IDMASTAREG + * IDST[0] : idma tx int + * IDST[1] : idma rx int + * IDST[2] : idma fatal bus error + * IDST[4] : idma descriptor invalid + * IDST[5] : idma error summary + * IDST[8] : idma normal interrupt sumary + * IDST[9] : idma abnormal interrupt sumary + */ + status = readl(&mmchost->reg->idst); + writel(status, &mmchost->reg->idst); + writel(0, &mmchost->reg->idie); + writel(0, &mmchost->reg->dmac); + writel(readl(&mmchost->reg->gctrl) & ~SUNXI_MMC_GCTRL_DMA_ENABLE, + &mmchost->reg->gctrl); + } + if (error < 0) { + writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); + mmc_update_clk(mmc); + } + writel(0xffffffff, &mmchost->reg->rint); + writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET, + &mmchost->reg->gctrl); + + return error; +} + +static const struct mmc_ops sunxi_mmc_ops = { + .send_cmd = mmc_send_cmd, + .set_ios = mmc_set_ios, + .init = mmc_core_init, +}; + +int sunxi_mmc_init(int sdc_no) +{ + struct mmc_config *cfg = &mmc_host[sdc_no].cfg; + + memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host)); + + cfg->name = "SUNXI SD/MMC"; + cfg->ops = &sunxi_mmc_ops; + + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + cfg->host_caps = MMC_MODE_4BIT; + cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + cfg->f_min = 400000; + cfg->f_max = 52000000; + + mmc_resource_init(sdc_no); + mmc_clk_io_on(sdc_no); + + if (mmc_create(cfg, &mmc_host[sdc_no]) == NULL) + return -1; + + return 0; +} diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index ed67eec25..ca9c4aa15 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -18,7 +18,7 @@ DECLARE_GLOBAL_DATA_PTR; -struct mmc_host mmc_host[MAX_HOSTS]; +struct mmc_host mmc_host[CONFIG_SYS_MMC_MAX_DEVICE]; #ifndef CONFIG_OF_CONTROL #error "Please enable device tree support to use this driver" @@ -669,13 +669,14 @@ static int process_nodes(const void *blob, int node_list[], int count) void tegra_mmc_init(void) { - int node_list[MAX_HOSTS], count; + int node_list[CONFIG_SYS_MMC_MAX_DEVICE], count; const void *blob = gd->fdt_blob; debug("%s entry\n", __func__); /* See if any Tegra124 MMC controllers are present */ count = fdtdec_find_aliases_for_id(blob, "sdhci", - COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, MAX_HOSTS); + COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, + CONFIG_SYS_MMC_MAX_DEVICE); debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count); if (process_nodes(blob, node_list, count)) { printf("%s: Error processing T30 mmc node(s)!\n", __func__); @@ -684,7 +685,8 @@ void tegra_mmc_init(void) /* See if any Tegra30 MMC controllers are present */ count = fdtdec_find_aliases_for_id(blob, "sdhci", - COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, MAX_HOSTS); + COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, + CONFIG_SYS_MMC_MAX_DEVICE); debug("%s: count of T30 sdhci nodes is %d\n", __func__, count); if (process_nodes(blob, node_list, count)) { printf("%s: Error processing T30 mmc node(s)!\n", __func__); @@ -693,7 +695,8 @@ void tegra_mmc_init(void) /* Now look for any Tegra20 MMC controllers */ count = fdtdec_find_aliases_for_id(blob, "sdhci", - COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, MAX_HOSTS); + COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, + CONFIG_SYS_MMC_MAX_DEVICE); debug("%s: count of T20 sdhci nodes is %d\n", __func__, count); if (process_nodes(blob, node_list, count)) { printf("%s: Error processing T20 mmc node(s)!\n", __func__); diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 881a63618..bf99b8e67 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -403,7 +403,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, dat[byte_pos] ^= 1 << bit_pos; printf("nand: bit-flip corrected @data=%d\n", byte_pos); } else if (byte_pos < error_max) { - read_ecc[byte_pos - SECTOR_BYTES] = 1 << bit_pos; + read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos; printf("nand: bit-flip corrected @oob=%d\n", byte_pos - SECTOR_BYTES); } else { diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 78751b260..7186e3b49 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -249,7 +249,7 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) rx_descs_init(dev); tx_descs_init(dev); - writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode); + writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, &dma_p->opmode); @@ -280,10 +280,18 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) u32 desc_num = priv->tx_currdescnum; struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; - /* Invalidate only "status" field for the following check */ - invalidate_dcache_range((unsigned long)&desc_p->txrx_status, - (unsigned long)&desc_p->txrx_status + - sizeof(desc_p->txrx_status)); + /* + * Strictly we only need to invalidate the "txrx_status" field + * for the following check, but on some platforms we cannot + * invalidate only 4 bytes, so roundup to + * ARCH_DMA_MINALIGN. This is safe because the individual + * descriptors in the array are each aligned to + * ARCH_DMA_MINALIGN. + */ + invalidate_dcache_range( + (unsigned long)desc_p, + (unsigned long)desc_p + + roundup(sizeof(desc_p->txrx_status), ARCH_DMA_MINALIGN)); /* Check if the descriptor is owned by CPU */ if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { @@ -351,7 +359,7 @@ static int dw_eth_recv(struct eth_device *dev) /* Invalidate received data */ invalidate_dcache_range((unsigned long)desc_p->dmamac_addr, (unsigned long)desc_p->dmamac_addr + - length); + roundup(length, ARCH_DMA_MINALIGN)); NetReceive(desc_p->dmamac_addr, length); @@ -414,7 +422,8 @@ int designware_initialize(ulong base_addr, u32 interface) * Since the priv structure contains the descriptors which need a strict * buswidth alignment, memalign is used to allocate memory */ - priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev)); + priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, + sizeof(struct dw_eth_dev)); if (!priv) { free(dev); return -ENOMEM; diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 382b0c7f0..ce5110205 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -77,18 +77,18 @@ struct eth_dma_regs { #define DW_DMA_BASE_OFFSET (0x1000) +/* Default DMA Burst length */ +#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL +#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8 +#endif + /* Bus mode register definitions */ #define FIXEDBURST (1 << 16) #define PRIORXTX_41 (3 << 14) #define PRIORXTX_31 (2 << 14) #define PRIORXTX_21 (1 << 14) #define PRIORXTX_11 (0 << 14) -#define BURST_1 (1 << 8) -#define BURST_2 (2 << 8) -#define BURST_4 (4 << 8) -#define BURST_8 (8 << 8) -#define BURST_16 (16 << 8) -#define BURST_32 (32 << 8) +#define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8) #define RXHIGHPRIO (1 << 1) #define DMAMAC_SRST (1 << 0) @@ -215,15 +215,14 @@ struct dmamacdescr { #endif struct dw_eth_dev { - u32 interface; - u32 tx_currdescnum; - u32 rx_currdescnum; - struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; + char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); + char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); - char txbuffs[TX_TOTAL_BUFSIZE]; - char rxbuffs[RX_TOTAL_BUFSIZE]; + u32 interface; + u32 tx_currdescnum; + u32 rx_currdescnum; struct eth_mac_regs *mac_regs_p; struct eth_dma_regs *dma_regs_p; diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 4129bdabf..920bbdce6 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o diff --git a/drivers/power/pmic/pmic_ltc3676.c b/drivers/power/pmic/pmic_ltc3676.c new file mode 100644 index 000000000..9b874cb07 --- /dev/null +++ b/drivers/power/pmic/pmic_ltc3676.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Tim Harvey <tharvey@gateworks.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/ltc3676_pmic.h> + +int power_ltc3676_init(unsigned char bus) +{ + static const char name[] = "LTC3676_PMIC"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = LTC3676_NUM_OF_REGS; + p->hw.i2c.addr = CONFIG_POWER_LTC3676_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + return 0; +} diff --git a/drivers/power/pmic/pmic_pfuze100.c b/drivers/power/pmic/pmic_pfuze100.c index 22c1f15ee..21f12d256 100644 --- a/drivers/power/pmic/pmic_pfuze100.c +++ b/drivers/power/pmic/pmic_pfuze100.c @@ -11,7 +11,7 @@ #include <power/pmic.h> #include <power/pfuze100_pmic.h> -int pmic_init(unsigned char bus) +int power_pfuze100_init(unsigned char bus) { static const char name[] = "PFUZE100_PMIC"; struct pmic *p = pmic_alloc(); diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 896c8d407..66becdc78 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_THOR_FUNCTION) += f_thor.o obj-$(CONFIG_USBDOWNLOAD_GADGET) += g_dnl.o obj-$(CONFIG_DFU_FUNCTION) += f_dfu.o obj-$(CONFIG_USB_GADGET_MASS_STORAGE) += f_mass_storage.o +obj-$(CONFIG_CMD_FASTBOOT) += f_fastboot.o endif ifdef CONFIG_USB_ETHER obj-y += ether.o diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 02d3fdade..9cd003636 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -205,13 +205,26 @@ static void ci_invalidate_qtd(int ep_num) static struct usb_request * ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) { - struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); - return &ci_ep->req; + struct ci_req *ci_req; + + ci_req = memalign(ARCH_DMA_MINALIGN, sizeof(*ci_req)); + if (!ci_req) + return NULL; + + INIT_LIST_HEAD(&ci_req->queue); + ci_req->b_buf = 0; + + return &ci_req->req; } -static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req) +static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *req) { - return; + struct ci_req *ci_req; + + ci_req = container_of(req, struct ci_req, req); + if (ci_req->b_buf) + free(ci_req->b_buf); + free(ci_req); } static void ep_enable(int num, int in, int maxpacket) @@ -267,99 +280,102 @@ static int ci_ep_disable(struct usb_ep *ep) return 0; } -static int ci_bounce(struct ci_ep *ep, int in) +static int ci_bounce(struct ci_req *ci_req, int in) { - uint32_t addr = (uint32_t)ep->req.buf; - uint32_t ba; + struct usb_request *req = &ci_req->req; + uint32_t addr = (uint32_t)req->buf; + uint32_t hwaddr; + uint32_t aligned_used_len; /* Input buffer address is not aligned. */ if (addr & (ARCH_DMA_MINALIGN - 1)) goto align; /* Input buffer length is not aligned. */ - if (ep->req.length & (ARCH_DMA_MINALIGN - 1)) + if (req->length & (ARCH_DMA_MINALIGN - 1)) goto align; /* The buffer is well aligned, only flush cache. */ - ep->b_len = ep->req.length; - ep->b_buf = ep->req.buf; + ci_req->hw_len = req->length; + ci_req->hw_buf = req->buf; goto flush; align: - /* Use internal buffer for small payloads. */ - if (ep->req.length <= 64) { - ep->b_len = 64; - ep->b_buf = ep->b_fast; - } else { - ep->b_len = roundup(ep->req.length, ARCH_DMA_MINALIGN); - ep->b_buf = memalign(ARCH_DMA_MINALIGN, ep->b_len); - if (!ep->b_buf) + if (ci_req->b_buf && req->length > ci_req->b_len) { + free(ci_req->b_buf); + ci_req->b_buf = 0; + } + if (!ci_req->b_buf) { + ci_req->b_len = roundup(req->length, ARCH_DMA_MINALIGN); + ci_req->b_buf = memalign(ARCH_DMA_MINALIGN, ci_req->b_len); + if (!ci_req->b_buf) return -ENOMEM; } + ci_req->hw_len = ci_req->b_len; + ci_req->hw_buf = ci_req->b_buf; + if (in) - memcpy(ep->b_buf, ep->req.buf, ep->req.length); + memcpy(ci_req->hw_buf, req->buf, req->length); flush: - ba = (uint32_t)ep->b_buf; - flush_dcache_range(ba, ba + ep->b_len); + hwaddr = (uint32_t)ci_req->hw_buf; + aligned_used_len = roundup(req->length, ARCH_DMA_MINALIGN); + flush_dcache_range(hwaddr, hwaddr + aligned_used_len); return 0; } -static void ci_debounce(struct ci_ep *ep, int in) +static void ci_debounce(struct ci_req *ci_req, int in) { - uint32_t addr = (uint32_t)ep->req.buf; - uint32_t ba = (uint32_t)ep->b_buf; + struct usb_request *req = &ci_req->req; + uint32_t addr = (uint32_t)req->buf; + uint32_t hwaddr = (uint32_t)ci_req->hw_buf; + uint32_t aligned_used_len; - if (in) { - if (addr == ba) - return; /* not a bounce */ - goto free; - } - invalidate_dcache_range(ba, ba + ep->b_len); + if (in) + return; + + aligned_used_len = roundup(req->actual, ARCH_DMA_MINALIGN); + invalidate_dcache_range(hwaddr, hwaddr + aligned_used_len); - if (addr == ba) - return; /* not a bounce */ + if (addr == hwaddr) + return; /* not a bounce */ - memcpy(ep->req.buf, ep->b_buf, ep->req.actual); -free: - /* Large payloads use allocated buffer, free it. */ - if (ep->b_buf != ep->b_fast) - free(ep->b_buf); + memcpy(req->buf, ci_req->hw_buf, req->actual); } -static int ci_ep_queue(struct usb_ep *ep, - struct usb_request *req, gfp_t gfp_flags) +static void ci_ep_submit_next_request(struct ci_ep *ci_ep) { - struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; struct ept_queue_item *item; struct ept_queue_head *head; - int bit, num, len, in, ret; + int bit, num, len, in; + struct ci_req *ci_req; + + ci_ep->req_primed = true; + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; item = ci_get_qtd(num, in); head = ci_get_qh(num, in); - len = req->length; - ret = ci_bounce(ci_ep, in); - if (ret) - return ret; + ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue); + len = ci_req->req.length; item->next = TERMINATE; item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE; - item->page0 = (uint32_t)ci_ep->b_buf; - item->page1 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x1000; - item->page2 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x2000; - item->page3 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x3000; - item->page4 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x4000; + item->page0 = (uint32_t)ci_req->hw_buf; + item->page1 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x1000; + item->page2 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x2000; + item->page3 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x3000; + item->page4 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x4000; ci_flush_qtd(num); head->next = (unsigned) item; head->info = 0; - DBG("ept%d %s queue len %x, buffer %p\n", - num, in ? "in" : "out", len, ci_ep->b_buf); + DBG("ept%d %s queue len %x, req %p, buffer %p\n", + num, in ? "in" : "out", len, ci_req, ci_req->hw_buf); ci_flush_qh(num); if (in) @@ -368,6 +384,29 @@ static int ci_ep_queue(struct usb_ep *ep, bit = EPT_RX(num); writel(bit, &udc->epprime); +} + +static int ci_ep_queue(struct usb_ep *ep, + struct usb_request *req, gfp_t gfp_flags) +{ + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + struct ci_req *ci_req = container_of(req, struct ci_req, req); + int in, ret; + int __maybe_unused num; + + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; + + ret = ci_bounce(ci_req, in); + if (ret) + return ret; + + DBG("ept%d %s pre-queue req %p, buffer %p\n", + num, in ? "in" : "out", ci_req, ci_req->hw_buf); + list_add_tail(&ci_req->queue, &ci_ep->queue); + + if (!ci_ep->req_primed) + ci_ep_submit_next_request(ci_ep); return 0; } @@ -376,6 +415,8 @@ static void handle_ep_complete(struct ci_ep *ep) { struct ept_queue_item *item; int num, in, len; + struct ci_req *ci_req; + num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0; if (num == 0) @@ -383,20 +424,27 @@ static void handle_ep_complete(struct ci_ep *ep) item = ci_get_qtd(num, in); ci_invalidate_qtd(num); + len = (item->info >> 16) & 0x7fff; if (item->info & 0xff) printf("EP%d/%s FAIL info=%x pg0=%x\n", num, in ? "in" : "out", item->info, item->page0); - len = (item->info >> 16) & 0x7fff; - ep->req.actual = ep->req.length - len; - ci_debounce(ep, in); + ci_req = list_first_entry(&ep->queue, struct ci_req, queue); + list_del_init(&ci_req->queue); + ep->req_primed = false; + + if (!list_empty(&ep->queue)) + ci_ep_submit_next_request(ep); + + ci_req->req.actual = ci_req->req.length - len; + ci_debounce(ci_req, in); - DBG("ept%d %s complete %x\n", - num, in ? "in" : "out", len); - ep->req.complete(&ep->ep, &ep->req); + DBG("ept%d %s req %p, complete %x\n", + num, in ? "in" : "out", ci_req, len); + ci_req->req.complete(&ep->ep, &ci_req->req); if (num == 0) { - ep->req.length = 0; - usb_ep_queue(&ep->ep, &ep->req, 0); + ci_req->req.length = 0; + usb_ep_queue(&ep->ep, &ci_req->req, 0); ep->desc = &ep0_in_desc; } } @@ -405,13 +453,18 @@ static void handle_ep_complete(struct ci_ep *ep) static void handle_setup(void) { - struct usb_request *req = &controller.ep[0].req; + struct ci_ep *ci_ep = &controller.ep[0]; + struct ci_req *ci_req; + struct usb_request *req; struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; struct ept_queue_head *head; struct usb_ctrlrequest r; int status = 0; int num, in, _num, _in, i; char *buf; + + ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue); + req = &ci_req->req; head = ci_get_qh(0, 0); /* EP0 OUT */ ci_invalidate_qh(0); @@ -424,6 +477,9 @@ static void handle_setup(void) DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest), r.bRequestType, r.bRequest, r.wIndex, r.wValue); + list_del_init(&ci_req->queue); + ci_ep->req_primed = false; + switch (SETUP(r.bRequestType, r.bRequest)) { case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE): _num = r.wIndex & 15; @@ -701,6 +757,8 @@ static int ci_udc_probe(void) /* Init EP 0 */ memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init)); controller.ep[0].desc = &ep0_in_desc; + INIT_LIST_HEAD(&controller.ep[0].queue); + controller.ep[0].req_primed = false; controller.gadget.ep0 = &controller.ep[0].ep; INIT_LIST_HEAD(&controller.gadget.ep0->ep_list); @@ -708,6 +766,8 @@ static int ci_udc_probe(void) for (i = 1; i < NUM_ENDPOINTS; i++) { memcpy(&controller.ep[i].ep, &ci_ep_init[1], sizeof(*ci_ep_init)); + INIT_LIST_HEAD(&controller.ep[i].queue); + controller.ep[i].req_primed = false; list_add_tail(&controller.ep[i].ep.ep_list, &controller.gadget.ep_list); } diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h index 4425fd934..23cff56d7 100644 --- a/drivers/usb/gadget/ci_udc.h +++ b/drivers/usb/gadget/ci_udc.h @@ -77,15 +77,22 @@ struct ci_udc { #define CTRL_TXT_BULK (2 << 18) #define CTRL_RXT_BULK (2 << 2) +struct ci_req { + struct usb_request req; + struct list_head queue; + /* Bounce buffer allocated if needed to align the transfer */ + uint8_t *b_buf; + uint32_t b_len; + /* Buffer for the current transfer. Either req.buf/len or b_buf/len */ + uint8_t *hw_buf; + uint32_t hw_len; +}; + struct ci_ep { struct usb_ep ep; struct list_head queue; + bool req_primed; const struct usb_endpoint_descriptor *desc; - - struct usb_request req; - uint8_t *b_buf; - uint32_t b_len; - uint8_t b_fast[64] __aligned(ARCH_DMA_MINALIGN); }; struct ci_drv { diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c index 1b1e1793d..859fe828d 100644 --- a/drivers/usb/gadget/f_dfu.c +++ b/drivers/usb/gadget/f_dfu.c @@ -175,10 +175,17 @@ static void dnload_request_flush(struct usb_ep *ep, struct usb_request *req) req->length, f_dfu->blk_seq_num); } +static inline int dfu_get_manifest_timeout(struct dfu_entity *dfu) +{ + return dfu->poll_timeout ? dfu->poll_timeout(dfu) : + DFU_MANIFEST_POLL_TIMEOUT; +} + static void handle_getstatus(struct usb_request *req) { struct dfu_status *dstat = (struct dfu_status *)req->buf; struct f_dfu *f_dfu = req->context; + struct dfu_entity *dfu = dfu_get_entity(f_dfu->altsetting); dfu_set_poll_timeout(dstat, 0); @@ -191,7 +198,8 @@ static void handle_getstatus(struct usb_request *req) f_dfu->dfu_state = DFU_STATE_dfuMANIFEST; break; case DFU_STATE_dfuMANIFEST: - dfu_set_poll_timeout(dstat, DFU_MANIFEST_POLL_TIMEOUT); + dfu_set_poll_timeout(dstat, dfu_get_manifest_timeout(dfu)); + break; default: break; } diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c new file mode 100644 index 000000000..9dd85b636 --- /dev/null +++ b/drivers/usb/gadget/f_fastboot.c @@ -0,0 +1,513 @@ +/* + * (C) Copyright 2008 - 2009 + * Windriver, <www.windriver.com> + * Tom Rix <Tom.Rix@windriver.com> + * + * Copyright 2011 Sebastian Andrzej Siewior <bigeasy@linutronix.de> + * + * Copyright 2014 Linaro, Ltd. + * Rob Herring <robh@kernel.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <errno.h> +#include <malloc.h> +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> +#include <linux/usb/composite.h> +#include <linux/compiler.h> +#include <version.h> +#include <g_dnl.h> + +#define FASTBOOT_VERSION "0.4" + +#define FASTBOOT_INTERFACE_CLASS 0xff +#define FASTBOOT_INTERFACE_SUB_CLASS 0x42 +#define FASTBOOT_INTERFACE_PROTOCOL 0x03 + +#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0 (0x0200) +#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1 (0x0040) +#define TX_ENDPOINT_MAXIMUM_PACKET_SIZE (0x0040) + +/* The 64 defined bytes plus \0 */ +#define RESPONSE_LEN (64 + 1) + +#define EP_BUFFER_SIZE 4096 + +struct f_fastboot { + struct usb_function usb_function; + + /* IN/OUT EP's and correspoinding requests */ + struct usb_ep *in_ep, *out_ep; + struct usb_request *in_req, *out_req; +}; + +static inline struct f_fastboot *func_to_fastboot(struct usb_function *f) +{ + return container_of(f, struct f_fastboot, usb_function); +} + +static struct f_fastboot *fastboot_func; +static unsigned int download_size; +static unsigned int download_bytes; + +static struct usb_endpoint_descriptor fs_ep_in = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = TX_ENDPOINT_MAXIMUM_PACKET_SIZE, + .bInterval = 0x00, +}; + +static struct usb_endpoint_descriptor fs_ep_out = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_OUT, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1, + .bInterval = 0x00, +}; + +static struct usb_endpoint_descriptor hs_ep_out = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_OUT, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0, + .bInterval = 0x00, +}; + +static struct usb_interface_descriptor interface_desc = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0x00, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x02, + .bInterfaceClass = FASTBOOT_INTERFACE_CLASS, + .bInterfaceSubClass = FASTBOOT_INTERFACE_SUB_CLASS, + .bInterfaceProtocol = FASTBOOT_INTERFACE_PROTOCOL, +}; + +static struct usb_descriptor_header *fb_runtime_descs[] = { + (struct usb_descriptor_header *)&interface_desc, + (struct usb_descriptor_header *)&fs_ep_in, + (struct usb_descriptor_header *)&hs_ep_out, + NULL, +}; + +/* + * static strings, in UTF-8 + */ +static const char fastboot_name[] = "Android Fastboot"; + +static struct usb_string fastboot_string_defs[] = { + [0].s = fastboot_name, + { } /* end of list */ +}; + +static struct usb_gadget_strings stringtab_fastboot = { + .language = 0x0409, /* en-us */ + .strings = fastboot_string_defs, +}; + +static struct usb_gadget_strings *fastboot_strings[] = { + &stringtab_fastboot, + NULL, +}; + +static void rx_handler_command(struct usb_ep *ep, struct usb_request *req); + +static void fastboot_complete(struct usb_ep *ep, struct usb_request *req) +{ + int status = req->status; + if (!status) + return; + printf("status: %d ep '%s' trans: %d\n", status, ep->name, req->actual); +} + +static int fastboot_bind(struct usb_configuration *c, struct usb_function *f) +{ + int id; + struct usb_gadget *gadget = c->cdev->gadget; + struct f_fastboot *f_fb = func_to_fastboot(f); + + /* DYNAMIC interface numbers assignments */ + id = usb_interface_id(c, f); + if (id < 0) + return id; + interface_desc.bInterfaceNumber = id; + + id = usb_string_id(c->cdev); + if (id < 0) + return id; + fastboot_string_defs[0].id = id; + interface_desc.iInterface = id; + + f_fb->in_ep = usb_ep_autoconfig(gadget, &fs_ep_in); + if (!f_fb->in_ep) + return -ENODEV; + f_fb->in_ep->driver_data = c->cdev; + + f_fb->out_ep = usb_ep_autoconfig(gadget, &fs_ep_out); + if (!f_fb->out_ep) + return -ENODEV; + f_fb->out_ep->driver_data = c->cdev; + + hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress; + + return 0; +} + +static void fastboot_unbind(struct usb_configuration *c, struct usb_function *f) +{ + memset(fastboot_func, 0, sizeof(*fastboot_func)); +} + +static void fastboot_disable(struct usb_function *f) +{ + struct f_fastboot *f_fb = func_to_fastboot(f); + + usb_ep_disable(f_fb->out_ep); + usb_ep_disable(f_fb->in_ep); + + if (f_fb->out_req) { + free(f_fb->out_req->buf); + usb_ep_free_request(f_fb->out_ep, f_fb->out_req); + f_fb->out_req = NULL; + } + if (f_fb->in_req) { + free(f_fb->in_req->buf); + usb_ep_free_request(f_fb->in_ep, f_fb->in_req); + f_fb->in_req = NULL; + } +} + +static struct usb_request *fastboot_start_ep(struct usb_ep *ep) +{ + struct usb_request *req; + + req = usb_ep_alloc_request(ep, 0); + if (!req) + return NULL; + + req->length = EP_BUFFER_SIZE; + req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, EP_BUFFER_SIZE); + if (!req->buf) { + usb_ep_free_request(ep, req); + return NULL; + } + + memset(req->buf, 0, req->length); + return req; +} + +static int fastboot_set_alt(struct usb_function *f, + unsigned interface, unsigned alt) +{ + int ret; + struct usb_composite_dev *cdev = f->config->cdev; + struct usb_gadget *gadget = cdev->gadget; + struct f_fastboot *f_fb = func_to_fastboot(f); + + debug("%s: func: %s intf: %d alt: %d\n", + __func__, f->name, interface, alt); + + /* make sure we don't enable the ep twice */ + if (gadget->speed == USB_SPEED_HIGH) + ret = usb_ep_enable(f_fb->out_ep, &hs_ep_out); + else + ret = usb_ep_enable(f_fb->out_ep, &fs_ep_out); + if (ret) { + puts("failed to enable out ep\n"); + return ret; + } + + f_fb->out_req = fastboot_start_ep(f_fb->out_ep); + if (!f_fb->out_req) { + puts("failed to alloc out req\n"); + ret = -EINVAL; + goto err; + } + f_fb->out_req->complete = rx_handler_command; + + ret = usb_ep_enable(f_fb->in_ep, &fs_ep_in); + if (ret) { + puts("failed to enable in ep\n"); + goto err; + } + + f_fb->in_req = fastboot_start_ep(f_fb->in_ep); + if (!f_fb->in_req) { + puts("failed alloc req in\n"); + ret = -EINVAL; + goto err; + } + f_fb->in_req->complete = fastboot_complete; + + ret = usb_ep_queue(f_fb->out_ep, f_fb->out_req, 0); + if (ret) + goto err; + + return 0; +err: + fastboot_disable(f); + return ret; +} + +static int fastboot_add(struct usb_configuration *c) +{ + struct f_fastboot *f_fb = fastboot_func; + int status; + + debug("%s: cdev: 0x%p\n", __func__, c->cdev); + + if (!f_fb) { + f_fb = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*f_fb)); + if (!f_fb) + return -ENOMEM; + + fastboot_func = f_fb; + memset(f_fb, 0, sizeof(*f_fb)); + } + + f_fb->usb_function.name = "f_fastboot"; + f_fb->usb_function.hs_descriptors = fb_runtime_descs; + f_fb->usb_function.bind = fastboot_bind; + f_fb->usb_function.unbind = fastboot_unbind; + f_fb->usb_function.set_alt = fastboot_set_alt; + f_fb->usb_function.disable = fastboot_disable; + f_fb->usb_function.strings = fastboot_strings; + + status = usb_add_function(c, &f_fb->usb_function); + if (status) { + free(f_fb); + fastboot_func = f_fb; + } + + return status; +} +DECLARE_GADGET_BIND_CALLBACK(usb_dnl_fastboot, fastboot_add); + +int fastboot_tx_write(const char *buffer, unsigned int buffer_size) +{ + struct usb_request *in_req = fastboot_func->in_req; + int ret; + + memcpy(in_req->buf, buffer, buffer_size); + in_req->length = buffer_size; + ret = usb_ep_queue(fastboot_func->in_ep, in_req, 0); + if (ret) + printf("Error %d on queue\n", ret); + return 0; +} + +static int fastboot_tx_write_str(const char *buffer) +{ + return fastboot_tx_write(buffer, strlen(buffer)); +} + +static void compl_do_reset(struct usb_ep *ep, struct usb_request *req) +{ + do_reset(NULL, 0, 0, NULL); +} + +static void cb_reboot(struct usb_ep *ep, struct usb_request *req) +{ + fastboot_func->in_req->complete = compl_do_reset; + fastboot_tx_write_str("OKAY"); +} + +static int strcmp_l1(const char *s1, const char *s2) +{ + if (!s1 || !s2) + return -1; + return strncmp(s1, s2, strlen(s1)); +} + +static void cb_getvar(struct usb_ep *ep, struct usb_request *req) +{ + char *cmd = req->buf; + char response[RESPONSE_LEN]; + const char *s; + + strcpy(response, "OKAY"); + strsep(&cmd, ":"); + if (!cmd) { + fastboot_tx_write_str("FAILmissing var"); + return; + } + + if (!strcmp_l1("version", cmd)) { + strncat(response, FASTBOOT_VERSION, sizeof(response)); + } else if (!strcmp_l1("bootloader-version", cmd)) { + strncat(response, U_BOOT_VERSION, sizeof(response)); + } else if (!strcmp_l1("downloadsize", cmd)) { + char str_num[12]; + + sprintf(str_num, "%08x", CONFIG_USB_FASTBOOT_BUF_SIZE); + strncat(response, str_num, sizeof(response)); + } else if (!strcmp_l1("serialno", cmd)) { + s = getenv("serial#"); + if (s) + strncat(response, s, sizeof(response)); + else + strcpy(response, "FAILValue not set"); + } else { + strcpy(response, "FAILVariable not implemented"); + } + fastboot_tx_write_str(response); +} + +static unsigned int rx_bytes_expected(void) +{ + int rx_remain = download_size - download_bytes; + if (rx_remain < 0) + return 0; + if (rx_remain > EP_BUFFER_SIZE) + return EP_BUFFER_SIZE; + return rx_remain; +} + +#define BYTES_PER_DOT 0x20000 +static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) +{ + char response[RESPONSE_LEN]; + unsigned int transfer_size = download_size - download_bytes; + const unsigned char *buffer = req->buf; + unsigned int buffer_size = req->actual; + + if (req->status != 0) { + printf("Bad status: %d\n", req->status); + return; + } + + if (buffer_size < transfer_size) + transfer_size = buffer_size; + + memcpy((void *)CONFIG_USB_FASTBOOT_BUF_ADDR + download_bytes, + buffer, transfer_size); + + download_bytes += transfer_size; + + /* Check if transfer is done */ + if (download_bytes >= download_size) { + /* + * Reset global transfer variable, keep download_bytes because + * it will be used in the next possible flashing command + */ + download_size = 0; + req->complete = rx_handler_command; + req->length = EP_BUFFER_SIZE; + + sprintf(response, "OKAY"); + fastboot_tx_write_str(response); + + printf("\ndownloading of %d bytes finished\n", download_bytes); + } else { + req->length = rx_bytes_expected(); + if (req->length < ep->maxpacket) + req->length = ep->maxpacket; + } + + if (download_bytes && !(download_bytes % BYTES_PER_DOT)) { + putc('.'); + if (!(download_bytes % (74 * BYTES_PER_DOT))) + putc('\n'); + } + req->actual = 0; + usb_ep_queue(ep, req, 0); +} + +static void cb_download(struct usb_ep *ep, struct usb_request *req) +{ + char *cmd = req->buf; + char response[RESPONSE_LEN]; + + strsep(&cmd, ":"); + download_size = simple_strtoul(cmd, NULL, 16); + download_bytes = 0; + + printf("Starting download of %d bytes\n", download_size); + + if (0 == download_size) { + sprintf(response, "FAILdata invalid size"); + } else if (download_size > CONFIG_USB_FASTBOOT_BUF_SIZE) { + download_size = 0; + sprintf(response, "FAILdata too large"); + } else { + sprintf(response, "DATA%08x", download_size); + req->complete = rx_handler_dl_image; + req->length = rx_bytes_expected(); + if (req->length < ep->maxpacket) + req->length = ep->maxpacket; + } + fastboot_tx_write_str(response); +} + +static void do_bootm_on_complete(struct usb_ep *ep, struct usb_request *req) +{ + char boot_addr_start[12]; + char *bootm_args[] = { "bootm", boot_addr_start, NULL }; + + puts("Booting kernel..\n"); + + sprintf(boot_addr_start, "0x%lx", load_addr); + do_bootm(NULL, 0, 2, bootm_args); + + /* This only happens if image is somehow faulty so we start over */ + do_reset(NULL, 0, 0, NULL); +} + +static void cb_boot(struct usb_ep *ep, struct usb_request *req) +{ + fastboot_func->in_req->complete = do_bootm_on_complete; + fastboot_tx_write_str("OKAY"); +} + +struct cmd_dispatch_info { + char *cmd; + void (*cb)(struct usb_ep *ep, struct usb_request *req); +}; + +static const struct cmd_dispatch_info cmd_dispatch_info[] = { + { + .cmd = "reboot", + .cb = cb_reboot, + }, { + .cmd = "getvar:", + .cb = cb_getvar, + }, { + .cmd = "download:", + .cb = cb_download, + }, { + .cmd = "boot", + .cb = cb_boot, + }, +}; + +static void rx_handler_command(struct usb_ep *ep, struct usb_request *req) +{ + char *cmdbuf = req->buf; + void (*func_cb)(struct usb_ep *ep, struct usb_request *req) = NULL; + int i; + + for (i = 0; i < ARRAY_SIZE(cmd_dispatch_info); i++) { + if (!strcmp_l1(cmd_dispatch_info[i].cmd, cmdbuf)) { + func_cb = cmd_dispatch_info[i].cb; + break; + } + } + + if (!func_cb) + fastboot_tx_write_str("FAILunknown command"); + else + func_cb(ep, req); + + if (req->status == 0) { + *cmdbuf = '\0'; + req->actual = 0; + usb_ep_queue(ep, req, 0); + } +} diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index feef9e461..28f215e07 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -219,21 +219,15 @@ static int download_tail(long long int left, int cnt) } /* - * To store last "packet" DFU storage backend requires dfu_write with - * size parameter equal to 0 + * To store last "packet" or write file from buffer to filesystem + * DFU storage backend requires dfu_flush * * This also frees memory malloc'ed by dfu_get_buf(), so no explicit * need fo call dfu_free_buf() is needed. */ - ret = dfu_write(dfu_entity, transfer_buffer, 0, cnt); - if (ret) - error("DFU write failed [%d] cnt: %d", ret, cnt); - ret = dfu_flush(dfu_entity, transfer_buffer, 0, cnt); - if (ret) { + if (ret) error("DFU flush failed!"); - return ret; - } return ret; } diff --git a/drivers/usb/gadget/storage_common.c b/drivers/usb/gadget/storage_common.c index 74300746b..02803df23 100644 --- a/drivers/usb/gadget/storage_common.c +++ b/drivers/usb/gadget/storage_common.c @@ -311,11 +311,7 @@ static struct fsg_lun *fsg_lun_from_dev(struct device *dev) #define DELAYED_STATUS (EP0_BUFSIZE + 999) /* An impossibly large value */ /* Number of buffers we will use. 2 is enough for double-buffering */ -#ifndef CONFIG_CI_UDC #define FSG_NUM_BUFFERS 2 -#else -#define FSG_NUM_BUFFERS 1 /* ci_udc only allows 1 req per ep at present */ -#endif /* Default size of buffer length. */ #define FSG_BUFLEN ((u32)16384) diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index b301e2825..7211c6ad9 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o +obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o # xhci obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 38db18e2c..33e5ea9eb 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -69,6 +69,7 @@ struct fdt_usb { unsigned enabled:1; /* 1 to enable, 0 to disable */ unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ unsigned initialized:1; /* has this port already been initialized? */ + enum usb_init_type init_type; enum dr_mode dr_mode; /* dual role mode */ enum periph_id periph_id;/* peripheral id */ struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */ @@ -237,29 +238,31 @@ int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg) return PORTSC_PSPD(reg); } -/* Put the port into host mode */ -static void set_host_mode(struct fdt_usb *config) +/* Set up VBUS for host/device mode */ +static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init) { /* - * If we are an OTG port, check if remote host is driving VBus and - * bail out in this case. + * If we are an OTG port initializing in host mode, + * check if remote host is driving VBus and bail out in this case. */ - if (config->dr_mode == DR_MODE_OTG && - (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) + if (init == USB_INIT_HOST && + config->dr_mode == DR_MODE_OTG && + (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) { + printf("tegrausb: VBUS input active; not enabling as host\n"); return; + } - /* - * If not driving, we set the GPIO to enable VBUS. We assume - * that the pinmux is set up correctly for this. - */ if (fdt_gpio_isvalid(&config->vbus_gpio)) { + int vbus_value; + fdtdec_setup_gpio(&config->vbus_gpio); - gpio_direction_output(config->vbus_gpio.gpio, - (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? - 0 : 1); - debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio, - (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? - "low" : "high"); + + vbus_value = (init == USB_INIT_HOST) ^ + !!(config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW); + gpio_direction_output(config->vbus_gpio.gpio, vbus_value); + + debug("set_up_vbus: GPIO %d %d\n", config->vbus_gpio.gpio, + vbus_value); } } @@ -293,10 +296,44 @@ static const unsigned *get_pll_timing(void) return timing; } +/* select the PHY to use with a USB controller */ +static void init_phy_mux(struct fdt_usb *config, uint pts, + enum usb_init_type init) +{ + struct usb_ctlr *usbctlr = config->reg; + +#if defined(CONFIG_TEGRA20) + if (config->periph_id == PERIPH_ID_USBD) { + clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, + PTS_UTMI << PTS1_SHIFT); + clrbits_le32(&usbctlr->port_sc1, STS1); + } else { + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, + PTS_UTMI << PTS_SHIFT); + clrbits_le32(&usbctlr->port_sc1, STS); + } +#else + /* Set to Host mode (if applicable) after Controller Reset was done */ + clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, + (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0); + /* + * Select PHY interface after setting host mode. + * For device mode, the ordering requirement is not an issue, since + * only the first USB controller supports device mode, and that USB + * controller can only talk to a UTMI PHY, so the PHY selection is + * already made at reset time, so this write is a no-op. + */ + clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, + pts << PTS_SHIFT); + clrbits_le32(&usbctlr->hostpc1_devlc, STS); +#endif +} + /* set up the UTMI USB controller with the parameters provided */ -static int init_utmi_usb_controller(struct fdt_usb *config) +static int init_utmi_usb_controller(struct fdt_usb *config, + enum usb_init_type init) { - u32 val; + u32 b_sess_valid_mask, val; int loop_count; const unsigned *timing; struct usb_ctlr *usbctlr = config->reg; @@ -314,6 +351,10 @@ static int init_utmi_usb_controller(struct fdt_usb *config) /* Follow the crystal clock disable by >100ns delay */ udelay(1); + b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN); + clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, + (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0); + /* * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP * mux must be switched to actually use a_sess_vld threshold. @@ -485,21 +526,7 @@ static int init_utmi_usb_controller(struct fdt_usb *config) clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); /* Select UTMI parallel interface */ -#if defined(CONFIG_TEGRA20) - if (config->periph_id == PERIPH_ID_USBD) { - clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, - PTS_UTMI << PTS1_SHIFT); - clrbits_le32(&usbctlr->port_sc1, STS1); - } else { - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, - PTS_UTMI << PTS_SHIFT); - clrbits_le32(&usbctlr->port_sc1, STS); - } -#else - clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, - PTS_UTMI << PTS_SHIFT); - clrbits_le32(&usbctlr->hostpc1_devlc, STS); -#endif + init_phy_mux(config, PTS_UTMI, init); /* Deassert power down state */ clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | @@ -529,7 +556,8 @@ static int init_utmi_usb_controller(struct fdt_usb *config) #endif /* set up the ULPI USB controller with the parameters provided */ -static int init_ulpi_usb_controller(struct fdt_usb *config) +static int init_ulpi_usb_controller(struct fdt_usb *config, + enum usb_init_type init) { u32 val; int loop_count; @@ -557,13 +585,7 @@ static int init_ulpi_usb_controller(struct fdt_usb *config) ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); /* Select ULPI parallel interface */ -#if defined(CONFIG_TEGRA20) - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, - PTS_ULPI << PTS_SHIFT); -#else - clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, - PTS_ULPI << PTS_SHIFT); -#endif + init_phy_mux(config, PTS_ULPI, init); /* enable ULPI transceiver */ setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); @@ -612,7 +634,8 @@ static int init_ulpi_usb_controller(struct fdt_usb *config) return 0; } #else -static int init_ulpi_usb_controller(struct fdt_usb *config) +static int init_ulpi_usb_controller(struct fdt_usb *config, + enum usb_init_type init) { printf("No code to set up ULPI controller, please enable" "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); @@ -765,42 +788,66 @@ int ehci_hcd_init(int index, enum usb_init_type init, config = &port[index]; + switch (init) { + case USB_INIT_HOST: + switch (config->dr_mode) { + case DR_MODE_HOST: + case DR_MODE_OTG: + break; + default: + printf("tegrausb: Invalid dr_mode %d for host mode\n", + config->dr_mode); + return -1; + } + break; + case USB_INIT_DEVICE: + if (config->periph_id != PERIPH_ID_USBD) { + printf("tegrausb: Device mode only supported on first USB controller\n"); + return -1; + } + if (!config->utmi) { + printf("tegrausb: Device mode only supported with UTMI PHY\n"); + return -1; + } + switch (config->dr_mode) { + case DR_MODE_DEVICE: + case DR_MODE_OTG: + break; + default: + printf("tegrausb: Invalid dr_mode %d for device mode\n", + config->dr_mode); + return -1; + } + break; + default: + printf("tegrausb: Unknown USB_INIT_* %d\n", init); + return -1; + } + /* skip init, if the port is already initialized */ - if (config->initialized) + if (config->initialized && config->init_type == init) goto success; - if (config->utmi && init_utmi_usb_controller(config)) { + if (config->utmi && init_utmi_usb_controller(config, init)) { printf("tegrausb: Cannot init port %d\n", index); return -1; } - if (config->ulpi && init_ulpi_usb_controller(config)) { + if (config->ulpi && init_ulpi_usb_controller(config, init)) { printf("tegrausb: Cannot init port %d\n", index); return -1; } - set_host_mode(config); + set_up_vbus(config, init); config->initialized = 1; + config->init_type = init; success: usbctlr = config->reg; *hccr = (struct ehci_hccr *)&usbctlr->cap_length; *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd; - if (controller->has_hostpc) { - /* Set to Host mode after Controller Reset was done */ - clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, - USBMODE_CM_HC); - /* Select UTMI parallel interface after setting host mode */ - if (config->utmi) { - clrsetbits_le32((char *)&usbctlr->usb_cmd + - HOSTPC1_DEVLC, PTS_MASK, - PTS_UTMI << PTS_SHIFT); - clrbits_le32((char *)&usbctlr->usb_cmd + - HOSTPC1_DEVLC, STS); - } - } return 0; } diff --git a/drivers/usb/host/ehci-zynq.c b/drivers/usb/host/ehci-zynq.c new file mode 100644 index 000000000..7770d0564 --- /dev/null +++ b/drivers/usb/host/ehci-zynq.c @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2014, Xilinx, Inc + * + * USB Low level initialization(Specific to zynq) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <usb.h> +#include <usb/ehci-fsl.h> +#include <usb/ulpi.h> + +#include "ehci.h" + +#define ZYNQ_USB_USBCMD_RST 0x0000002 +#define ZYNQ_USB_USBCMD_STOP 0x0000000 +#define ZYNQ_USB_NUM_MIO 12 + +/* + * Create the appropriate control structures to manage + * a new EHCI host controller. + */ +int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, + struct ehci_hcor **hcor) +{ + struct usb_ehci *ehci; + struct ulpi_viewport ulpi_vp; + int ret, mio_usb; + /* Used for writing the ULPI data address */ + struct ulpi_regs *ulpi = (struct ulpi_regs *)0; + + if (!index) { + mio_usb = zynq_slcr_get_mio_pin_status("usb0"); + if (mio_usb != ZYNQ_USB_NUM_MIO) { + printf("usb0 wrong num MIO: %d, Index %d\n", mio_usb, + index); + return -1; + } + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0; + } else { + mio_usb = zynq_slcr_get_mio_pin_status("usb1"); + if (mio_usb != ZYNQ_USB_NUM_MIO) { + printf("usb1 wrong num MIO: %d, Index %d\n", mio_usb, + index); + return -1; + } + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1; + } + + *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); + *hcor = (struct ehci_hcor *)((uint32_t) *hccr + + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + + ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint; + ulpi_vp.port_num = 0; + + ret = ulpi_init(&ulpi_vp); + if (ret) { + puts("zynq ULPI viewport init failed\n"); + return -1; + } + + /* ULPI set flags */ + ulpi_write(&ulpi_vp, &ulpi->otg_ctrl, + ULPI_OTG_DP_PULLDOWN | ULPI_OTG_DM_PULLDOWN | + ULPI_OTG_EXTVBUSIND); + ulpi_write(&ulpi_vp, &ulpi->function_ctrl, + ULPI_FC_FULL_SPEED | ULPI_FC_OPMODE_NORMAL | + ULPI_FC_SUSPENDM); + ulpi_write(&ulpi_vp, &ulpi->iface_ctrl, 0); + + /* Set VBus */ + ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); + + return 0; +} + +/* + * Destroy the appropriate control structures corresponding + * the the EHCI host controller. + */ +int ehci_hcd_stop(int index) +{ + struct usb_ehci *ehci; + + if (!index) + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0; + else + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1; + + /* Stop controller */ + writel(ZYNQ_USB_USBCMD_STOP, &ehci->usbcmd); + udelay(1000); + + /* Initiate controller reset */ + writel(ZYNQ_USB_USBCMD_RST, &ehci->usbcmd); + + return 0; +} diff --git a/drivers/usb/musb-new/musb_gadget_ep0.c b/drivers/usb/musb-new/musb_gadget_ep0.c index 6599d386d..8c3b0a145 100644 --- a/drivers/usb/musb-new/musb_gadget_ep0.c +++ b/drivers/usb/musb-new/musb_gadget_ep0.c @@ -576,6 +576,10 @@ static void ep0_txstate(struct musb *musb) } else request = NULL; + /* send it out, triggering a "txpktrdy cleared" irq */ + musb_ep_select(musb->mregs, 0); + musb_writew(regs, MUSB_CSR0, csr); + /* report completions as soon as the fifo's loaded; there's no * win in waiting till this last packet gets acked. (other than * very precise fault reporting, needed by USB TMC; possible with @@ -588,10 +592,6 @@ static void ep0_txstate(struct musb *musb) return; musb->ackpend = 0; } - - /* send it out, triggering a "txpktrdy cleared" irq */ - musb_ep_select(musb->mregs, 0); - musb_writew(regs, MUSB_CSR0, csr); } /* diff --git a/drivers/video/Makefile b/drivers/video/Makefile index c52702924..945f35dc5 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o obj-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o +obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o obj-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o diff --git a/drivers/video/imx25lcdc.c b/drivers/video/imx25lcdc.c new file mode 100644 index 000000000..ef5767bae --- /dev/null +++ b/drivers/video/imx25lcdc.c @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2011 + * Matthias Weisser <weisserm@arcor.de> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * imx25lcdc.c - Graphic interface for i.MX25 lcd controller + */ + +#include <common.h> + +#include <malloc.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <video_fb.h> +#include "videomodes.h" + +/* + * 4MB (at the end of system RAM) + */ +#define VIDEO_MEM_SIZE 0x400000 + +#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */ + +/* + * Graphic Device + */ +static GraphicDevice imx25fb; + +void *video_hw_init(void) +{ + struct lcdc_regs *lcdc = (struct lcdc_regs *)IMX_LCDC_BASE; + struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; + GraphicDevice *pGD = &imx25fb; + char *s; + u32 *videomem; + + memset(pGD, 0, sizeof(GraphicDevice)); + + pGD->gdfIndex = GDF_16BIT_565RGB; + pGD->gdfBytesPP = 2; + pGD->memSize = VIDEO_MEM_SIZE; + pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE; + + videomem = (u32 *)pGD->frameAdrs; + + s = getenv("videomode"); + if (s != NULL) { + struct ctfb_res_modes var_mode; + u32 lsr, lpcr, lhcr, lvcr; + unsigned long div; + int bpp; + + /* Disable all clocks of the LCDC */ + writel(readl(&ccm->cgr0) & ~((1<<7) | (1<<24)), &ccm->cgr0); + writel(readl(&ccm->cgr1) & ~(1<<29), &ccm->cgr1); + + bpp = video_get_params(&var_mode, s); + + if (bpp == 0) { + var_mode.xres = 320; + var_mode.yres = 240; + var_mode.pixclock = 154000; + var_mode.left_margin = 68; + var_mode.right_margin = 20; + var_mode.upper_margin = 4; + var_mode.lower_margin = 18; + var_mode.hsync_len = 40; + var_mode.vsync_len = 6; + var_mode.sync = 0; + var_mode.vmode = 0; + } + + /* Fill memory with white */ + memset(videomem, 0xFF, var_mode.xres * var_mode.yres * 2); + + imx25fb.winSizeX = var_mode.xres; + imx25fb.winSizeY = var_mode.yres; + + /* LCD base clock is 66.6MHZ. We do calculations in kHz */ + div = 66000 / (1000000000L / var_mode.pixclock); + if (div > 63) + div = 63; + if (0 == div) + div = 1; + + lsr = ((var_mode.xres / 16) << 20) | + var_mode.yres; + lpcr = (1 << 31) | + (1 << 30) | + (5 << 25) | + (1 << 23) | + (1 << 22) | + (1 << 19) | + (1 << 7) | + div; + lhcr = (var_mode.right_margin << 0) | + (var_mode.left_margin << 8) | + (var_mode.hsync_len << 26); + + lvcr = (var_mode.lower_margin << 0) | + (var_mode.upper_margin << 8) | + (var_mode.vsync_len << 26); + + writel((uint32_t)videomem, &lcdc->lssar); + writel(lsr, &lcdc->lsr); + writel(var_mode.xres * 2 / 4, &lcdc->lvpwr); + writel(lpcr, &lcdc->lpcr); + writel(lhcr, &lcdc->lhcr); + writel(lvcr, &lcdc->lvcr); + writel(0x00040060, &lcdc->ldcr); + + writel(0xA90300, &lcdc->lpccr); + + /* Ensable all clocks of the LCDC */ + writel(readl(&ccm->cgr0) | ((1<<7) | (1<<24)), &ccm->cgr0); + writel(readl(&ccm->cgr1) | (1<<29), &ccm->cgr1); + } + + return pGD; +} diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 9ab5446c6..2dacba2eb 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -38,8 +38,6 @@ targets += $(patsubst $(obj)/%,%,$(LIB)) $(COBJS) $(LIBOBJS-y) LIBOBJS := $(addprefix $(obj)/,$(LIBOBJS-y)) ELF := $(addprefix $(obj)/,$(ELF)) -gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) - # For PowerPC there's no need to compile standalone applications as a # relocatable executable. The relocation data is not needed, and # also causes the entry point of the standalone application to be @@ -63,7 +61,7 @@ $(LIB): $(LIBOBJS) FORCE quiet_cmd_link_elf = LD $@ cmd_link_elf = $(LD) $(LDFLAGS) -g -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) \ - -o $@ -e $(SYM_PREFIX)$(@F) $< $(LIB) -L$(gcclibdir) -lgcc + -o $@ -e $(SYM_PREFIX)$(@F) $< $(LIB) $(PLATFORM_LIBGCC) $(ELF): $(obj)/%: $(obj)/%.o $(LIB) FORCE $(call if_changed,link_elf) diff --git a/include/android_image.h b/include/android_image.h new file mode 100644 index 000000000..094d60afe --- /dev/null +++ b/include/android_image.h @@ -0,0 +1,69 @@ +/* + * This is from the Android Project, + * Repository: https://android.googlesource.com/platform/bootable/bootloader/legacy + * File: include/boot/bootimg.h + * Commit: 4205b865141ff2e255fe1d3bd16de18e217ef06a + * + * Copyright (C) 2008 The Android Open Source Project + * + * SPDX-License-Identifier: BSD-2-Clause + */ + +#ifndef _ANDROID_IMAGE_H_ +#define _ANDROID_IMAGE_H_ + +#define ANDR_BOOT_MAGIC "ANDROID!" +#define ANDR_BOOT_MAGIC_SIZE 8 +#define ANDR_BOOT_NAME_SIZE 16 +#define ANDR_BOOT_ARGS_SIZE 512 + +struct andr_img_hdr { + char magic[ANDR_BOOT_MAGIC_SIZE]; + + u32 kernel_size; /* size in bytes */ + u32 kernel_addr; /* physical load addr */ + + u32 ramdisk_size; /* size in bytes */ + u32 ramdisk_addr; /* physical load addr */ + + u32 second_size; /* size in bytes */ + u32 second_addr; /* physical load addr */ + + u32 tags_addr; /* physical addr for kernel tags */ + u32 page_size; /* flash page size we assume */ + u32 unused[2]; /* future expansion: should be 0 */ + + char name[ANDR_BOOT_NAME_SIZE]; /* asciiz product name */ + + char cmdline[ANDR_BOOT_ARGS_SIZE]; + + u32 id[8]; /* timestamp / checksum / sha1 / etc */ +}; + +/* + * +-----------------+ + * | boot header | 1 page + * +-----------------+ + * | kernel | n pages + * +-----------------+ + * | ramdisk | m pages + * +-----------------+ + * | second stage | o pages + * +-----------------+ + * + * n = (kernel_size + page_size - 1) / page_size + * m = (ramdisk_size + page_size - 1) / page_size + * o = (second_size + page_size - 1) / page_size + * + * 0. all entities are page_size aligned in flash + * 1. kernel and ramdisk are required (size != 0) + * 2. second is optional (second_size == 0 -> no second) + * 3. load each element (kernel, ramdisk, second) at + * the specified physical address (kernel_addr, etc) + * 4. prepare tags at tag_addr. kernel_args[] is + * appended to the kernel commandline in the tags. + * 5. r0 = 0, r1 = MACHINE_TYPE, r2 = tags_addr + * 6. if second_size != 0: jump to second_addr + * else: jump to kernel_addr + */ +#endif diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index e98b661e3..2850ed8a6 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -65,7 +65,7 @@ typedef struct global_data { struct global_data *new_gd; /* relocated global data */ #ifdef CONFIG_DM - struct device *dm_root; /* Root instance for Driver Model */ + struct udevice *dm_root;/* Root instance for Driver Model */ struct list_head uclass_root; /* Head of core tree */ #endif diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index e325df40d..a6e52a0de 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -86,7 +86,7 @@ enum { GPIOF_UNKNOWN, }; -struct device; +struct udevice; /** * struct struct dm_gpio_ops - Driver model GPIO operations @@ -116,15 +116,15 @@ struct device; * all devices. Be careful not to confuse offset with gpio in the parameters. */ struct dm_gpio_ops { - int (*request)(struct device *dev, unsigned offset, const char *label); - int (*free)(struct device *dev, unsigned offset); - int (*direction_input)(struct device *dev, unsigned offset); - int (*direction_output)(struct device *dev, unsigned offset, + int (*request)(struct udevice *dev, unsigned offset, const char *label); + int (*free)(struct udevice *dev, unsigned offset); + int (*direction_input)(struct udevice *dev, unsigned offset); + int (*direction_output)(struct udevice *dev, unsigned offset, int value); - int (*get_value)(struct device *dev, unsigned offset); - int (*set_value)(struct device *dev, unsigned offset, int value); - int (*get_function)(struct device *dev, unsigned offset); - int (*get_state)(struct device *dev, unsigned offset, char *state, + int (*get_value)(struct udevice *dev, unsigned offset); + int (*set_value)(struct udevice *dev, unsigned offset, int value); + int (*get_function)(struct udevice *dev, unsigned offset); + int (*get_state)(struct udevice *dev, unsigned offset, char *state, int maxlen); }; @@ -166,7 +166,7 @@ struct gpio_dev_priv { * @offset_count: Returns number of GPIOs within this bank * @return bank name of this device */ -const char *gpio_get_bank_info(struct device *dev, int *offset_count); +const char *gpio_get_bank_info(struct udevice *dev, int *offset_count); /** * gpio_lookup_name - Look up a GPIO name and return its details @@ -179,7 +179,7 @@ const char *gpio_get_bank_info(struct device *dev, int *offset_count); * @offsetp: Returns the offset number within this device * @gpiop: Returns the absolute GPIO number, numbered from 0 */ -int gpio_lookup_name(const char *name, struct device **devp, +int gpio_lookup_name(const char *name, struct udevice **devp, unsigned int *offsetp, unsigned int *gpiop); #endif /* _ASM_GENERIC_GPIO_H_ */ diff --git a/include/autoboot.h b/include/autoboot.h new file mode 100644 index 000000000..3a9059a0b --- /dev/null +++ b/include/autoboot.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Add to readline cmdline-editing by + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AUTOBOOT_H +#define __AUTOBOOT_H + +#ifdef CONFIG_BOOTDELAY +/** + * bootdelay_process() - process the bootd delay + * + * Process the boot delay, boot limit, then get the value of either + * bootcmd, failbootcmd or altbootcmd depending on the current state. + * Return this command so it can be executed. + * + * @return command to executed + */ +const char *bootdelay_process(void); + +/** + * autoboot_command() - run the autoboot command + * + * If enabled, run the autoboot command returned from bootdelay_process(). + * Also do the CONFIG_MENUKEY processing if enabled. + * + * @cmd: Command to run + */ +void autoboot_command(const char *cmd); +#else +static inline const char *bootdelay_process(void) +{ + return NULL; +} + +static inline void autoboot_command(const char *s) +{ +} +#endif + +#endif diff --git a/include/bootretry.h b/include/bootretry.h new file mode 100644 index 000000000..2ecd7a48b --- /dev/null +++ b/include/bootretry.h @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BOOTRETRY_H +#define __BOOTRETRY_H + +#ifdef CONFIG_BOOT_RETRY_TIME +/** + * bootretry_tstc_timeout() - ensure we get a keypress before timeout + * + * Check for a keypress repeatedly, resetting the watchdog each time. If a + * keypress is not received within the command timeout, return an error. + * + * @return 0 if a key is received in time, -ETIMEDOUT if not + */ +int bootretry_tstc_timeout(void); + +/** + * bootretry_init_cmd_timeout() - set up command timeout + * + * Get the required command timeout from the environment. + */ +void bootretry_init_cmd_timeout(void); + +/** + * bootretry_reset_cmd_timeout() - reset command timeout + * + * Reset the command timeout so that the user has a fresh start. This is + * typically used when input is received from the user. + */ +void bootretry_reset_cmd_timeout(void); + +/** bootretry_dont_retry() - Indicate that we should not retry the boot */ +void bootretry_dont_retry(void); +#else +static inline int bootretry_tstc_timeout(void) +{ + return 0; +} + +static inline void bootretry_init_cmd_timeout(void) +{ +} + +static inline void bootretry_reset_cmd_timeout(void) +{ +} + +static inline void bootretry_dont_retry(void) +{ +} + +#endif + +#endif diff --git a/include/cli.h b/include/cli.h new file mode 100644 index 000000000..699426252 --- /dev/null +++ b/include/cli.h @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2014 Google, Inc + * Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CLI_H +#define __CLI_H + +/** + * Go into the command loop + * + * This will return if we get a timeout waiting for a command. See + * CONFIG_BOOT_RETRY_TIME. + */ +void cli_simple_loop(void); + +/** + * cli_simple_run_command() - Execute a command with the simple CLI + * + * @cmd: String containing the command to execute + * @flag Flag value - see CMD_FLAG_... + * @return 1 - command executed, repeatable + * 0 - command executed but not repeatable, interrupted commands are + * always considered not repeatable + * -1 - not executed (unrecognized, bootd recursion or too many args) + * (If cmd is NULL or "" or longer than CONFIG_SYS_CBSIZE-1 it is + * considered unrecognized) + */ +int cli_simple_run_command(const char *cmd, int flag); + +/** + * cli_simple_run_command_list() - Execute a list of command + * + * The commands should be separated by ; or \n and will be executed + * by the built-in parser. + * + * This function cannot take a const char * for the command, since if it + * finds newlines in the string, it replaces them with \0. + * + * @param cmd String containing list of commands + * @param flag Execution flags (CMD_FLAG_...) + * @return 0 on success, or != 0 on error. + */ +int cli_simple_run_command_list(char *cmd, int flag); + +/** + * cli_readline() - read a line into the console_buffer + * + * This is a convenience function which calls cli_readline_into_buffer(). + * + * @prompt: Prompt to display + * @return command line length excluding terminator, or -ve on error + */ +int cli_readline(const char *const prompt); + +/** + * readline_into_buffer() - read a line into a buffer + * + * Display the prompt, then read a command line into @buffer. The + * maximum line length is CONFIG_SYS_CBSIZE including a \0 terminator, which + * will always be added. + * + * The command is echoed as it is typed. Command editing is supported if + * CONFIG_CMDLINE_EDITING is defined. Tab auto-complete is supported if + * CONFIG_AUTO_COMPLETE is defined. If CONFIG_BOOT_RETRY_TIME is defined, + * then a timeout will be applied. + * + * If CONFIG_BOOT_RETRY_TIME is defined and retry_time >= 0, + * time out when time goes past endtime (timebase time in ticks). + * + * @prompt: Prompt to display + * @buffer: Place to put the line that is entered + * @timeout: Timeout in milliseconds, 0 if none + * @return command line length excluding terminator, or -ve on error: of the + * timeout is exceeded (either CONFIG_BOOT_RETRY_TIME or the timeout + * parameter), then -2 is returned. If a break is detected (Ctrl-C) then + * -1 is returned. + */ +int cli_readline_into_buffer(const char *const prompt, char *buffer, + int timeout); + +/** + * parse_line() - split a command line down into separate arguments + * + * The argv[] array is filled with pointers into @line, and each argument + * is terminated by \0 (i.e. @line is changed in the process unless there + * is only one argument). + * + * #argv is terminated by a NULL after the last argument pointer. + * + * At most CONFIG_SYS_MAXARGS arguments are permited - if there are more + * than that then an error is printed, and this function returns + * CONFIG_SYS_MAXARGS, with argv[] set up to that point. + * + * @line: Command line to parse + * @args: Array to hold arguments + * @return number of arguments + */ +int cli_simple_parse_line(char *line, char *argv[]); + +#ifdef CONFIG_OF_CONTROL +/** + * cli_process_fdt() - process the boot command from the FDT + * + * If bootcmmd is defined in the /config node of the FDT, we use that + * as the boot command. Further, if bootsecure is set to 1 (in the same + * node) then we return true, indicating that the command should be executed + * as securely as possible, avoiding the CLI parser. + * + * @cmdp: On entry, the command that will be executed if the FDT does + * not have a command. Returns the command to execute after + * checking the FDT. + * @return true to execute securely, else false + */ +bool cli_process_fdt(const char **cmdp); + +/** cli_secure_boot_cmd() - execute a command as securely as possible + * + * This avoids using the parser, thus executing the command with the + * smallest amount of code. Parameters are not supported. + */ +void cli_secure_boot_cmd(const char *cmd); +#else +static inline bool cli_process_fdt(const char **cmdp) +{ + return false; +} + +static inline void cli_secure_boot_cmd(const char *cmd) +{ +} +#endif /* CONFIG_OF_CONTROL */ + +/** + * Go into the command loop + * + * This will return if we get a timeout waiting for a command, but only for + * the simple parser (not hush). See CONFIG_BOOT_RETRY_TIME. + */ +void cli_loop(void); + +/** Set up the command line interpreter ready for action */ +void cli_init(void); + +#define endtick(seconds) (get_ticks() + (uint64_t)(seconds) * get_tbclk()) + +#endif diff --git a/include/hush.h b/include/cli_hush.h index 595303a65..4951eef57 100644 --- a/include/hush.h +++ b/include/cli_hush.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _HUSH_H_ -#define _HUSH_H_ +#ifndef _CLI_HUSH_H_ +#define _CLI_HUSH_H_ #define FLAG_EXIT_FROM_LOOP 1 #define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */ diff --git a/include/common.h b/include/common.h index 13e5dc74e..3473ee50e 100644 --- a/include/common.h +++ b/include/common.h @@ -286,12 +286,6 @@ int run_command(const char *cmd, int flag); * @return 0 on success, or != 0 on error. */ int run_command_list(const char *cmd, int len, int flag); -int readline (const char *const prompt); -int readline_into_buffer(const char *const prompt, char *buffer, - int timeout); -int parse_line (char *, char *[]); -void init_cmd_timeout(void); -void reset_cmd_timeout(void); extern char console_buffer[]; /* arch/$(ARCH)/lib/board.c */ @@ -305,6 +299,7 @@ extern ulong monitor_flash_len; int mac_read_from_eeprom(void); extern u8 __dtb_dt_begin[]; /* embedded device tree blob */ int set_cpu_clk_info(void); +int mdm_init(void); #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void); #else @@ -836,7 +831,7 @@ int ctrlc (void); int had_ctrlc (void); /* have we had a Control-C since last clear? */ void clear_ctrlc (void); /* clear the Control-C condition */ int disable_ctrlc (int); /* 1 to disable, 0 to enable Control-C detect */ - +int confirm_yesno(void); /* 1 if input is "y", "Y", "yes" or "YES" */ /* * STDIO based functions (can always be used) */ diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index 2822a08c0..fd6c9763d 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -219,6 +219,7 @@ #define CONFIG_CMD_ELF #define CONFIG_CMD_DATE #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMD_MII #define CONFIG_CMD_BEDBUG diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h index 036396c78..1ab2b3d51 100644 --- a/include/configs/MVBC_P.h +++ b/include/configs/MVBC_P.h @@ -89,6 +89,7 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_PCI #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMD_I2C #undef CONFIG_WATCHDOG diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 27c2fa011..1ee4d7cc3 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -267,6 +267,7 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_I2C #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMD_USB #define CONFIG_DOS_PARTITION diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h index ad15506fa..27f730d84 100644 --- a/include/configs/MVSMR.h +++ b/include/configs/MVSMR.h @@ -74,6 +74,7 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_DHCP #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_NET diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 7849b222b..2782e559f 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -222,6 +222,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMD_I2C #undef CONFIG_CMD_LOADB #undef CONFIG_CMD_LOADS diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index 17a2da034..8bb932ce8 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -48,6 +48,7 @@ #define CONFIG_USE_ARCH_MEMCPY #define CONFIG_TMU_TIMER #define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_GENERIC_BOARD /* STACK */ #define CONFIG_SYS_INIT_SP_ADDR 0xE8083000 diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index d875753a6..fa64a688a 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -88,6 +88,7 @@ #define CONFIG_CMD_LOADS #define CONFIG_CMD_LOADB #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_HUSH_PARSER diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index ccfda71c9..341b21df2 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -22,7 +22,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ #define CONFIG_AT91SAM9M10G45EK -#define CONFIG_AT91FAMILY #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS @@ -34,6 +33,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO @@ -115,6 +116,20 @@ #endif +/* MMC */ +#define CONFIG_CMD_MMC + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#endif + +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* Ethernet */ #define CONFIG_MACB #define CONFIG_RMII @@ -126,7 +141,6 @@ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_ATMEL #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 -#define CONFIG_DOS_PARTITION #define CONFIG_USB_STORAGE #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ @@ -134,6 +148,7 @@ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END 0x23e00000 +#ifdef CONFIG_SYS_USE_NANDFLASH /* bootstrap + u-boot + env in nandflash */ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0xc0000 @@ -149,6 +164,24 @@ "256k(env),256k(env_redundant),256k(spare)," \ "512k(dtb),6M(kernel)ro,-(rootfs) " \ "root=/dev/mtdblock7 rw rootfstype=jffs2" +#elif CONFIG_SYS_USE_MMC +/* bootstrap + u-boot + env + linux in mmc */ +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE 0 +#define FAT_ENV_PART 1 +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_ENV_IS_IN_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_ENV_SIZE 0x4000 + +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "mtdparts=atmel_nand:" \ + "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \ + "root=/dev/mmcblk0p2 rw rootwait" +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \ + "fatload mmc 0:1 0x72000000 zImage; " \ + "bootz 0x72000000 - 0x71000000" +#endif #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index e23549d44..9b0e588c6 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -18,9 +18,6 @@ #define CONFIG_SYS_TEXT_BASE 0x26f00000 -#define CONFIG_ARM926EJS -#define CONFIG_AT91FAMILY - /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index f0a6757ff..b1d4baaff 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -18,7 +18,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define CONFIG_AT91SAM9X5EK -#define CONFIG_AT91FAMILY #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS @@ -30,6 +29,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h index 5228ba6ef..2f5a6609b 100644 --- a/include/configs/balloon3.h +++ b/include/configs/balloon3.h @@ -54,6 +54,7 @@ #undef CONFIG_CMD_IMLS #define CONFIG_CMD_USB #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK #undef CONFIG_LCD /* diff --git a/include/configs/beaver.h b/include/configs/beaver.h index df9a98bca..9ff089e67 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -21,6 +21,9 @@ #include "tegra30-common.h" +/* VDD core PMIC */ +#define CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 + /* Enable fdt support for Beaver. Flash the image in u-boot-dtb.bin */ #define CONFIG_DEFAULT_DEVICE_TREE tegra30-beaver #define CONFIG_OF_CONTROL diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index e15b52737..59f429cf5 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -21,6 +21,9 @@ #include "tegra30-common.h" +/* VDD core PMIC */ +#define CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3 + /* Enable fdt support for Cardhu. Flash the image in u-boot-dtb.bin */ #define CONFIG_DEFAULT_DEVICE_TREE tegra30-cardhu #define CONFIG_OF_CONTROL diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h new file mode 100644 index 000000000..db0409534 --- /dev/null +++ b/include/configs/cm_t54.h @@ -0,0 +1,149 @@ +/* + * Config file for Compulab CM-T54 board + * + * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ + * + * Author: Dmitry Lifshitz <lifshitz@compulab.co.il> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_CM_T54_H +#define __CONFIG_CM_T54_H + +#define CONFIG_CM_T54 +#define CONFIG_DRAM_2G + +#include <configs/ti_omap5_common.h> + +#undef CONFIG_MISC_INIT_R +#undef CONFIG_SPL_OS_BOOT + +/* Device Tree defines */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + +/* EEPROM related defines */ +#define CONFIG_SYS_I2C_OMAP34XX +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* Enable SD/MMC CD and WP GPIOs */ +#define OMAP_HSMMC_USE_GPIO + +/* UART setup */ +#define CONFIG_CONS_INDEX 4 +#define CONFIG_SYS_NS16550_COM4 UART4_BASE +#define CONFIG_BAUDRATE 115200 + +/* SD/MMC RAW boot */ +#undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR +#undef CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* 0x40000 - 256 KB */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 /* 384 KB */ + +/* MMC ENV related defines */ +#undef CONFIG_ENV_OFFSET +#undef CONFIG_ENV_SIZE + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ +#define CONFIG_SYS_MMC_ENV_PART 0 +#define CONFIG_ENV_OFFSET 0xc0000 /* (in bytes) 768 KB */ +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_CMD_SAVEENV + +/* Enhance our eMMC support / experience. */ +#define CONFIG_HSMMC2_8BIT +#define CONFIG_SUPPORT_EMMC_BOOT + +/* USB UHH support options */ +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 76 /* HSIC2 HUB #RESET */ +#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 83 /* HSIC3 ETH #RESET */ + +/* Enabled commands */ +#define CONFIG_CMD_DHCP /* DHCP Support */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_PING + +/* USB Networking options */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_RNDIS +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 + +/* Max time to hold reset on this board, see doc/README.omap-reset-time */ +#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296 + +/* + * Miscellaneous configurable options + */ +#undef CONFIG_SYS_AUTOLOAD +#undef CONFIG_SYS_PROMPT +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND +#undef CONFIG_BOOTDELAY + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_SYS_AUTOLOAD "no" +#define CONFIG_SYS_PROMPT "CM-T54 # " + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "baudrate=115200\0" \ + "bootdelay=3\0" \ + "autoload=no\0" \ + "bootscr=bootscr.img\0" \ + "fdtfile=omap5-sbc-t54.dtb\0" \ + "kernel=zImage-cm-t54\0" \ + "ramdisk=ramdisk-cm-t54.img\0" \ + "console=ttyO3\0" \ + "ramdisksize=16384\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk1p2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=${mmcroot} rw rootwait\0" \ + "ramroot=/dev/ram0\0" \ + "ramargs=setenv bootargs console=${console} " \ + "root=${ramroot} ramdisk_size=${ramdisksize} rw\0" \ + "mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \ + "mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \ + "mmcloadramdisk=load mmc ${mmcdev} ${rdaddr} ${ramdisk}\0" \ + "mmcloadbootscript=load mmc ${mmcdev} ${loadaddr} ${bootsrc}\0" \ + "mmcbootscript=echo Running bootscript from mmc${mmcdev}...; " \ + "source ${loadaddr}\0" \ + "mmcbootlinux=echo Booting from mmc${mmcdev} ...; " \ + "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ + "mmcboot=if mmc dev ${mmcdev} && mmc rescan; then " \ + "if run mmcloadbootscript; " \ + "then run mmcbootscript; " \ + "fi; " \ + "if run mmcloadkernel; then " \ + "if run mmcloadfdt; then " \ + "if run mmcloadramdisk; then " \ + "run ramargs; " \ + "run mmcbootlinux; " \ + "fi; " \ + "run mmcargs; " \ + "setenv rdaddr - ; " \ + "run mmcbootlinux; " \ + "fi; " \ + "fi; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "bootcmd=run mmcboot || setenv mmcdev 1; setenv mmcroot /dev/mmcblk0p2; run mmcboot;" + +#endif /* __CONFIG_CM_T54_H */ diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index d1d732f21..a1a63a018 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -167,6 +167,7 @@ #define CONFIG_CMD_ECHO #undef CONFIG_CMD_FLASH #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMD_GPIO #define CONFIG_CMD_IMI #undef CONFIG_CMD_IMLS diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 959e188d9..6171060e9 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -27,15 +27,12 @@ #define CONFIG_SYS_TEXT_BASE 0x73f00000 -#define CONFIG_AT91_LEGACY #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_AT91FAMILY - #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h index 39f706238..1feaefd14 100644 --- a/include/configs/cpu9260.h +++ b/include/configs/cpu9260.h @@ -32,7 +32,6 @@ #include <asm/arch/hardware.h> -#define CONFIG_AT91FAMILY #define CONFIG_ARCH_CPU_INIT #define CONFIG_DISPLAY_CPUINFO #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 860a11dd2..b27940995 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -386,6 +386,7 @@ #define CONFIG_SPL_STACK 0x8001ff00 #define CONFIG_SPL_TEXT_BASE 0x80000000 #define CONFIG_SPL_MAX_FOOTPRINT 32768 +#define CONFIG_SPL_PAD_TO 32768 #endif /* Load U-Boot Image From MMC */ diff --git a/include/configs/draco.h b/include/configs/draco.h new file mode 100644 index 000000000..a2438d883 --- /dev/null +++ b/include/configs/draco.h @@ -0,0 +1,92 @@ +/* + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_DRACO_H +#define __CONFIG_DRACO_H + +#define CONFIG_SIEMENS_DRACO +#define MACH_TYPE_DRACO 4314 +#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_DRACO + +#include "siemens-am33x-common.h" + +#define CONFIG_SYS_MPUCLK 275 +#define DDR_PLL_FREQ 303 +#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC + +#define BOARD_DFU_BUTTON_GPIO 27 +#define BOARD_DFU_BUTTON_LED 64 /* red LED */ +#define BOARD_STATUS_LED 103 /* green LED */ +#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ + +#undef CONFIG_DOS_PARTITION +#undef CONFIG_CMD_FAT + + + /* Physical Memory Map */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define EEPROM_ADDR_DDR3 0x90 +#define EEPROM_ADDR_CHIP 0x120 + +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 + +#undef CONFIG_SPL_NET_SUPPORT +#undef CONFIG_SPL_NET_VCI_STRING +#undef CONFIG_SPL_ETH_SUPPORT + +#undef CONFIG_MII +#undef CONFIG_PHY_GIGE +#define CONFIG_PHY_SMSC + +#define CONFIG_FACTORYSET + +/* Watchdog */ +#define CONFIG_OMAP_WATCHDOG + +#ifndef CONFIG_SPL_BUILD + +/* Default env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "nand_img_size=0x400000\0" \ + "optargs=\0" \ + CONFIG_COMMON_ENV_SETTINGS + +#ifndef CONFIG_RESTORE_FLASH +/* set to negative value for no autoboot */ +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_BOOTCOMMAND \ +"if dfubutton; then " \ + "run dfu_start; " \ + "reset; " \ +"fi;" \ +"run nand_boot;" \ +"reset;" + + +#else +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "dhcp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +#endif +#endif /* CONFIG_SPL_BUILD */ +#endif /* ! __CONFIG_DRACO_H */ diff --git a/include/configs/duovero.h b/include/configs/duovero.h new file mode 100644 index 000000000..e68f415c2 --- /dev/null +++ b/include/configs/duovero.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright: 2013 + * Gumstix, Inc - http://www.gumstix.com + * Maintainer: Ash Charles <ash@gumstix.com> + * + * Configuration settings for the Gumstix DuoVero board. + * See omap4_common.h for OMAP4 common part + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_DUOVERO_H +#define __CONFIG_DUOVERO_H + +/* + * High Level Configuration Options + */ +#define CONFIG_DUOVERO +#define MACH_TYPE_OMAP4_DUOVERO 4097 /* Until the next sync */ +#define CONFIG_MACH_TYPE MACH_TYPE_OMAP4_DUOVERO + +#include <configs/ti_omap4_common.h> + +#undef CONFIG_SPL_OS_BOOT + +#undef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS + +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "duovero # " + +/* USB UHH support options */ +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 + +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1 +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62 + +#define CONFIG_SYS_ENABLE_PADS_ALL + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NET + +#define CONFIG_SMC911X +#define CONFIG_SMC911X_32_BIT +#define CONFIG_SMC911X_BASE 0x2C000000 + +/* GPIO */ +#define CONFIG_CMD_GPIO + +/* ENV related config options */ +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#endif /* __CONFIG_DUOVERO_H */ diff --git a/include/configs/dxr2.h b/include/configs/dxr2.h index 75f7812e7..76e6cac77 100644 --- a/include/configs/dxr2.h +++ b/include/configs/dxr2.h @@ -20,12 +20,12 @@ #include "siemens-am33x-common.h" #define CONFIG_SYS_MPUCLK 275 -#define DXR2_IOCTRL_VAL 0x18b #define DDR_PLL_FREQ 303 #undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC #define BOARD_DFU_BUTTON_GPIO 27 -#define BOARD_DFU_BUTTON_LED 64 +#define BOARD_DFU_BUTTON_LED 64 /* red LED */ +#define BOARD_STATUS_LED 103 /* green LED */ #define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ #undef CONFIG_DOS_PARTITION diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h new file mode 100644 index 000000000..eb91c44e3 --- /dev/null +++ b/include/configs/embestmx6boards.h @@ -0,0 +1,336 @@ +/* + * Copyright (C) 2014 Eukréa Electromatique + * Author: Eric Bénard <eric@eukrea.com> + * + * Configuration settings for the Embest RIoTboard + * + * based on mx6*sabre*.h which are : + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __RIOTBOARD_CONFIG_H +#define __RIOTBOARD_CONFIG_H + +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> + +#include "mx6_common.h" +#include <linux/sizes.h> + +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CONSOLE_DEV "ttymxc0" +#define CONFIG_MMCROOT "/dev/mmcblk1p2" + +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +#define CONFIG_MX6 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART + +#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 4 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SST +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(2, 30) << 8)) +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_SETEXPR +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 1 + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#ifdef CONFIG_SUPPORT_EMMC_BOOT +#define EMMC_ENV \ + "emmcdev=2\0" \ + "update_emmc_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "if mmc dev ${emmcdev}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" +#else +#define EMMC_ENV "" +#endif + +#ifdef CONFIG_CMD_SF +#define SF_ENV \ + "update_spi_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if ${get_cmd} ${update_spi_firmware_filename}; then " \ + "if sf probe; then " \ + "sf erase 0 0xc0000; " \ + "sf write ${loadaddr} 0x400 ${filesize}; " \ + "fi; " \ + "fi\0" +#else +#define SF_ENV "" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x18000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "console=" CONFIG_CONSOLE_DEV "\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=1\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "update_sd_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if mmc dev ${mmcdev}; then " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" \ + EMMC_ENV \ + SF_ENV \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE (128 * 1024) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +#if defined(CONFIG_ENV_IS_IN_MMC) +/* RiOTboard */ +#define CONFIG_DEFAULT_FDT_FILE "imx6s-riotboard.dtb" +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */ +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +/* MarSBoard */ +#define CONFIG_DEFAULT_FDT_FILE "imx6q-marsboard.dtb" +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_SECT_SIZE (8 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +#define CONFIG_OF_LIBFDT + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +/* Framebuffer */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + +#endif /* __RIOTBOARD_CONFIG_H */ diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 480d8678c..c81fc44b1 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -23,8 +23,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 /* CPU information */ -#define CONFIG_ARM926EJS -#define CONFIG_AT91FAMILY #define CONFIG_DISPLAY_CPUINFO /* Display at console. */ #define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h index 414db420d..5a9b1b42d 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-dt.h @@ -288,4 +288,6 @@ #define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_GPIO + #endif /* __CONFIG_H */ diff --git a/include/configs/grsim.h b/include/configs/grsim.h index 556c749f9..1e089a9bf 100644 --- a/include/configs/grsim.h +++ b/include/configs/grsim.h @@ -53,6 +53,7 @@ #define CONFIG_CMD_DIAG #define CONFIG_CMD_ECHO /* echo arguments */ #define CONFIG_CMD_FPGA /* FPGA configuration Support */ +#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMD_IRQ #define CONFIG_CMD_ITEST /* Integer (and string) test */ #define CONFIG_CMD_LOADB /* loadb */ diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h index 8be98983c..66194a8ff 100644 --- a/include/configs/grsim_leon2.h +++ b/include/configs/grsim_leon2.h @@ -51,6 +51,7 @@ #define CONFIG_CMD_DIAG #define CONFIG_CMD_ECHO /* echo arguments */ #define CONFIG_CMD_FPGA /* FPGA configuration Support */ +#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMD_IRQ #define CONFIG_CMD_ITEST /* Integer (and string) test */ #define CONFIG_CMD_LOADB /* loadb */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 33983907f..cd554957d 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -24,6 +24,8 @@ #define CONFIG_SERIAL_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) @@ -136,6 +138,8 @@ #define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CONFIG_POWER_LTC3676 +#define CONFIG_POWER_LTC3676_I2C_ADDR 0x3c /* Various command support */ #include <config_cmd_default.h> @@ -190,6 +194,22 @@ #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP #define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 1200 +/* Framebuffer and LCD */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_CMD_HDMIDETECT +#define CONFIG_CONSOLE_MUX +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + /* serial console (ttymxc1,115200) */ #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/highbank.h b/include/configs/highbank.h index a6202cfab..da1c837cc 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -13,6 +13,7 @@ #define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_OF_BOARD_SETUP #define CONFIG_FIT diff --git a/include/configs/hummingboard.h b/include/configs/hummingboard.h index 289552334..34dbdce1a 100644 --- a/include/configs/hummingboard.h +++ b/include/configs/hummingboard.h @@ -27,6 +27,8 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) diff --git a/include/configs/iocon.h b/include/configs/iocon.h index f36c2a350..79c4736bc 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -62,7 +62,8 @@ * Commands additional to the ones defined in amcc-common.h */ #define CONFIG_CMD_CACHE -#define CONFIG_CMD_FPGAD +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK #undef CONFIG_CMD_EEPROM /* diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 9bb8f342b..dde73298f 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -165,6 +165,7 @@ #define CONFIG_CMD_EEPROM /* U-Boot general configuration */ +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_PROMPT "K2HK EVM # " #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_PBSIZE 2048 diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 90e2d7a03..6795f28a1 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -31,16 +31,22 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_NFS #define CONFIG_CMD_BOOTZ - -#if defined(CONFIG_SYS_USE_BOOT_NORFLASH) -#define CONFIG_CMD_FLASH -#define CONFIG_SYS_TEXT_BASE 0x00000000 -#else -/* SPI flash boot is default. */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT #define CONFIG_CMD_SF #define CONFIG_CMD_SPI + +#define CONFIG_FAT_WRITE +#define CONFIG_EXT4_WRITE + #define CONFIG_SYS_TEXT_BASE 0xE6304000 -#endif +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_SYS_GENERIC_BOARD + +/* Support File sytems */ +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT + #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS @@ -61,8 +67,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_USE_ARCH_MEMSET -#define CONFIG_USE_ARCH_MEMCPY #define CONFIG_TMU_TIMER /* STACK */ @@ -86,7 +90,6 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF0 -#define SCIF0_BASE 0xe6e60000 #undef CONFIG_SYS_CONSOLE_INFO_QUIET #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE @@ -109,29 +112,6 @@ #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* FLASH */ -#if defined(CONFIG_SYS_USE_BOOT_NORFLASH) -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } -#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) } -#define CONFIG_SYS_FLASH_ERASE_TOUT 3000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 3000 -#define CONFIG_SYS_FLASH_LOCK_TOUT 3000 -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000 -/* ENV setting */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ - CONFIG_SYS_MONITOR_LEN) - -#else /* CONFIG_SYS_USE_BOOT_NORFLASH */ - #define CONFIG_SYS_NO_FLASH #define CONFIG_SPI #define CONFIG_SH_QSPI @@ -142,8 +122,6 @@ #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_ADDR 0xC0000 -#endif /* CONFIG_SYS_USE_BOOT_NORFLASH */ - /* Common ENV setting */ #define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_SECT_SIZE (256 * 1024) @@ -166,8 +144,9 @@ #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ -#define CONFIG_SYS_CLK_FREQ 10000000 -#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) #define CONFIG_SH_SCIF_CLK_FREQ 14745600 #define CONFIG_SYS_TMU_CLK_DIV 4 @@ -189,4 +168,10 @@ #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ +/* USB */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_RMOBILE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_USB_STORAGE + #endif /* __KOELSCH_H */ diff --git a/include/configs/kwb.h b/include/configs/kwb.h index 0f631c0f6..0860434f2 100644 --- a/include/configs/kwb.h +++ b/include/configs/kwb.h @@ -109,7 +109,7 @@ #undef CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_MMC_ENV_PART 2 #define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) diff --git a/include/configs/lager.h b/include/configs/lager.h index b420e45e6..f39a788e9 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -16,8 +16,6 @@ #define CONFIG_RMOBILE #define CONFIG_RMOBILE_BOARD_STRING "Lager" #define CONFIG_SH_GPIO_PFC -#define MACH_TYPE_LAGER 4538 -#define CONFIG_MACH_TYPE MACH_TYPE_LAGER #include <asm/arch/rmobile.h> @@ -34,15 +32,21 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_NFS #define CONFIG_CMD_BOOTZ - -#if defined(CONFIG_SYS_USE_BOOT_NORFLASH) -#define CONFIG_CMD_FLASH -#define CONFIG_SYS_TEXT_BASE 0x00000000 -#else +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT #define CONFIG_CMD_SF #define CONFIG_CMD_SPI + +#define CONFIG_FAT_WRITE +#define CONFIG_EXT4_WRITE + #define CONFIG_SYS_TEXT_BASE 0xE8080000 -#endif +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_SYS_GENERIC_BOARD + +/* Support File sytems */ +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS @@ -64,8 +68,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_USE_ARCH_MEMSET -#define CONFIG_USE_ARCH_MEMCPY #define CONFIG_TMU_TIMER /* STACK */ @@ -89,7 +91,6 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF0 -#define SCIF0_BASE 0xe6e60000 #undef CONFIG_SYS_CONSOLE_INFO_QUIET #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE @@ -111,31 +112,6 @@ #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) -#if defined(CONFIG_SYS_USE_BOOT_NORFLASH) -/* USE NOR FLASH */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } -#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) } -#define CONFIG_SYS_FLASH_ERASE_TOUT 3000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 3000 -#define CONFIG_SYS_FLASH_LOCK_TOUT 3000 -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000 - -/* ENV setting */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ - CONFIG_SYS_MONITOR_LEN) - -#else /* CONFIG_SYS_USE_BOOT_NORFLASH */ - /* USE SPI */ #define CONFIG_SPI #define CONFIG_SPI_FLASH_BAR @@ -147,7 +123,6 @@ /* ENV setting */ #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_ADDR 0xC0000 -#endif /* Common ENV setting */ #define CONFIG_ENV_OVERWRITE @@ -186,9 +161,10 @@ #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ /* Board Clock */ -#define CONFIG_BASE_CLK_FREQ 20000000u -#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */ -#define CONFIG_PLL1_CLK_FREQ (CONFIG_BASE_CLK_FREQ * 156 / 2) +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ +#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) #define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) #define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) #define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) @@ -196,4 +172,10 @@ #define CONFIG_SYS_TMU_CLK_DIV 4 +/* USB */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_RMOBILE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 4 +#define CONFIG_USB_STORAGE + #endif /* __LAGER_H */ diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 96a889fe8..f5f49613c 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -66,6 +66,7 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_SPI #define CONFIG_CMD_USB +#define CONFIG_CMD_FS_GENERIC #define CONFIG_DOS_PARTITION #define CONFIG_EFI_PARTITION @@ -109,20 +110,41 @@ #define CONFIG_LOADADDR 0x00800000 #define CONFIG_BOOTCOMMAND "run bootcmd_${bootsource}" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/sda2" + +#if defined(CONFIG_LSXHL) +#define CONFIG_FDTFILE "kirkwood-lsxhl.dtb" +#elif defined(CONFIG_LSCHLV2) +#define CONFIG_FDTFILE "kirkwood-lschlv2.dtb" +#else +#error "Unsupported board" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ - "bootsource=hdd\0" \ + "bootsource=legacy\0" \ "hdpart=0:1\0" \ - "bootcmd_net=bootp 0x00100000 uImage " \ - "&& tftpboot 0x00800000 uInitrd " \ + "kernel_addr=0x00800000\0" \ + "ramdisk_addr=0x01000000\0" \ + "fdt_addr=0x01ff0000\0" \ + "bootcmd_legacy=ide reset " \ + "&& load ide ${hdpart} 0x00100000 /uImage.buffalo " \ + "&& load ide ${hdpart} 0x00800000 /initrd.buffalo " \ "&& bootm 0x00100000 0x00800000\0" \ + "bootcmd_net=bootp ${kernel_addr} uImage " \ + "&& tftpboot ${ramdisk_addr} uInitrd " \ + "&& tftpboot ${fdt_addr} " CONFIG_FDTFILE " " \ + "&& bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ "bootcmd_hdd=ide reset " \ - "&& ext2load ide ${hdpart} 0x00100000 /uImage " \ - "&& ext2load ide ${hdpart} 0x00800000 /uInitrd " \ - "&& bootm 0x00100000 0x00800000\0" \ + "&& load ide ${hdpart} ${kernel_addr} /uImage " \ + "&& load ide ${hdpart} ${ramdisk_addr} /uInitrd " \ + "&& load ide ${hdpart} ${fdt_addr} " \ + "/" CONFIG_FDTFILE " " \ + "&& bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ "bootcmd_usb=usb start " \ - "&& fatload usb 0:1 0x00100000 /uImage " \ - "&& fatload usb 0:1 0x00800000 /uInitrd " \ - "&& bootm 0x00100000 0x00800000\0" \ + "&& load usb 0:1 ${kernel_addr} /uImage " \ + "&& load usb 0:1 ${ramdisk_addr} /uInitrd " \ + "&& load usb 0:1 ${fdt_addr} " \ + "/" CONFIG_FDTFILE " " \ + "&& bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ "bootcmd_rescue=run config_nc_dhcp; run nc\0" \ "eraseenv=sf probe 0 " \ "&& sf erase " __stringify(CONFIG_ENV_OFFSET) \ @@ -161,6 +183,7 @@ #undef CONFIG_SYS_IDE_MAXDEVICE #define CONFIG_SYS_IDE_MAXDEVICE 1 #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_64BIT_LBA #endif #endif /* _CONFIG_LSXL_H */ diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index bb1fa44d8..3e387c42d 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -7,7 +7,6 @@ #ifndef __CONFIGS_M28EVK_H__ #define __CONFIGS_M28EVK_H__ - /* System configurations */ #define CONFIG_MX28 /* i.MX28 SoC */ #define MACH_TYPE_M28EVK 3613 diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h index e7afd07b9..01e395a49 100644 --- a/include/configs/mt_ventoux.h +++ b/include/configs/mt_ventoux.h @@ -49,6 +49,7 @@ * FPGA */ #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_FPGA #define CONFIG_FPGA_XILINX #define CONFIG_FPGA_SPARTAN3 diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 797a637bf..134d6804b 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -23,6 +23,8 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 3f0d80ac6..5bbae8cf7 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -23,6 +23,8 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_OF_LIBFDT /* Size of malloc() pool */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 5859f360e..12d79b455 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -22,6 +22,8 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG +#define CONFIG_SYS_GENERIC_BOARD + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index a04e7c7a3..3da0ef4bd 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -23,6 +23,8 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 7a2c172d4..e59a3b4b0 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -25,6 +25,8 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 5d02d23ec..0fa6573c7 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -47,6 +47,7 @@ #define CONFIG_VIDEO_BMP_LOGO #define CONFIG_IPUV3_CLK 260000000 #define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP #define CONFIG_CMD_PCI #ifdef CONFIG_CMD_PCI diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 1876dbf35..3d05a647d 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -10,6 +10,7 @@ #define __CONFIG_H #include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> #include <linux/sizes.h> #include "mx6_common.h" @@ -196,4 +197,15 @@ #define CONFIG_CMD_CACHE #endif +#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(4, 11) << 8)) +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index ba55177e7..8bce28fe2 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -40,6 +40,7 @@ /* * CPU specifics */ +#define CONFIG_SYS_GENERIC_BOARD /* MXS uses FDT */ #define CONFIG_OF_LIBFDT diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index f7e7315a9..b2b17ce96 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -24,6 +24,7 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) @@ -141,6 +142,7 @@ #define CONFIG_CMD_HDMIDETECT #define CONFIG_CONSOLE_MUX #define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index fae0e6ffc..0a7df60f2 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -66,6 +66,16 @@ #define CONFIG_TWL4030_USB 1 #define CONFIG_USB_ETHER #define CONFIG_USB_ETHER_RNDIS +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_VBUS_DRAW 0 +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_G_DNL_VENDOR_NUM 0x0451 +#define CONFIG_G_DNL_PRODUCT_NUM 0xd022 +#define CONFIG_G_DNL_MANUFACTURER "TI" +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000 /* USB EHCI */ #define CONFIG_CMD_USB @@ -170,11 +180,17 @@ "if test $beaglerev = C4; then " \ "setenv fdtfile omap3-beagle.dtb; fi; " \ "if test $beaglerev = xMAB; then " \ - "setenv fdtfile omap3-beagle-xm.dtb; fi; " \ + "setenv fdtfile omap3-beagle-xm-ab.dtb; fi; " \ "if test $beaglerev = xMC; then " \ "setenv fdtfile omap3-beagle-xm.dtb; fi; " \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ + "validatefdt=" \ + "if test $beaglerev = xMAB; then " \ + "if test ! -e mmc ${bootpart} ${bootdir}/${fdtfile}; then " \ + "setenv fdtfile omap3-beagle-xm.dtb; " \ + "fi; " \ + "fi; \0" \ "bootenv=uEnv.txt\0" \ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ @@ -190,7 +206,7 @@ "rootfstype=${ramrootfstype}\0" \ "loadramdisk=load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \ "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "loadfdt=run validatefdt; load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index 8d11010f8..a3dcb152d 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -127,6 +127,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_SYS_I2C #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 007e27f9f..7b97be9ac 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -7,135 +7,88 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP34XX /* which is a 34XX */ -#define CONFIG_OMAP3_OVERO /* working with overo */ -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON - -#define CONFIG_SDRC /* The chip has SDRC controller */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define CONFIG_NAND -#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <configs/ti_omap3_common.h> -/* - * Display CPU and Board information - */ +/* Display CPU and Board information */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - +/* call misc_init_r */ #define CONFIG_MISC_INIT_R -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG +/* pass the revision tag */ #define CONFIG_REVISION_TAG -#define CONFIG_OF_LIBFDT +/* override size of malloc() pool */ +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ +/* Shift 128 << 15 provides 4 MiB heap to support UBI commands. + * Shift 128 << 10 provides 128 KiB heap for limited-memory devices. */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 15)) -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +/* I2C Support */ +#define CONFIG_SYS_I2C_OMAP34XX -/* - * select serial console configuration - */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 +/* TWL4030 LED */ +#define CONFIG_TWL4030_LED -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ - 115200} -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_OMAP_HSMMC -#define CONFIG_DOS_PARTITION +/* Initialize GPIOs by default */ +#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO Bank 2 */ +#define CONFIG_OMAP3_GPIO_3 /* GPIO64..95 is in GPIO Bank 3 */ +#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO Bank 4 */ +#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO Bank 5 */ +#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO Bank 6 */ /* commands to include */ -#include <config_cmd_default.h> - #define CONFIG_CMD_CACHE -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ - -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_NAND /* NAND support */ - -#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ #undef CONFIG_CMD_IMI /* iminfo */ -#undef CONFIG_CMD_IMLS /* List all found images */ #undef CONFIG_CMD_NFS /* NFS support */ -#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_OMAP34XX +#ifdef CONFIG_NAND +#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */ +#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */ -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER -#define CONFIG_TWL4030_LED +#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */ +#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */ -/* - * Board NAND Info. +#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ + +/* NAND block size is 128 KiB. Synchronize these values with + * overo_nand_partitions in mach-omap2/board-overo.c in Linux: + * xloader 4 * NAND_BLOCK_SIZE = 512 KiB + * uboot 14 * NAND_BLOCK_SIZE = 1792 KiB + * uboot environtment 2 * NAND_BLOCK_SIZE = 256 KiB + * linux 64 * NAND_BLOCK_SIZE = 8 MiB + * rootfs remainder */ +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ + "512k(xloader)," \ + "1792k(u-boot)," \ + "256k(environ)," \ + "8m(linux)," \ + "-(rootfs)" +#else /* CONFIG_NAND */ +#define MTDPARTS_DEFAULT +#endif /* CONFIG_NAND */ + +/* Board NAND Info. */ #define CONFIG_SYS_NAND_QUIET_TEST -#define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand */ - /* at CS0 */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ - /* partition */ - /* Environment information */ -#define CONFIG_BOOTDELAY 5 - #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ + DEFAULT_LINUX_BOOT_ENV \ + "fdtfile=overo.dtb\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "usbtty=cdc_acm\0" \ "console=ttyO2,115200n8\0" \ - "mpurate=500\0" \ + "mpurate=auto\0" \ "optargs=\0" \ "vram=12M\0" \ "dvimode=1024x768MR-16@60\0" \ @@ -145,6 +98,7 @@ "mmcrootfstype=ext3 rootwait\0" \ "nandroot=ubi0:rootfs ubi.mtd=4\0" \ "nandrootfstype=ubifs\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ "mmcargs=setenv bootargs console=${console} " \ "${optargs} " \ "mpurate=${mpurate} " \ @@ -161,80 +115,69 @@ "omapdss.def_disp=${defaultdisplay} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ + "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running boot script from mmc ...; " \ "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ + "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "mmcbootfdt=echo Booting with DT from mmc ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ - "nand read ${loadaddr} 280000 400000; " \ + "nand read ${loadaddr} linux; " \ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi" + "fi;" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loaduimage; then " \ + "run mmcboot;" \ + "fi;" \ + "if run loadzimage; then " \ + "if test -n $fdtfile; then " \ + "if run loadfdt; then " \ + "run mmcbootfdt;" \ + "fi;" \ + "fi;" \ + "fi;" \ + "fi;" \ + "run nandboot; " \ -#define CONFIG_AUTO_COMPLETE 1 /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#undef CONFIG_SYS_PROMPT #define CONFIG_SYS_PROMPT "Overo # " -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command */ - /* args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* memtest works on */ #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 0x01F00000) /* 31MB */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ - /* address */ -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ - +/* FLASH and environment organization */ /* Configure the PISMO */ #define PISMO1_NAND_SIZE GPMC_SIZE_128M #define PISMO1_ONEN_SIZE GPMC_SIZE_128M -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#if defined(CONFIG_CMD_NAND) +#if defined(CONFIG_NAND) #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE #endif @@ -250,67 +193,18 @@ #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET +/* Configure SMSC9211 ethernet */ #if defined(CONFIG_CMD_NET) -/*---------------------------------------------------------------------------- - * SMSC9211 Ethernet from SMSC9118 family - *---------------------------------------------------------------------------- - */ - #define CONFIG_SMC911X #define CONFIG_SMC911X_32_BIT #define CONFIG_SMC911X_BASE 0x2C000000 - #endif /* (CONFIG_CMD_NET) */ -/* - * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader - * and older u-boot.bin with the new U-Boot SPL. - */ -#define CONFIG_SYS_TEXT_BASE 0x80008000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +/* Initial RAM setup */ #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - #define CONFIG_SYS_CACHELINE_SIZE 64 -/* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_TEXT_BASE 0x40200800 -#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK - -/* move malloc and bss high to prevent clashing with the main image */ -#define CONFIG_SYS_SPL_MALLOC_START 0x87000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 -#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */ -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_GPIO_SUPPORT -#define CONFIG_SPL_POWER_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" - /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 diff --git a/include/configs/pepper.h b/include/configs/pepper.h new file mode 100644 index 000000000..cc153abaa --- /dev/null +++ b/include/configs/pepper.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2013 Gumstix, Inc. - http://www.gumstix.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_PEPPER_H +#define __CONFIG_PEPPER_H + +#define CONFIG_MMC +#include <configs/ti_am335x_common.h> + +#undef CONFIG_BOARD_LATE_INIT +#undef CONFIG_SPL_OS_BOOT + +/* Clock defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "pepper# " + +/* Mach type */ +#define MACH_TYPE_PEPPER 4207 /* Until the next sync */ +#define CONFIG_MACH_TYPE MACH_TYPE_PEPPER + +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_IS_NOWHERE +/* Display cpuinfo */ +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "fdtfile=am335x-pepper.dtb\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \ + "load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "loaduimage=fatload mmc ${mmcdev}:1 ${loadaddr} uImage\0" \ + "uimageboot=echo Booting from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "ubiboot=echo Booting from nand (ubifs) ...; " \ + "run ubiargs; run ubiload; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run mmcload; then " \ + "run mmcboot;" \ + "fi;" \ + "if run loaduimage; then " \ + "run uimageboot;" \ + "fi;" \ + "fi;" \ + +/* Serial console configuration */ +#define CONFIG_CONS_INDEX 1 /* UART0 */ +#define CONFIG_SERIAL1 1 +#define CONFIG_SYS_NS16550_COM1 0x44e09000 + +/* Ethernet support */ +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 0 +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_PHY_RESET_DELAY 1000 + +/* SPL */ +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#endif /* __CONFIG_PEPPER_H */ diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 6276d4339..d75d56296 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -21,7 +21,7 @@ #include "siemens-am33x-common.h" #define CONFIG_SYS_MPUCLK 720 -#define DXR2_IOCTRL_VAL 0x18b +#define DDR_IOCTRL_VAL 0x18b #define DDR_PLL_FREQ 266 #define BOARD_DFU_BUTTON_GPIO 59 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 991c43e1c..799d4fe9d 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -214,8 +214,8 @@ /* * I2C Settings */ -#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get(j4, 3) -#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get(j4, 0) +#define CONFIG_SOFT_I2C_GPIO_SCL S5PC110_GPIO_J43 +#define CONFIG_SOFT_I2C_GPIO_SDA S5PC110_GPIO_J40 #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 2da887109..eb046cdac 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -111,12 +111,9 @@ "onenand write 0x41008000 0xc00000 0x500000\0" \ "bootk=" \ "run loaduimage; bootm 0x40007FC0\0" \ - "updatemmc=" \ - "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \ - "mmc boot 0 1 1 0\0" \ "updatebackup=" \ - "mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \ - "mmc boot 0 1 1 0\0" \ + "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \ + "mmc dev 0 0\0" \ "updatebootb=" \ "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ "lpj=lpj=3981312\0" \ @@ -170,8 +167,8 @@ /* * I2C Settings */ -#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(1, b, 7) -#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(1, b, 6) +#define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_B7 +#define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_B6 #define CONFIG_CMD_I2C @@ -196,10 +193,10 @@ */ #define CONFIG_SOFT_SPI #define CONFIG_SOFT_SPI_MODE SPI_MODE_3 -#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_get(2, y3, 1) -#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_get(2, y3, 3) -#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_get(2, y3, 0) -#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_get(2, y4, 3) +#define CONFIG_SOFT_SPI_GPIO_SCLK EXYNOS4_GPIO_Y31 +#define CONFIG_SOFT_SPI_GPIO_MOSI EXYNOS4_GPIO_Y33 +#define CONFIG_SOFT_SPI_GPIO_MISO EXYNOS4_GPIO_Y30 +#define CONFIG_SOFT_SPI_GPIO_CS EXYNOS4_GPIO_Y43 #define SPI_DELAY udelay(1) #undef SPI_INIT @@ -231,8 +228,8 @@ int universal_spi_read(void); #define KEY_PWR_INTERRUPT_REG MAX8998_REG_IRQ1 #define KEY_PWR_INTERRUPT_MASK (1 << 7) -#define KEY_VOL_UP_GPIO exynos4_gpio_get(2, x2, 0) -#define KEY_VOL_DOWN_GPIO exynos4_gpio_get(2, x2, 1) +#define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 +#define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 #endif /* __ASSEMBLY__ */ /* LCD console */ diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index 41c946d1e..f72ab0bad 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -18,15 +18,20 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_AT91FAMILY #define CONFIG_ARCH_CPU_INIT + +#ifndef CONFIG_SPL_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT +#endif + #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT /* Device Tree support */ +#define CONFIG_SYS_GENERIC_BOARD + /* general purpose I/O */ #define CONFIG_AT91_GPIO @@ -74,8 +79,12 @@ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS #define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x310000 +#else #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif /* NAND flash */ #define CONFIG_CMD_NAND @@ -199,4 +208,46 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +/* SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT + +#elif CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + +#endif + #endif diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 516be85fe..da2718044 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -21,7 +21,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_AT91FAMILY #define CONFIG_ARCH_CPU_INIT #ifndef CONFIG_SPL_BUILD @@ -34,6 +33,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT /* Device Tree support */ +#define CONFIG_SYS_GENERIC_BOARD + /* general purpose I/O */ #define CONFIG_AT91_GPIO @@ -281,6 +282,7 @@ #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER #elif CONFIG_SYS_USE_SERIALFLASH #define CONFIG_SPL_SPI_SUPPORT diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 721c4e6ba..53816a602 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -46,6 +46,8 @@ #define CONFIG_CMD_ECHO #define CONFIG_CMD_CACHE +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_ENV_VARS_UBOOT_CONFIG #ifndef CONFIG_SPL_BUILD #define CONFIG_ROOTPATH "/opt/eldk" @@ -358,7 +360,7 @@ #define CONFIG_COMMON_ENV_SETTINGS \ "verify=no \0" \ - "project_dir=systemone\0" \ + "project_dir=targetdir\0" \ "upgrade_available=0\0" \ "altbootcmd=run bootcmd\0" \ "bootlimit=3\0" \ @@ -402,7 +404,11 @@ "dfu_args=run bootargs_defaults;" \ "setenv bootargs ${bootargs} ;" \ "mtdparts default; " \ - "dfu 0 nand 0; \0" \ + "led dfu 1;" \ + "led stat 0;" \ + "dfu 0 nand 0;" \ + "led dfu 0;" \ + "led stat 1;\0" \ "dfu_alt_info=" DFU_ALT_INFO_NAND "\0" \ "net_args=run bootargs_defaults;" \ "mtdparts default;" \ diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 183aae726..66fa1799e 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -14,4 +14,8 @@ #undef CONFIG_DEFAULT_DEVICE_TREE #define CONFIG_DEFAULT_DEVICE_TREE exynos5250-smdk5250 +/* Enable FIT support and comparison */ +#define CONFIG_FIT +#define CONFIG_FIT_BEST_MATCH + #endif /* __CONFIG_SMDK_H */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index b96eea889..58f706a3a 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -51,4 +51,8 @@ #define CONFIG_MAX_I2C_NUM 11 +/* Enable FIT support and comparison */ +#define CONFIG_FIT +#define CONFIG_FIT_BEST_MATCH + #endif /* __CONFIG_5420_H */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 1388f4998..34adfaf60 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -12,6 +12,7 @@ /* High Level Configuration Options */ #define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ #define CONFIG_S5P 1 /* S5P Family */ +#define CONFIG_EXYNOS4 /* EXYNOS4 Family */ #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ #define CONFIG_SMDKV310 1 /* working with SMDKV310*/ diff --git a/include/configs/snow.h b/include/configs/snow.h index ed5c0b614..673fa1469 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -14,4 +14,8 @@ #undef CONFIG_DEFAULT_DEVICE_TREE #define CONFIG_DEFAULT_DEVICE_TREE exynos5250-snow +/* Enable FIT support and comparison */ +#define CONFIG_FIT +#define CONFIG_FIT_BEST_MATCH + #endif /* __CONFIG_SNOW_H */ diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h new file mode 100644 index 000000000..9b693f703 --- /dev/null +++ b/include/configs/sun7i.h @@ -0,0 +1,24 @@ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> + * + * Configuration settings for the Allwinner A20 (sun7i) CPU + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * A20 specific configuration + */ +#define CONFIG_SUN7I /* sun7i SoC generation */ + +#define CONFIG_SYS_PROMPT "sun7i# " + +/* + * Include common sunxi configuration where most the settings are + */ +#include <configs/sunxi-common.h> + +#endif /* __CONFIG_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h new file mode 100644 index 000000000..5d72d62f1 --- /dev/null +++ b/include/configs/sunxi-common.h @@ -0,0 +1,195 @@ +/* + * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net> + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * Configuration settings for the Allwinner sunxi series of boards. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_COMMON_CONFIG_H +#define _SUNXI_COMMON_CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_SUNXI /* sunxi family */ +#ifdef CONFIG_SPL_BUILD +#ifndef CONFIG_SPL_FEL +#define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */ +#endif +#endif + +#include <asm/arch/cpu.h> /* get chip and board defs */ + +#define CONFIG_SYS_TEXT_BASE 0x4a000000 + +/* + * Display CPU information + */ +#define CONFIG_DISPLAY_CPUINFO + +/* Serial & console */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +/* ns16550 reg in the low bits of cpu reg */ +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK 24000000 +#define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE +#define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE +#define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE +#define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE + +/* DRAM Base */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_INIT_RAM_ADDR 0x0 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ + +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_SETEXPR + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG + +/* mmc config */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_MMC +#define CONFIG_MMC_SUNXI +#define CONFIG_MMC_SUNXI_SLOT 0 +#define CONFIG_MMC_SUNXI_USE_DMA +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ + +/* 4MB of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) + +/* + * Miscellaneous configurable options + */ +#define CONFIG_CMD_ECHO +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_GENERIC_BOARD + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR 0x48000000 /* default load address */ + +/* standalone support */ +#define CONFIG_STANDALONE_LOAD_ADDR 0x48000000 + +#define CONFIG_SYS_HZ 1000 + +/* baudrate */ +#define CONFIG_BAUDRATE 115200 + +/* The stack sizes are set up in start.S using the settings below */ +#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ + +/* FLASH and environment organization */ + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512 KiB */ +#define CONFIG_IDENT_STRING " Allwinner Technology" + +#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" + +#define CONFIG_SYS_BOOT_GET_CMDLINE + +#include <config_cmd_default.h> + +#define CONFIG_FAT_WRITE /* enable write access */ + +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT + +#ifdef CONFIG_SPL_FEL + +#define CONFIG_SPL +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds" +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/sunxi" +#define CONFIG_SPL_TEXT_BASE 0x2000 +#define CONFIG_SPL_MAX_SIZE 0x4000 /* 16 KiB */ + +#else /* CONFIG_SPL */ + +#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KiB */ + +#define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */ +#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */ + +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */ +#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ + +#endif /* CONFIG_SPL */ + +/* end of 32 KiB in sram */ +#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK +#define CONFIG_SYS_SPL_MALLOC_START 0x4ff00000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 /* 512 KiB */ + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +#define CONFIG_CONS_INDEX 1 /* UART0 */ + +#ifdef CONFIG_SUNXI_GMAC +#define CONFIG_DESIGNWARE_ETH /* GMAC can use designware driver */ +#define CONFIG_DW_AUTONEG +#define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */ +#define CONFIG_PHY_ADDR 1 +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_PHYLIB +#endif + +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_DNS +#define CONFIG_NETCONSOLE +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#endif + +#if !defined CONFIG_ENV_IS_IN_MMC && \ + !defined CONFIG_ENV_IS_IN_NAND && \ + !defined CONFIG_ENV_IS_IN_FAT && \ + !defined CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_IS_NOWHERE +#endif + +#ifndef CONFIG_SPL_BUILD +#include <config_distro_defaults.h> +#endif + +#endif /* _SUNXI_COMMON_CONFIG_H */ diff --git a/include/configs/tb100.h b/include/configs/tb100.h new file mode 100644 index 000000000..8a861a836 --- /dev/null +++ b/include/configs/tb100.h @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2011-2014 Pierrick Hascoet, Abilis Systems + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_TB100_H_ +#define _CONFIG_TB100_H_ + +#include <linux/sizes.h> + +/* + * CPU configuration + */ +#define CONFIG_ARC700 +#define CONFIG_ARC_MMU_VER 3 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_CLK_FREQ 500000000 +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ + +/* + * Board configuration + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_ARCH_EARLY_INIT_R + +/* + * Memory configuration + */ +#define CONFIG_SYS_TEXT_BASE 0x84000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE SZ_128M + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN SZ_128K +#define CONFIG_SYS_BOOTM_LEN SZ_32M +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_SYS_NO_FLASH + +/* + * UART configuration + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK 166666666 +#define CONFIG_SYS_NS16550_COM1 0xFF100000 +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_BAUDRATE 115200 + +/* + * Ethernet PHY configuration + */ +#define CONFIG_PHYLIB +#define CONFIG_PHY_GIGE + +/* + * Even though the board houses Realtek RTL8211E PHY + * corresponding PHY driver (drivers/net/phy/realtek.c) behaves unexpectedly. + * In particular "parse_status" reports link is down. + * + * Until Realtek PHY driver is fixed fall back to generic PHY driver + * which implements all required functionality and behaves much more stable. + * + * #define CONFIG_PHY_REALTEK + * + */ + +/* + * Ethernet configuration + */ +#define CONFIG_DESIGNWARE_ETH +#define ETH0_BASE_ADDRESS 0xFE100000 +#define ETH1_BASE_ADDRESS 0xFE110000 + +/* + * Command line configuration + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_PING + +#define CONFIG_OF_LIBFDT + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 16 + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE SZ_2K +#define CONFIG_ENV_OFFSET 0 + +/* + * Environment configuration + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyS0,115200n8" +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* + * Console configuration + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "[tb100]:~# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#endif /* _CONFIG_TB100_H_ */ diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index ae786cfd7..129acf2cb 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -48,6 +48,13 @@ #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* + * Common HW configuration. + * If this varies between SoCs later, move to tegraNN-common.h + * Note: This is number of devices, not max device ID. + */ +#define CONFIG_SYS_MMC_MAX_DEVICE 4 + +/* * select serial console configuration */ #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 77fbfb641..44b37183b 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -109,9 +109,13 @@ "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ "env import -t ${loadaddr} ${filesize}\0" \ "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \ "mmcboot=echo Booting from mmc${mmcdev} ...; " \ "run mmcargs; " \ "bootz ${loadaddr} - ${fdtaddr}\0" \ + "uimageboot=echo Booting from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ "findfdt="\ "if test $board_name = sdp4430; then " \ "setenv fdtfile omap4-sdp.dtb; fi; " \ @@ -121,6 +125,8 @@ "setenv fdtfile omap4-panda-a4.dtb; fi;" \ "if test $board_name = panda-es; then " \ "setenv fdtfile omap4-panda-es.dtb; fi;" \ + "if test $board_name = duovero; then " \ + "setenv fdtfile omap4-duovero.dtb; fi;" \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ @@ -144,6 +150,9 @@ "run loadfdt;" \ "run mmcboot; " \ "fi; " \ + "if run loaduimage; then " \ + "run uimageboot;" \ + "fi; " \ "fi" /* diff --git a/include/configs/trats.h b/include/configs/trats.h index c4afecf3d..90f19626a 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -59,7 +59,7 @@ #define CONFIG_BOOTARGS "Please use defined boot" #define CONFIG_BOOTCOMMAND "run mmcboot" -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - GENERATED_GBL_DATA_SIZE) @@ -121,12 +121,9 @@ "bootm 0x40007FC0 - ${fdtaddr};" \ "fi;" \ "bootm 0x40007FC0;\0" \ - "updatemmc=" \ - "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \ - "mmc boot 0 1 1 0\0" \ "updatebackup=" \ - "mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \ - "mmc boot 0 1 1 0\0" \ + "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \ + "mmc dev 0 0\0" \ "updatebootb=" \ "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ "lpj=lpj=3981312\0" \ @@ -207,8 +204,8 @@ #define CONFIG_SYS_I2C_INIT_BOARD /* I2C FG */ -#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(2, y4, 1) -#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(2, y4, 0) +#define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_Y41 +#define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_Y40 /* POWER */ #define CONFIG_POWER @@ -245,8 +242,8 @@ #define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1 #define KEY_PWR_INTERRUPT_MASK (1 << 0) -#define KEY_VOL_UP_GPIO exynos4_gpio_get(2, x2, 0) -#define KEY_VOL_DOWN_GPIO exynos4_gpio_get(2, x2, 1) +#define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 +#define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 #endif /* __ASSEMBLY__ */ /* LCD console */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 14def7d16..206975bca 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -52,7 +52,7 @@ #define CONFIG_BOOTARGS "Please use defined boot" #define CONFIG_BOOTCOMMAND "run mmcboot" -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - GENERATED_GBL_DATA_SIZE) @@ -111,16 +111,11 @@ "bootm 0x40007FC0 - ${fdtaddr};" \ "fi;" \ "bootm 0x40007FC0;\0" \ - "updatemmc=" \ - "mmc boot 0 1 1 1; mmc write 0x42008000 0 0x200;" \ - "mmc boot 0 1 1 0\0" \ "updatebackup=" \ - "mmc boot 0 1 1 2; mmc write 0x42100000 0 0x200;" \ - " mmc boot 0 1 1 0\0" \ + "mmc dev 0 2; mmc write 0x51000000 0 0x800;" \ + " mmc dev 0 0\0" \ "updatebootb=" \ - "mmc read 0x51000000 0x80 0x200; run updatebackup\0" \ - "updateuboot=" \ - "mmc write 0x50000000 0x80 0x400\0" \ + "mmc read 0x51000000 0x80 0x800; run updatebackup\0" \ "mmcboot=" \ "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ @@ -227,8 +222,8 @@ int get_soft_i2c_sda_pin(void); #define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1 #define KEY_PWR_INTERRUPT_MASK (1 << 1) -#define KEY_VOL_UP_GPIO exynos4x12_gpio_get(2, x2, 2) -#define KEY_VOL_DOWN_GPIO exynos4x12_gpio_get(2, x3, 3) +#define KEY_VOL_UP_GPIO EXYNOS4X12_GPIO_X22 +#define KEY_VOL_DOWN_GPIO EXYNOS4X12_GPIO_X33 #endif /* __ASSEMBLY__ */ /* LCD console */ diff --git a/include/configs/tseries.h b/include/configs/tseries.h index 8fb87ac44..e550afad4 100644 --- a/include/configs/tseries.h +++ b/include/configs/tseries.h @@ -237,7 +237,7 @@ #elif defined(CONFIG_EMMC_BOOT) #undef CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_MMC_ENV_PART 2 #define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) diff --git a/include/configs/udoo.h b/include/configs/udoo.h index a0306de6a..700e9c1b2 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -26,6 +26,8 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h index 14c6e675c..bef821f33 100644 --- a/include/configs/vl_ma2sc.h +++ b/include/configs/vl_ma2sc.h @@ -13,8 +13,6 @@ /*--------------------------------------------------------------------------*/ -#define CONFIG_ARM926EJS /* This is an ARM926EJS Core */ -#define CONFIG_AT91FAMILY #define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/ #define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */ #define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 6c74c7295..7d96908f0 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -26,6 +26,8 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) @@ -56,6 +58,12 @@ #define CONFIG_LOADADDR 0x12000000 #define CONFIG_SYS_TEXT_BASE 0x17800000 +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + /* MMC Configuration */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC @@ -98,7 +106,9 @@ #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO #define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_CMD_HDMIDETECT #define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) #define CONFIG_DEFAULT_FDT_FILE "imx6dl-wandboard.dtb" @@ -135,7 +145,33 @@ "fi; " \ "fi\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ + "root=${mmcroot}; run videoargs\0" \ + "videoargs=" \ + "setenv nextcon 0; " \ + "if hdmidet; then " \ + "setenv bootargs ${bootargs} " \ + "video=mxcfb${nextcon}:dev=hdmi,1280x720M@60," \ + "if=RGB24; " \ + "setenv fbmen fbmem=28M; " \ + "setexpr nextcon ${nextcon} + 1; " \ + "else " \ + "echo - no HDMI monitor;" \ + "fi; " \ + "i2c dev 1; " \ + "if i2c probe 0x10; then " \ + "setenv bootargs ${bootargs} " \ + "video=mxcfb${nextcon}:dev=lcd,800x480@60," \ + "if=RGB666; " \ + "if test 0 -eq ${nextcon}; then " \ + "setenv fbmem fbmem=10M; " \ + "else " \ + "setenv fbmem ${fbmem},10M; " \ + "fi; " \ + "setexpr nextcon ${nextcon} + 1; " \ + "else " \ + "echo '- no FWBADAPT-7WVGA-LCD-F07A-0102 display';" \ + "fi; " \ + "setenv bootargs ${bootargs} ${fbmem}\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ diff --git a/include/configs/x600.h b/include/configs/x600.h index 7405419f0..eae85d62c 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -107,6 +107,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMD_GPIO #define CONFIG_CMD_I2C #define CONFIG_CMD_MEMORY diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 731e69b5f..dc5bc22ce 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -83,10 +83,27 @@ # define CONFIG_SDHCI # define CONFIG_ZYNQ_SDHCI # define CONFIG_CMD_MMC -# define CONFIG_CMD_FAT +#endif + +#ifdef CONFIG_ZYNQ_USB +# define CONFIG_USB_EHCI +# define CONFIG_CMD_USB +# define CONFIG_USB_STORAGE +# define CONFIG_USB_EHCI_ZYNQ +# define CONFIG_USB_ULPI_VIEWPORT +# define CONFIG_USB_ULPI +# define CONFIG_EHCI_IS_TDI +# define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQ_USB) # define CONFIG_SUPPORT_VFAT +# define CONFIG_CMD_FAT # define CONFIG_CMD_EXT2 +# define CONFIG_FAT_WRITE # define CONFIG_DOS_PARTITION +# define CONFIG_CMD_EXT4 +# define CONFIG_CMD_EXT4_WRITE #endif #define CONFIG_SYS_I2C_ZYNQ @@ -150,7 +167,13 @@ "bootm ${load_addr}\0" \ "jtagboot=echo TFTPing FIT to RAM... && " \ "tftpboot ${load_addr} ${fit_image} && " \ - "bootm ${load_addr}\0" + "bootm ${load_addr}\0" \ + "usbboot=if usb start; then " \ + "echo Copying FIT from USB to RAM... && " \ + "fatload usb 0 ${load_addr} ${fit_image} && " \ + "bootm ${load_addr}\0" \ + "fi\0" + #define CONFIG_BOOTCOMMAND "run $modeboot" #define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */ #define CONFIG_SYS_LOAD_ADDR 0 /* default? */ @@ -165,7 +188,7 @@ #define CONFIG_SYS_LONGHELP #define CONFIG_CLOCKS #define CONFIG_CMD_CLK -#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) @@ -191,6 +214,10 @@ #define CONFIG_FPGA_XILINX #define CONFIG_FPGA_ZYNQPL #define CONFIG_CMD_FPGA +#define CONFIG_CMD_FPGA_LOADMK +#define CONFIG_CMD_FPGA_LOADP +#define CONFIG_CMD_FPGA_LOADBP +#define CONFIG_CMD_FPGA_LOADFS /* Open Firmware flat tree */ #define CONFIG_OF_LIBFDT @@ -209,7 +236,7 @@ #define CONFIG_RSA /* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN (20 * 1024 * 1024) +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) /* Boot FreeBSD/vxWorks from an ELF image */ #if defined(CONFIG_ZYNQ_BOOT_FREEBSD) @@ -235,16 +262,10 @@ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/zynq/u-boot-spl.lds" -/* Disable dcache for SPL just for sure */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_DCACHE_OFF -#undef CONFIG_FPGA -#undef CONFIG_OF_CONTROL -#endif - /* MMC support */ #ifdef CONFIG_ZYNQ_SDHCI0 #define CONFIG_SPL_MMC_SUPPORT @@ -253,7 +274,18 @@ #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_OF_SEPARATE) +# define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot-dtb.img" +#else +# define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#endif +#endif + +/* Disable dcache for SPL just for sure */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_DCACHE_OFF +#undef CONFIG_FPGA +#undef CONFIG_OF_CONTROL #endif /* Address in RAM where the parameters must be copied by SPL. */ diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h index de0e24129..291a5fef5 100644 --- a/include/configs/zynq_zc70x.h +++ b/include/configs/zynq_zc70x.h @@ -19,6 +19,7 @@ #define CONFIG_SYS_NO_FLASH #define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_USB #define CONFIG_ZYNQ_I2C0 #define CONFIG_ZYNQ_EEPROM #define CONFIG_ZYNQ_BOOT_FREEBSD diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h index 274140cb3..ce17d4060 100644 --- a/include/configs/zynq_zed.h +++ b/include/configs/zynq_zed.h @@ -18,6 +18,7 @@ #define CONFIG_SYS_NO_FLASH +#define CONFIG_ZYNQ_USB #define CONFIG_ZYNQ_SDHCI0 #define CONFIG_ZYNQ_BOOT_FREEBSD #define CONFIG_DEFAULT_DEVICE_TREE zynq-zed diff --git a/include/dfu.h b/include/dfu.h index 240916854..26ffbc8e8 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -43,6 +43,9 @@ struct mmc_internal_data { unsigned int lba_size; unsigned int lba_blk_size; + /* eMMC HW partition access */ + int hw_partition; + /* FAT/EXT */ unsigned int dev; unsigned int part; @@ -100,6 +103,7 @@ struct dfu_entity { u64 offset, void *buf, long *len); int (*flush_medium)(struct dfu_entity *dfu); + unsigned int (*poll_timeout)(struct dfu_entity *dfu); struct list_head list; diff --git a/include/dm-demo.h b/include/dm-demo.h index 6e38d3c5b..a24fec665 100644 --- a/include/dm-demo.h +++ b/include/dm-demo.h @@ -23,14 +23,14 @@ struct dm_demo_pdata { }; struct demo_ops { - int (*hello)(struct device *dev, int ch); - int (*status)(struct device *dev, int *status); + int (*hello)(struct udevice *dev, int ch); + int (*status)(struct udevice *dev, int *status); }; -int demo_hello(struct device *dev, int ch); -int demo_status(struct device *dev, int *status); +int demo_hello(struct udevice *dev, int ch); +int demo_status(struct udevice *dev, int *status); int demo_list(void); -int demo_parse_dt(struct device *dev); +int demo_parse_dt(struct udevice *dev); #endif diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h index c026e8e49..ea3df3663 100644 --- a/include/dm/device-internal.h +++ b/include/dm/device-internal.h @@ -11,7 +11,7 @@ #ifndef _DM_DEVICE_INTERNAL_H #define _DM_DEVICE_INTERNAL_H -struct device; +struct udevice; /** * device_bind() - Create a device and bind it to a driver @@ -34,9 +34,9 @@ struct device; * @devp: Returns a pointer to the bound device * @return 0 if OK, -ve on error */ -int device_bind(struct device *parent, struct driver *drv, +int device_bind(struct udevice *parent, struct driver *drv, const char *name, void *platdata, int of_offset, - struct device **devp); + struct udevice **devp); /** * device_bind_by_name: Create a device and bind it to a driver @@ -49,8 +49,8 @@ int device_bind(struct device *parent, struct driver *drv, * @devp: Returns a pointer to the bound device * @return 0 if OK, -ve on error */ -int device_bind_by_name(struct device *parent, const struct driver_info *info, - struct device **devp); +int device_bind_by_name(struct udevice *parent, const struct driver_info *info, + struct udevice **devp); /** * device_probe() - Probe a device, activating it @@ -61,7 +61,7 @@ int device_bind_by_name(struct device *parent, const struct driver_info *info, * @dev: Pointer to device to probe * @return 0 if OK, -ve on error */ -int device_probe(struct device *dev); +int device_probe(struct udevice *dev); /** * device_remove() - Remove a device, de-activating it @@ -72,7 +72,7 @@ int device_probe(struct device *dev); * @dev: Pointer to device to remove * @return 0 if OK, -ve on error (an error here is normally a very bad thing) */ -int device_remove(struct device *dev); +int device_remove(struct udevice *dev); /** * device_unbind() - Unbind a device, destroying it @@ -82,6 +82,6 @@ int device_remove(struct device *dev); * @dev: Pointer to device to unbind * @return 0 if OK, -ve on error */ -int device_unbind(struct device *dev); +int device_unbind(struct udevice *dev); #endif diff --git a/include/dm/device.h b/include/dm/device.h index 4cd38ed2d..ec049824e 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -24,7 +24,7 @@ struct driver_info; #define DM_FLAG_ALLOC_PDATA (2 << 0) /** - * struct device - An instance of a driver + * struct udevice - An instance of a driver * * This holds information about a device, which is a driver bound to a * particular port or peripheral (essentially a driver instance). @@ -53,12 +53,12 @@ struct driver_info; * @sibling_node: Next device in list of all devices * @flags: Flags for this device DM_FLAG_... */ -struct device { +struct udevice { struct driver *driver; const char *name; void *platdata; int of_offset; - struct device *parent; + struct udevice *parent; void *priv; struct uclass *uclass; void *uclass_priv; @@ -122,11 +122,11 @@ struct driver { char *name; enum uclass_id id; const struct device_id *of_match; - int (*bind)(struct device *dev); - int (*probe)(struct device *dev); - int (*remove)(struct device *dev); - int (*unbind)(struct device *dev); - int (*ofdata_to_platdata)(struct device *dev); + int (*bind)(struct udevice *dev); + int (*probe)(struct udevice *dev); + int (*remove)(struct udevice *dev); + int (*unbind)(struct udevice *dev); + int (*ofdata_to_platdata)(struct udevice *dev); int priv_auto_alloc_size; int platdata_auto_alloc_size; const void *ops; /* driver-specific operations */ @@ -144,7 +144,7 @@ struct driver { * @dev Device to check * @return platform data, or NULL if none */ -void *dev_get_platdata(struct device *dev); +void *dev_get_platdata(struct udevice *dev); /** * dev_get_priv() - Get the private data for a device @@ -154,6 +154,6 @@ void *dev_get_platdata(struct device *dev); * @dev Device to check * @return private data, or NULL if none */ -void *dev_get_priv(struct device *dev); +void *dev_get_priv(struct udevice *dev); #endif diff --git a/include/dm/lists.h b/include/dm/lists.h index 0d09f9a14..7feba4b00 100644 --- a/include/dm/lists.h +++ b/include/dm/lists.h @@ -32,8 +32,8 @@ struct driver *lists_driver_lookup_name(const char *name); */ struct uclass_driver *lists_uclass_lookup(enum uclass_id id); -int lists_bind_drivers(struct device *parent); +int lists_bind_drivers(struct udevice *parent); -int lists_bind_fdt(struct device *parent, const void *blob, int offset); +int lists_bind_fdt(struct udevice *parent, const void *blob, int offset); #endif diff --git a/include/dm/root.h b/include/dm/root.h index 0ebccda35..3018bc862 100644 --- a/include/dm/root.h +++ b/include/dm/root.h @@ -10,7 +10,7 @@ #ifndef _DM_ROOT_H_ #define _DM_ROOT_H_ -struct device; +struct udevice; /** * dm_root() - Return pointer to the top of the driver tree @@ -19,7 +19,7 @@ struct device; * * @return pointer to root device, or NULL if not inited yet */ -struct device *dm_root(void); +struct udevice *dm_root(void); /** * dm_scan_platdata() - Scan all platform data and bind drivers diff --git a/include/dm/test.h b/include/dm/test.h index eeaa2eb2f..409f1a366 100644 --- a/include/dm/test.h +++ b/include/dm/test.h @@ -30,7 +30,7 @@ struct dm_test_pdata { * @return 0 if OK, -ve on error */ struct test_ops { - int (*ping)(struct device *dev, int pingval, int *pingret); + int (*ping)(struct udevice *dev, int pingval, int *pingret); }; /* Operations that our test driver supports */ @@ -102,8 +102,8 @@ extern struct dm_test_state global_test_state; * @skip_post_probe: Skip uclass post-probe processing */ struct dm_test_state { - struct device *root; - struct device *testdev; + struct udevice *root; + struct udevice *testdev; int fail_count; int force_fail_alloc; int skip_post_probe; @@ -138,8 +138,8 @@ struct dm_test { } /* Declare ping methods for the drivers */ -int test_ping(struct device *dev, int pingval, int *pingret); -int testfdt_ping(struct device *dev, int pingval, int *pingret); +int test_ping(struct udevice *dev, int pingval, int *pingret); +int testfdt_ping(struct udevice *dev, int pingval, int *pingret); /** * dm_check_operations() - Check that we can perform ping operations @@ -152,7 +152,7 @@ int testfdt_ping(struct device *dev, int pingval, int *pingret); * @priv: Pointer to private test information * @return 0 if OK, -ve on error */ -int dm_check_operations(struct dm_test_state *dms, struct device *dev, +int dm_check_operations(struct dm_test_state *dms, struct udevice *dev, uint32_t base, struct dm_test_priv *priv); /** diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h index cc65d5259..1434db3eb 100644 --- a/include/dm/uclass-internal.h +++ b/include/dm/uclass-internal.h @@ -21,7 +21,7 @@ * @return the uclass pointer of a child at the given index or * return NULL on error. */ -int uclass_find_device(enum uclass_id id, int index, struct device **devp); +int uclass_find_device(enum uclass_id id, int index, struct udevice **devp); /** * uclass_bind_device() - Associate device with a uclass @@ -31,7 +31,7 @@ int uclass_find_device(enum uclass_id id, int index, struct device **devp); * @dev: Pointer to the device * #return 0 on success, -ve on error */ -int uclass_bind_device(struct device *dev); +int uclass_bind_device(struct udevice *dev); /** * uclass_unbind_device() - Deassociate device with a uclass @@ -41,7 +41,7 @@ int uclass_bind_device(struct device *dev); * @dev: Pointer to the device * #return 0 on success, -ve on error */ -int uclass_unbind_device(struct device *dev); +int uclass_unbind_device(struct udevice *dev); /** * uclass_post_probe_device() - Deal with a device that has just been probed @@ -52,7 +52,7 @@ int uclass_unbind_device(struct device *dev); * @dev: Pointer to the device * #return 0 on success, -ve on error */ -int uclass_post_probe_device(struct device *dev); +int uclass_post_probe_device(struct udevice *dev); /** * uclass_pre_remove_device() - Handle a device which is about to be removed @@ -62,7 +62,7 @@ int uclass_post_probe_device(struct device *dev); * @dev: Pointer to the device * #return 0 on success, -ve on error */ -int uclass_pre_remove_device(struct device *dev); +int uclass_pre_remove_device(struct udevice *dev); /** * uclass_find() - Find uclass by its id diff --git a/include/dm/uclass.h b/include/dm/uclass.h index cd23cfed1..931d9c0b9 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -37,7 +37,7 @@ struct uclass { struct list_head sibling_node; }; -struct device; +struct udevice; /** * struct uclass_driver - Driver for the uclass @@ -65,10 +65,10 @@ struct device; struct uclass_driver { const char *name; enum uclass_id id; - int (*post_bind)(struct device *dev); - int (*pre_unbind)(struct device *dev); - int (*post_probe)(struct device *dev); - int (*pre_remove)(struct device *dev); + int (*post_bind)(struct udevice *dev); + int (*pre_unbind)(struct udevice *dev); + int (*post_probe)(struct udevice *dev); + int (*pre_remove)(struct udevice *dev); int (*init)(struct uclass *class); int (*destroy)(struct uclass *class); int priv_auto_alloc_size; @@ -101,7 +101,7 @@ int uclass_get(enum uclass_id key, struct uclass **ucp); * @ucp: Returns pointer to uclass (there is only one per for each ID) * @return 0 if OK, -ve on error */ -int uclass_get_device(enum uclass_id id, int index, struct device **ucp); +int uclass_get_device(enum uclass_id id, int index, struct udevice **ucp); /** * uclass_first_device() - Get the first device in a uclass @@ -110,7 +110,7 @@ int uclass_get_device(enum uclass_id id, int index, struct device **ucp); * @devp: Returns pointer to the first device in that uclass, or NULL if none * @return 0 if OK (found or not found), -1 on error */ -int uclass_first_device(enum uclass_id id, struct device **devp); +int uclass_first_device(enum uclass_id id, struct udevice **devp); /** * uclass_next_device() - Get the next device in a uclass @@ -119,7 +119,7 @@ int uclass_first_device(enum uclass_id id, struct device **devp); * to the next device in the same uclass, or NULL if none * @return 0 if OK (found or not found), -1 on error */ -int uclass_next_device(struct device **devp); +int uclass_next_device(struct udevice **devp); /** * uclass_foreach_dev() - Helper function to iteration through devices @@ -127,7 +127,7 @@ int uclass_next_device(struct device **devp); * This creates a for() loop which works through the available devices in * a uclass in order from start to end. * - * @pos: struct device * to hold the current device. Set to NULL when there + * @pos: struct udevice * to hold the current device. Set to NULL when there * are no more devices. * uc: uclass to scan */ diff --git a/include/fpga.h b/include/fpga.h index 15e603a16..914024c17 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -35,13 +35,29 @@ typedef struct { /* typedef fpga_desc */ void *devdesc; /* real device descriptor */ } fpga_desc; /* end, typedef fpga_desc */ +typedef struct { /* typedef fpga_desc */ + unsigned int blocksize; + char *interface; + char *dev_part; + char *filename; + int fstype; +} fpga_fs_info; + +typedef enum { + BIT_FULL = 0, + BIT_PARTIAL, +} bitstream_type; /* root function definitions */ extern void fpga_init(void); extern int fpga_add(fpga_type devtype, void *desc); extern int fpga_count(void); -extern int fpga_load(int devnum, const void *buf, size_t bsize); -extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size); +extern int fpga_load(int devnum, const void *buf, size_t bsize, + bitstream_type bstype); +extern int fpga_fsload(int devnum, const void *buf, size_t size, + fpga_fs_info *fpga_fsinfo); +extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype); extern int fpga_dump(int devnum, const void *buf, size_t bsize); extern int fpga_info(int devnum); extern const fpga_desc *const fpga_validate(int devnum, const void *buf, diff --git a/include/image.h b/include/image.h index b27877870..41e56abe1 100644 --- a/include/image.h +++ b/include/image.h @@ -225,6 +225,7 @@ struct lmb; #define IH_TYPE_PBLIMAGE 15 /* Freescale PBL Boot Image */ #define IH_TYPE_MXSIMAGE 16 /* Freescale MXSBoot Image */ #define IH_TYPE_GPIMAGE 17 /* TI Keystone GPHeader Image */ +#define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */ /* * Compression Types @@ -413,6 +414,7 @@ enum fit_load_op { #define IMAGE_FORMAT_INVALID 0x00 #define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */ #define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */ +#define IMAGE_FORMAT_ANDROID 0x03 /* Android boot image */ int genimg_get_format(const void *img_addr); int genimg_has_config(bootm_headers_t *images); @@ -1031,4 +1033,16 @@ static inline int fit_image_check_target_arch(const void *fdt, int node) #endif /* CONFIG_FIT_VERBOSE */ #endif /* CONFIG_FIT */ +#if defined(CONFIG_ANDROID_BOOT_IMAGE) +struct andr_img_hdr; +int android_image_check_header(const struct andr_img_hdr *hdr); +int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, + ulong *os_data, ulong *os_len); +int android_image_get_ramdisk(const struct andr_img_hdr *hdr, + ulong *rd_data, ulong *rd_len); +ulong android_image_get_end(const struct andr_img_hdr *hdr); +ulong android_image_get_kload(const struct andr_img_hdr *hdr); + +#endif /* CONFIG_ANDROID_BOOT_IMAGE */ + #endif /* __IMAGE_H__ */ diff --git a/include/mmc.h b/include/mmc.h index bc11f45a6..a3a100bd3 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -54,6 +54,7 @@ #define COMM_ERR -18 /* Communications Error */ #define TIMEOUT -19 #define IN_PROGRESS -20 /* operation is in progress */ +#define SWITCH_ERR -21 /* Card reports failure to switch mode */ #define MMC_CMD_GO_IDLE_STATE 0 #define MMC_CMD_SEND_OP_COND 1 @@ -70,6 +71,7 @@ #define MMC_CMD_SET_BLOCKLEN 16 #define MMC_CMD_READ_SINGLE_BLOCK 17 #define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_SET_BLOCK_COUNT 23 #define MMC_CMD_WRITE_SINGLE_BLOCK 24 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 #define MMC_CMD_ERASE_GROUP_START 35 @@ -109,6 +111,7 @@ #define SECURE_ERASE 0x80000000 #define MMC_STATUS_MASK (~0x0206BF7F) +#define MMC_STATUS_SWITCH_ERROR (1 << 7) #define MMC_STATUS_RDY_FOR_DATA (1 << 8) #define MMC_STATUS_CURR_STATE (0xf << 9) #define MMC_STATUS_ERROR (1 << 19) @@ -225,6 +228,7 @@ * boot partitions (2), general purpose partitions (4) in MMC v4.4. */ #define MMC_NUM_BOOT_PARTITION 2 +#define MMC_PART_RPMB 3 /* RPMB partition number */ struct mmc_cid { unsigned long psn; @@ -336,7 +340,13 @@ int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); /* Function to modify the RST_n_FUNCTION field of EXT_CSD */ int mmc_set_rst_n_function(struct mmc *mmc, u8 enable); - +/* Functions to read / write the RPMB partition */ +int mmc_rpmb_set_key(struct mmc *mmc, void *key); +int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter); +int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, + unsigned short cnt, unsigned char *key); +int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, + unsigned short cnt, unsigned char *key); /** * Start device initialization and return immediately; it does not block on * polling OCR (operation condition register) status. Then you should call diff --git a/include/netdev.h b/include/netdev.h index e211f1841..63481eca2 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -78,6 +78,7 @@ int sh_eth_initialize(bd_t *bis); int skge_initialize(bd_t *bis); int smc91111_initialize(u8 dev_num, int base_addr); int smc911x_initialize(u8 dev_num, int base_addr); +int sunxi_gmac_initialize(bd_t *bis); int sunxi_wemac_initialize(bd_t *bis); int tsi108_eth_initialize(bd_t *bis); int uec_standard_init(bd_t *bis); diff --git a/include/palmas.h b/include/palmas.h index eaf367086..cca3f9a9d 100644 --- a/include/palmas.h +++ b/include/palmas.h @@ -24,6 +24,10 @@ #define LDO1_CTRL 0x50 #define LDO1_VOLTAGE 0x51 +/* LDO2 control/voltage */ +#define LDO2_CTRL 0x52 +#define LDO2_VOLTAGE 0x53 + /* LDO9 control/voltage */ #define LDO9_CTRL 0x60 #define LDO9_VOLTAGE 0x61 diff --git a/include/part.h b/include/part.h index 53532dcd6..f2c8c641f 100644 --- a/include/part.h +++ b/include/part.h @@ -103,6 +103,7 @@ block_dev_desc_t* sata_get_dev(int dev); block_dev_desc_t* scsi_get_dev(int dev); block_dev_desc_t* usb_stor_get_dev(int dev); block_dev_desc_t* mmc_get_dev(int dev); +int mmc_select_hwpart(int dev_num, int hwpart); block_dev_desc_t* systemace_get_dev(int dev); block_dev_desc_t* mg_disk_get_dev(int dev); block_dev_desc_t *host_get_dev(int dev); @@ -126,6 +127,7 @@ static inline block_dev_desc_t* sata_get_dev(int dev) { return NULL; } static inline block_dev_desc_t* scsi_get_dev(int dev) { return NULL; } static inline block_dev_desc_t* usb_stor_get_dev(int dev) { return NULL; } static inline block_dev_desc_t* mmc_get_dev(int dev) { return NULL; } +static inline int mmc_select_hwpart(int dev_num, int hwpart) { return -1; } static inline block_dev_desc_t* systemace_get_dev(int dev) { return NULL; } static inline block_dev_desc_t* mg_disk_get_dev(int dev) { return NULL; } static inline block_dev_desc_t *host_get_dev(int dev) { return NULL; } diff --git a/include/power/ltc3676_pmic.h b/include/power/ltc3676_pmic.h new file mode 100644 index 000000000..dcaa98519 --- /dev/null +++ b/include/power/ltc3676_pmic.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Tim Harvey <tharvey@gateworks.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LTC3676_PMIC_H_ +#define __LTC3676_PMIC_H_ + +/* LTC3676 registers */ +enum { + LTC3676_BUCK1 = 0x01, + LTC3676_BUCK2 = 0x02, + LTC3676_BUCK3 = 0x03, + LTC3676_BUCK4 = 0x04, + LTC3676_LDOA = 0x05, + LTC3676_LDOB = 0x06, + LTC3676_SQD1 = 0x07, + LTC3676_SQD2 = 0x08, + LTC3676_CNTRL = 0x09, + LTC3676_DVB1A = 0x0A, + LTC3676_DVB1B = 0x0B, + LTC3676_DVB2A = 0x0C, + LTC3676_DVB2B = 0x0D, + LTC3676_DVB3A = 0x0E, + LTC3676_DVB3B = 0x0F, + LTC3676_DVB4A = 0x10, + LTC3676_DVB4B = 0x11, + LTC3676_MSKIRQ = 0x12, + LTC3676_MSKPG = 0x13, + LTC3676_USER = 0x14, + LTC3676_HRST = 0x1E, + LTC3676_CLIRQ = 0x1F, + LTC3676_IRQSTAT = 0x15, + LTC3676_PGSTATL = 0x16, + LTC3676_PGSTATR = 0x17, + LTC3676_NUM_OF_REGS = 0x20, +}; + +/* + * SW Configuration + */ + +#define LTC3676_DVB_MASK 0x1f +#define LTC3676_PGOOD_MASK (1<<5) +#define LTC3676_REF_SELA (0<<5) +#define LTC3676_REF_SELB (1<<5) + +int power_ltc3676_init(unsigned char bus); +#endif diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h index 2a9032a1f..444aba6c6 100644 --- a/include/power/pfuze100_pmic.h +++ b/include/power/pfuze100_pmic.h @@ -93,4 +93,5 @@ enum { #define SWBST_MODE_AUTO (2 << 2) #define SWBST_MODE_APS (2 << 3) +int power_pfuze100_init(unsigned char bus); #endif diff --git a/include/samsung/misc.h b/include/samsung/misc.h index ede6c1583..10653a1b1 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -15,6 +15,8 @@ enum { BOOT_MODE_THOR, BOOT_MODE_UMS, BOOT_MODE_DFU, + BOOT_MODE_GPT, + BOOT_MODE_ENV, BOOT_MODE_EXIT, }; diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h index ed460644c..69b80cd1a 100644 --- a/include/usb_mass_storage.h +++ b/include/usb_mass_storage.h @@ -9,17 +9,9 @@ #define __USB_MASS_STORAGE_H__ #define SECTOR_SIZE 0x200 -#include <mmc.h> +#include <part.h> #include <linux/usb/composite.h> -#ifndef UMS_START_SECTOR -#define UMS_START_SECTOR 0 -#endif - -#ifndef UMS_NUM_SECTORS -#define UMS_NUM_SECTORS 0 -#endif - /* Wait at maximum 60 seconds for cable connection */ #define UMS_CABLE_READY_TIMEOUT 60 @@ -31,14 +23,13 @@ struct ums { unsigned int start_sector; unsigned int num_sectors; const char *name; - struct mmc *mmc; + block_dev_desc_t *block_dev; }; extern struct ums *ums; int fsg_init(struct ums *); void fsg_cleanup(void); -struct ums *ums_init(unsigned int); int fsg_main_thread(void *); int fsg_add(struct usb_configuration *c); #endif /* __USB_MASS_STORAGE_H__ */ diff --git a/include/xilinx.h b/include/xilinx.h index 9801267c5..aebcb3bfd 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -45,16 +45,20 @@ typedef struct { /* typedef xilinx_desc */ } xilinx_desc; /* end, typedef xilinx_desc */ struct xilinx_fpga_op { - int (*load)(xilinx_desc *, const void *, size_t); + int (*load)(xilinx_desc *, const void *, size_t, bitstream_type); + int (*loadfs)(xilinx_desc *, const void *, size_t, fpga_fs_info *); int (*dump)(xilinx_desc *, const void *, size_t); int (*info)(xilinx_desc *); }; /* Generic Xilinx Functions *********************************************************************/ -int xilinx_load(xilinx_desc *desc, const void *image, size_t size); +int xilinx_load(xilinx_desc *desc, const void *image, size_t size, + bitstream_type bstype); int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize); int xilinx_info(xilinx_desc *desc); +int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, + fpga_fs_info *fpga_fsinfo); /* Board specific implementation specific function types *********************************************************************/ diff --git a/lib/Makefile b/lib/Makefile index 27e4f78bf..377ab134b 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -35,6 +35,7 @@ obj-y += net_utils.o obj-$(CONFIG_PHYSMEM) += physmem.o obj-y += qsort.o obj-$(CONFIG_SHA1) += sha1.o +obj-$(CONFIG_SUPPORT_EMMC_RPMB) += sha256.o obj-$(CONFIG_SHA256) += sha256.o obj-y += strmhz.o obj-$(CONFIG_TPM) += tpm.o diff --git a/spl/Makefile b/spl/Makefile index 55500fd89..bf677aa42 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -183,12 +183,29 @@ MKIMAGEFLAGS_MLO.byteswap = -T omapimage -n byteswap -a $(CONFIG_SPL_TEXT_BASE) MLO MLO.byteswap: $(obj)/u-boot-spl.bin $(call if_changed,mkimage) +MKIMAGEFLAGS_boot.bin = -T atmelimage + +ifeq ($(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER),y) +MKIMAGEFLAGS_boot.bin += -n $(shell $(obj)/../tools/atmel_pmecc_params) + +boot.bin: $(obj)/../tools/atmel_pmecc_params +endif + +boot.bin: $(obj)/u-boot-spl.bin + $(call if_changed,mkimage) + ALL-y += $(obj)/$(SPL_BIN).bin ifdef CONFIG_SAMSUNG ALL-y += $(obj)/$(BOARD)-spl.bin endif +ifdef CONFIG_SUNXI +ifndef CONFIG_SPL_FEL +ALL-y += $(obj)/sunxi-spl.bin +endif +endif + all: $(ALL-y) ifdef CONFIG_SAMSUNG @@ -216,6 +233,13 @@ ifneq ($(CONFIG_SPL_TEXT_BASE),) LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE) endif +ifdef CONFIG_SUNXI +quiet_cmd_mksunxiboot = MKSUNXI $@ +cmd_mksunxiboot = $(objtree)/tools/mksunxiboot $< $@ +$(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin + $(call if_changed,mksunxiboot) +endif + quiet_cmd_u-boot-spl = LD $@ cmd_u-boot-spl = cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \ $(patsubst $(obj)/%,%,$(u-boot-spl-init)) --start-group \ diff --git a/test/dm/cmd_dm.c b/test/dm/cmd_dm.c index a03fe20f0..083f15c31 100644 --- a/test/dm/cmd_dm.c +++ b/test/dm/cmd_dm.c @@ -16,12 +16,12 @@ #include <dm/test.h> #include <dm/uclass-internal.h> -static int display_succ(struct device *in, char *buf) +static int display_succ(struct udevice *in, char *buf) { int len; int ip = 0; char local[16]; - struct device *pos, *n, *prev = NULL; + struct udevice *pos, *n, *prev = NULL; printf("%s- %s @ %08x", buf, in->name, map_to_sysmem(in)); if (in->flags & DM_FLAG_ACTIVATED) @@ -49,7 +49,7 @@ static int display_succ(struct device *in, char *buf) return 0; } -static int dm_dump(struct device *dev) +static int dm_dump(struct udevice *dev) { if (!dev) return -EINVAL; @@ -59,7 +59,7 @@ static int dm_dump(struct device *dev) static int do_dm_dump_all(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - struct device *root; + struct udevice *root; root = dm_root(); printf("ROOT %08x\n", map_to_sysmem(root)); @@ -74,7 +74,7 @@ static int do_dm_dump_uclass(cmd_tbl_t *cmdtp, int flag, int argc, int id; for (id = 0; id < UCLASS_COUNT; id++) { - struct device *dev; + struct udevice *dev; ret = uclass_get(id, &uc); if (ret) diff --git a/test/dm/core.c b/test/dm/core.c index 14a57c310..be3646b96 100644 --- a/test/dm/core.c +++ b/test/dm/core.c @@ -60,7 +60,7 @@ static struct driver_info driver_info_manual = { /* Test that binding with platdata occurs correctly */ static int dm_test_autobind(struct dm_test_state *dms) { - struct device *dev; + struct udevice *dev; /* * We should have a single class (UCLASS_ROOT) and a single root @@ -95,7 +95,7 @@ DM_TEST(dm_test_autobind, 0); static int dm_test_autoprobe(struct dm_test_state *dms) { int expected_base_add; - struct device *dev; + struct udevice *dev; struct uclass *uc; int i; @@ -157,7 +157,7 @@ DM_TEST(dm_test_autoprobe, DM_TESTF_SCAN_PDATA); static int dm_test_platdata(struct dm_test_state *dms) { const struct dm_test_pdata *pdata; - struct device *dev; + struct udevice *dev; int i; for (i = 0; i < 3; i++) { @@ -175,7 +175,7 @@ DM_TEST(dm_test_platdata, DM_TESTF_SCAN_PDATA); static int dm_test_lifecycle(struct dm_test_state *dms) { int op_count[DM_TEST_OP_COUNT]; - struct device *dev, *test_dev; + struct udevice *dev, *test_dev; int pingret; int ret; @@ -229,7 +229,7 @@ DM_TEST(dm_test_lifecycle, DM_TESTF_SCAN_PDATA | DM_TESTF_PROBE_TEST); /* Test that we can bind/unbind and the lists update correctly */ static int dm_test_ordering(struct dm_test_state *dms) { - struct device *dev, *dev_penultimate, *dev_last, *test_dev; + struct udevice *dev, *dev_penultimate, *dev_last, *test_dev; int pingret; ut_assertok(device_bind_by_name(dms->root, &driver_info_manual, @@ -281,7 +281,7 @@ static int dm_test_ordering(struct dm_test_state *dms) DM_TEST(dm_test_ordering, DM_TESTF_SCAN_PDATA); /* Check that we can perform operations on a device (do a ping) */ -int dm_check_operations(struct dm_test_state *dms, struct device *dev, +int dm_check_operations(struct dm_test_state *dms, struct udevice *dev, uint32_t base, struct dm_test_priv *priv) { int expected; @@ -311,7 +311,7 @@ int dm_check_operations(struct dm_test_state *dms, struct device *dev, /* Check that we can perform operations on devices */ static int dm_test_operations(struct dm_test_state *dms) { - struct device *dev; + struct udevice *dev; int i; /* @@ -341,7 +341,7 @@ DM_TEST(dm_test_operations, DM_TESTF_SCAN_PDATA); /* Remove all drivers and check that things work */ static int dm_test_remove(struct dm_test_state *dms) { - struct device *dev; + struct udevice *dev; int i; for (i = 0; i < 3; i++) { @@ -367,7 +367,7 @@ static int dm_test_leak(struct dm_test_state *dms) for (i = 0; i < 2; i++) { struct mallinfo start, end; - struct device *dev; + struct udevice *dev; int ret; int id; @@ -435,10 +435,10 @@ DM_TEST(dm_test_uclass, 0); * this array. * @return 0 if OK, -ve on error */ -static int create_children(struct dm_test_state *dms, struct device *parent, - int count, int key, struct device *child[]) +static int create_children(struct dm_test_state *dms, struct udevice *parent, + int count, int key, struct udevice *child[]) { - struct device *dev; + struct udevice *dev; int i; for (i = 0; i < count; i++) { @@ -460,10 +460,10 @@ static int create_children(struct dm_test_state *dms, struct device *parent, static int dm_test_children(struct dm_test_state *dms) { - struct device *top[NODE_COUNT]; - struct device *child[NODE_COUNT]; - struct device *grandchild[NODE_COUNT]; - struct device *dev; + struct udevice *top[NODE_COUNT]; + struct udevice *child[NODE_COUNT]; + struct udevice *grandchild[NODE_COUNT]; + struct udevice *dev; int total; int ret; int i; diff --git a/test/dm/gpio.c b/test/dm/gpio.c index bf632bca5..2b2b0b51f 100644 --- a/test/dm/gpio.c +++ b/test/dm/gpio.c @@ -17,7 +17,7 @@ static int dm_test_gpio(struct dm_test_state *dms) { unsigned int offset, gpio; struct dm_gpio_ops *ops; - struct device *dev; + struct udevice *dev; const char *name; int offset_count; char buf[80]; diff --git a/test/dm/test-driver.c b/test/dm/test-driver.c index c4be8a12d..0f1a37b36 100644 --- a/test/dm/test-driver.c +++ b/test/dm/test-driver.c @@ -18,7 +18,7 @@ int dm_testdrv_op_count[DM_TEST_OP_COUNT]; static struct dm_test_state *dms = &global_test_state; -static int testdrv_ping(struct device *dev, int pingval, int *pingret) +static int testdrv_ping(struct udevice *dev, int pingval, int *pingret) { const struct dm_test_pdata *pdata = dev_get_platdata(dev); struct dm_test_priv *priv = dev_get_priv(dev); @@ -33,7 +33,7 @@ static const struct test_ops test_ops = { .ping = testdrv_ping, }; -static int test_bind(struct device *dev) +static int test_bind(struct udevice *dev) { /* Private data should not be allocated */ ut_assert(!dev_get_priv(dev)); @@ -42,7 +42,7 @@ static int test_bind(struct device *dev) return 0; } -static int test_probe(struct device *dev) +static int test_probe(struct udevice *dev) { struct dm_test_priv *priv = dev_get_priv(dev); @@ -54,7 +54,7 @@ static int test_probe(struct device *dev) return 0; } -static int test_remove(struct device *dev) +static int test_remove(struct udevice *dev) { /* Private data should still be allocated */ ut_assert(dev_get_priv(dev)); @@ -63,7 +63,7 @@ static int test_remove(struct device *dev) return 0; } -static int test_unbind(struct device *dev) +static int test_unbind(struct udevice *dev) { /* Private data should not be allocated */ ut_assert(!dev->priv); @@ -94,7 +94,7 @@ U_BOOT_DRIVER(test2_drv) = { .priv_auto_alloc_size = sizeof(struct dm_test_priv), }; -static int test_manual_drv_ping(struct device *dev, int pingval, int *pingret) +static int test_manual_drv_ping(struct udevice *dev, int pingval, int *pingret) { *pingret = pingval + 2; @@ -105,14 +105,14 @@ static const struct test_ops test_manual_ops = { .ping = test_manual_drv_ping, }; -static int test_manual_bind(struct device *dev) +static int test_manual_bind(struct udevice *dev) { dm_testdrv_op_count[DM_TEST_OP_BIND]++; return 0; } -static int test_manual_probe(struct device *dev) +static int test_manual_probe(struct udevice *dev) { dm_testdrv_op_count[DM_TEST_OP_PROBE]++; if (!dms->force_fail_alloc) @@ -123,13 +123,13 @@ static int test_manual_probe(struct device *dev) return 0; } -static int test_manual_remove(struct device *dev) +static int test_manual_remove(struct udevice *dev) { dm_testdrv_op_count[DM_TEST_OP_REMOVE]++; return 0; } -static int test_manual_unbind(struct device *dev) +static int test_manual_unbind(struct udevice *dev) { dm_testdrv_op_count[DM_TEST_OP_UNBIND]++; return 0; diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c index e1d982fd7..6eccf1112 100644 --- a/test/dm/test-fdt.c +++ b/test/dm/test-fdt.c @@ -18,7 +18,7 @@ DECLARE_GLOBAL_DATA_PTR; -static int testfdt_drv_ping(struct device *dev, int pingval, int *pingret) +static int testfdt_drv_ping(struct udevice *dev, int pingval, int *pingret) { const struct dm_test_pdata *pdata = dev->platdata; struct dm_test_priv *priv = dev_get_priv(dev); @@ -33,7 +33,7 @@ static const struct test_ops test_ops = { .ping = testfdt_drv_ping, }; -static int testfdt_ofdata_to_platdata(struct device *dev) +static int testfdt_ofdata_to_platdata(struct udevice *dev) { struct dm_test_pdata *pdata = dev_get_platdata(dev); @@ -44,7 +44,7 @@ static int testfdt_ofdata_to_platdata(struct device *dev) return 0; } -static int testfdt_drv_probe(struct device *dev) +static int testfdt_drv_probe(struct udevice *dev) { struct dm_test_priv *priv = dev_get_priv(dev); @@ -75,7 +75,7 @@ U_BOOT_DRIVER(testfdt_drv) = { }; /* From here is the testfdt uclass code */ -int testfdt_ping(struct device *dev, int pingval, int *pingret) +int testfdt_ping(struct udevice *dev, int pingval, int *pingret) { const struct test_ops *ops = device_get_ops(dev); @@ -94,7 +94,7 @@ UCLASS_DRIVER(testfdt) = { static int dm_test_fdt(struct dm_test_state *dms) { const int num_drivers = 3; - struct device *dev; + struct udevice *dev; struct uclass *uc; int ret; int i; diff --git a/test/dm/test-main.c b/test/dm/test-main.c index 828ed46f8..fbdae688e 100644 --- a/test/dm/test-main.c +++ b/test/dm/test-main.c @@ -32,7 +32,7 @@ static int dm_test_init(struct dm_test_state *dms) /* Ensure all the test devices are probed */ static int do_autoprobe(struct dm_test_state *dms) { - struct device *dev; + struct udevice *dev; int ret; /* Scanning the uclass is enough to probe all the devices */ diff --git a/test/dm/test-uclass.c b/test/dm/test-uclass.c index 8b564b89d..017e09792 100644 --- a/test/dm/test-uclass.c +++ b/test/dm/test-uclass.c @@ -18,7 +18,7 @@ static struct dm_test_state *dms = &global_test_state; -int test_ping(struct device *dev, int pingval, int *pingret) +int test_ping(struct udevice *dev, int pingval, int *pingret) { const struct test_ops *ops = device_get_ops(dev); @@ -28,24 +28,25 @@ int test_ping(struct device *dev, int pingval, int *pingret) return ops->ping(dev, pingval, pingret); } -static int test_post_bind(struct device *dev) +static int test_post_bind(struct udevice *dev) { dm_testdrv_op_count[DM_TEST_OP_POST_BIND]++; return 0; } -static int test_pre_unbind(struct device *dev) +static int test_pre_unbind(struct udevice *dev) { dm_testdrv_op_count[DM_TEST_OP_PRE_UNBIND]++; return 0; } -static int test_post_probe(struct device *dev) +static int test_post_probe(struct udevice *dev) { - struct device *prev = list_entry(dev->uclass_node.prev, struct device, - uclass_node); + struct udevice *prev = list_entry(dev->uclass_node.prev, + struct udevice, uclass_node); + struct dm_test_uclass_perdev_priv *priv = dev->uclass_priv; struct uclass *uc = dev->uclass; @@ -68,7 +69,7 @@ static int test_post_probe(struct device *dev) return 0; } -static int test_pre_remove(struct device *dev) +static int test_pre_remove(struct udevice *dev) { dm_testdrv_op_count[DM_TEST_OP_PRE_REMOVE]++; diff --git a/tools/.gitignore b/tools/.gitignore index b1e997fc3..725db906e 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -11,6 +11,7 @@ /mkexynosspl /mpc86x_clk /mxsboot +/mksunxiboot /ncb /proftool /relocate-rela diff --git a/tools/Makefile b/tools/Makefile index 6e43a0150..761055764 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -38,6 +38,8 @@ ENVCRC-$(CONFIG_ENV_IS_IN_NVRAM) = y ENVCRC-$(CONFIG_ENV_IS_IN_SPI_FLASH) = y CONFIG_BUILD_ENVCRC ?= $(ENVCRC-y) +hostprogs-$(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER) += atmel_pmecc_params$(SFX) + # TODO: CONFIG_CMD_LICENSE does not work hostprogs-$(CONFIG_CMD_LICENSE) += bin2header$(SFX) hostprogs-$(CONFIG_LCD_LOGO) += bmp_logo$(SFX) @@ -69,6 +71,7 @@ RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := rsa-sign.o rsa-verify.o rsa-checksum.o # common objs for dumpimage and mkimage dumpimage-mkimage-objs := aisimage.o \ + atmelimage.o \ $(FIT_SIG_OBJS-y) \ crc32.o \ default_image.o \ @@ -131,6 +134,8 @@ hostprogs-$(CONFIG_MX23) += mxsboot$(SFX) hostprogs-$(CONFIG_MX28) += mxsboot$(SFX) HOSTCFLAGS_mxsboot$(SFX).o := -pedantic +hostprogs-$(CONFIG_SUNXI) += mksunxiboot$(SFX) + hostprogs-$(CONFIG_NETCONSOLE) += ncb$(SFX) hostprogs-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX) diff --git a/tools/atmel_pmecc_params.c b/tools/atmel_pmecc_params.c new file mode 100644 index 000000000..8eaf27f80 --- /dev/null +++ b/tools/atmel_pmecc_params.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2014 Andreas Bießmann <andreas.devel@googlemail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This is a host tool for generating an appropriate string out of board + * configuration. The string is required for correct generation of PMECC + * header which in turn is required for NAND flash booting of Atmel AT91 style + * hardware. + * + * See doc/README.atmel_pmecc for more information. + */ + +#include <config.h> +#include <stdlib.h> + +static int pmecc_get_ecc_bytes(int cap, int sector_size) +{ + int m = 12 + sector_size / 512; + return (m * cap + 7) / 8; +} + +int main(int argc, char *argv[]) +{ + unsigned int use_pmecc = 0; + unsigned int sector_per_page; + unsigned int sector_size = CONFIG_PMECC_SECTOR_SIZE; + unsigned int oob_size = CONFIG_SYS_NAND_OOBSIZE; + unsigned int ecc_bits = CONFIG_PMECC_CAP; + unsigned int ecc_offset; + +#ifdef CONFIG_ATMEL_NAND_HW_PMECC + use_pmecc = 1; +#endif + + sector_per_page = CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_PMECC_SECTOR_SIZE; + ecc_offset = oob_size - + pmecc_get_ecc_bytes(ecc_bits, sector_size) * sector_per_page; + + printf("usePmecc=%d,", use_pmecc); + printf("sectorPerPage=%d,", sector_per_page); + printf("sectorSize=%d,", sector_size); + printf("spareSize=%d,", oob_size); + printf("eccBits=%d,", ecc_bits); + printf("eccOffset=%d", ecc_offset); + printf("\n"); + + exit(EXIT_SUCCESS); +} diff --git a/tools/atmelimage.c b/tools/atmelimage.c new file mode 100644 index 000000000..c8101d2dd --- /dev/null +++ b/tools/atmelimage.c @@ -0,0 +1,342 @@ +/* + * (C) Copyright 2014 + * Andreas Bießmann <andreas.devel@googlemail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "imagetool.h" +#include "mkimage.h" + +#include <image.h> + +#define pr_err(fmt, args...) fprintf(stderr, "atmelimage Error: " fmt, ##args) + +static int atmel_check_image_type(uint8_t type) +{ + if (type == IH_TYPE_ATMELIMAGE) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +static uint32_t nand_pmecc_header[52]; + +/* + * A helper struct for parsing the mkimage -n parameter + * + * Keep in same order as the configs array! + */ +static struct pmecc_config { + int use_pmecc; + int sector_per_page; + int spare_size; + int ecc_bits; + int sector_size; + int ecc_offset; +} pmecc; + +/* + * Strings used for configure the PMECC header via -n mkimage switch + * + * We estimate a coma separated list of key=value pairs. The mkimage -n + * parameter argument should not contain any whitespace. + * + * Keep in same order as struct pmecc_config! + */ +static const char * const configs[] = { + "usePmecc", + "sectorPerPage", + "spareSize", + "eccBits", + "sectorSize", + "eccOffset" +}; + +static int atmel_find_pmecc_parameter_in_token(const char *token) +{ + size_t pos; + char *param; + + debug("token: '%s'\n", token); + + for (pos = 0; pos < ARRAY_SIZE(configs); pos++) { + if (strncmp(token, configs[pos], strlen(configs[pos])) == 0) { + param = strstr(token, "="); + if (!param) + goto err; + + param++; + debug("\t%s parameter: '%s'\n", configs[pos], param); + + switch (pos) { + case 0: + pmecc.use_pmecc = strtol(param, NULL, 10); + return EXIT_SUCCESS; + case 1: + pmecc.sector_per_page = strtol(param, NULL, 10); + return EXIT_SUCCESS; + case 2: + pmecc.spare_size = strtol(param, NULL, 10); + return EXIT_SUCCESS; + case 3: + pmecc.ecc_bits = strtol(param, NULL, 10); + return EXIT_SUCCESS; + case 4: + pmecc.sector_size = strtol(param, NULL, 10); + return EXIT_SUCCESS; + case 5: + pmecc.ecc_offset = strtol(param, NULL, 10); + return EXIT_SUCCESS; + } + } + } + +err: + pr_err("Could not find parameter in token '%s'\n", token); + return EXIT_FAILURE; +} + +static int atmel_parse_pmecc_params(char *txt) +{ + char *token; + + token = strtok(txt, ","); + while (token != NULL) { + if (atmel_find_pmecc_parameter_in_token(token)) + return EXIT_FAILURE; + + token = strtok(NULL, ","); + } + + return EXIT_SUCCESS; +} + +static int atmel_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + uint32_t *ints = (uint32_t *)ptr; + size_t pos; + size_t size = image_size; + + /* check if we have an PMECC header attached */ + for (pos = 0; pos < ARRAY_SIZE(nand_pmecc_header); pos++) + if (ints[pos] >> 28 != 0xC) + break; + + if (pos == ARRAY_SIZE(nand_pmecc_header)) { + ints += ARRAY_SIZE(nand_pmecc_header); + size -= sizeof(nand_pmecc_header); + } + + /* check the seven interrupt vectors of binary */ + for (pos = 0; pos < 7; pos++) { + debug("atmelimage: interrupt vector #%d is 0x%08X\n", pos+1, + ints[pos]); + /* + * all vectors except the 6'th one must contain valid + * LDR or B Opcode + */ + if (pos == 5) + /* 6'th vector has image size set, check later */ + continue; + if ((ints[pos] & 0xff000000) == 0xea000000) + /* valid B Opcode */ + continue; + if ((ints[pos] & 0xfffff000) == 0xe59ff000) + /* valid LDR (I=0, P=1, U=1, B=0, W=0, L=1) */ + continue; + /* ouch, one of the checks has missed ... */ + return 1; + } + + return ints[5] != cpu_to_le32(size); +} + +static void atmel_print_pmecc_header(const uint32_t word) +{ + int val; + + printf("\t\tPMECC header\n"); + + printf("\t\t====================\n"); + + val = (word >> 18) & 0x1ff; + printf("\t\teccOffset: %9i\n", val); + + val = (((word >> 16) & 0x3) == 0) ? 512 : 1024; + printf("\t\tsectorSize: %8i\n", val); + + if (((word >> 13) & 0x7) <= 2) + val = (2 << ((word >> 13) & 0x7)); + else + val = (12 << (((word >> 13) & 0x7) - 3)); + printf("\t\teccBitReq: %9i\n", val); + + val = (word >> 4) & 0x1ff; + printf("\t\tspareSize: %9i\n", val); + + val = (1 << ((word >> 1) & 0x3)); + printf("\t\tnbSectorPerPage: %3i\n", val); + + printf("\t\tusePmecc: %10i\n", word & 0x1); + printf("\t\t====================\n"); +} + +static void atmel_print_header(const void *ptr) +{ + uint32_t *ints = (uint32_t *)ptr; + size_t pos; + + /* check if we have an PMECC header attached */ + for (pos = 0; pos < ARRAY_SIZE(nand_pmecc_header); pos++) + if (ints[pos] >> 28 != 0xC) + break; + + if (pos == ARRAY_SIZE(nand_pmecc_header)) { + printf("Image Type:\tATMEL ROM-Boot Image with PMECC Header\n"); + atmel_print_pmecc_header(ints[0]); + pos += 5; + } else { + printf("Image Type:\tATMEL ROM-Boot Image without PMECC Header\n"); + pos = 5; + } + printf("\t\t6'th vector has %u set\n", le32_to_cpu(ints[pos])); +} + +static void atmel_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + /* just save the image size into 6'th interrupt vector */ + uint32_t *ints = (uint32_t *)ptr; + size_t cnt; + size_t pos = 5; + size_t size = sbuf->st_size; + + for (cnt = 0; cnt < ARRAY_SIZE(nand_pmecc_header); cnt++) + if (ints[cnt] >> 28 != 0xC) + break; + + if (cnt == ARRAY_SIZE(nand_pmecc_header)) { + pos += ARRAY_SIZE(nand_pmecc_header); + size -= sizeof(nand_pmecc_header); + } + + ints[pos] = cpu_to_le32(size); +} + +static int atmel_check_params(struct image_tool_params *params) +{ + if (strlen(params->imagename) > 0) + if (atmel_parse_pmecc_params(params->imagename)) + return EXIT_FAILURE; + + return !(!params->eflag && + !params->fflag && + !params->xflag && + ((params->dflag && !params->lflag) || + (params->lflag && !params->dflag))); +} + +static int atmel_vrec_header(struct image_tool_params *params, + struct image_type_params *tparams) +{ + uint32_t tmp; + size_t pos; + + if (strlen(params->imagename) == 0) + return EXIT_SUCCESS; + + tmp = 0xC << 28; + + tmp |= (pmecc.ecc_offset & 0x1ff) << 18; + + switch (pmecc.sector_size) { + case 512: + tmp |= 0 << 16; + break; + case 1024: + tmp |= 1 << 16; + break; + + default: + pr_err("Wrong sectorSize (%i) for PMECC header\n", + pmecc.sector_size); + return EXIT_FAILURE; + } + + switch (pmecc.ecc_bits) { + case 2: + tmp |= 0 << 13; + break; + case 4: + tmp |= 1 << 13; + break; + case 8: + tmp |= 2 << 13; + break; + case 12: + tmp |= 3 << 13; + break; + case 24: + tmp |= 4 << 13; + break; + + default: + pr_err("Wrong eccBits (%i) for PMECC header\n", + pmecc.ecc_bits); + return EXIT_FAILURE; + } + + tmp |= (pmecc.spare_size & 0x1ff) << 4; + + switch (pmecc.sector_per_page) { + case 1: + tmp |= 0 << 1; + break; + case 2: + tmp |= 1 << 1; + break; + case 4: + tmp |= 2 << 1; + break; + case 8: + tmp |= 3 << 1; + break; + + default: + pr_err("Wrong sectorPerPage (%i) for PMECC header\n", + pmecc.sector_per_page); + return EXIT_FAILURE; + } + + if (pmecc.use_pmecc) + tmp |= 1; + + for (pos = 0; pos < ARRAY_SIZE(nand_pmecc_header); pos++) + nand_pmecc_header[pos] = tmp; + + debug("PMECC header filled 52 times with 0x%08X\n", tmp); + + tparams->header_size = sizeof(nand_pmecc_header); + tparams->hdr = nand_pmecc_header; + + return EXIT_SUCCESS; +} + +static struct image_type_params atmelimage_params = { + .name = "ATMEL ROM-Boot Image support", + .header_size = 0, + .hdr = NULL, + .check_image_type = atmel_check_image_type, + .verify_header = atmel_verify_header, + .print_header = atmel_print_header, + .set_header = atmel_set_header, + .check_params = atmel_check_params, + .vrec_header = atmel_vrec_header, +}; + +void init_atmel_image_type(void) +{ + register_image_type(&atmelimage_params); +} diff --git a/tools/imagetool.c b/tools/imagetool.c index da72115e5..32d6278ed 100644 --- a/tools/imagetool.c +++ b/tools/imagetool.c @@ -27,6 +27,8 @@ void register_image_tool(imagetool_register_t image_register) */ register_func = image_register; + /* Init ATMEL ROM Boot Image generation/list support */ + init_atmel_image_type(); /* Init Freescale PBL Boot image generation/list support */ init_pbl_image_type(); /* Init Kirkwood Boot image generation/list support */ diff --git a/tools/imagetool.h b/tools/imagetool.h index a3e9d302e..c480687ec 100644 --- a/tools/imagetool.h +++ b/tools/imagetool.h @@ -159,6 +159,7 @@ void register_image_type(struct image_type_params *tparams); * Supported image types init functions */ void init_default_image_type(void); +void init_atmel_image_type(void); void init_pbl_image_type(void); void init_ais_image_type(void); void init_kwb_image_type(void); diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c new file mode 100644 index 000000000..da7c9f0dd --- /dev/null +++ b/tools/mksunxiboot.c @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * a simple tool to generate bootable image for sunxi platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <fcntl.h> +#include <stdio.h> +#include <unistd.h> +#include <stdlib.h> +#include <string.h> +#include <errno.h> +#include <sys/types.h> +#include <sys/stat.h> + +/* boot head definition from sun4i boot code */ +struct boot_file_head { + uint32_t b_instruction; /* one intruction jumping to real code */ + uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */ + uint32_t check_sum; /* generated by PC */ + uint32_t length; /* generated by PC */ + /* + * We use a simplified header, only filling in what is needed + * by the boot ROM. To be compatible with Allwinner tools we + * would need to implement the proper fields here instead of + * padding. + */ + uint8_t pad[12]; /* align to 32 bytes */ +}; + +#define BOOT0_MAGIC "eGON.BT0" +#define STAMP_VALUE 0x5F0A6C39 + +/* check sum functon from sun4i boot code */ +int gen_check_sum(struct boot_file_head *head_p) +{ + uint32_t length; + uint32_t *buf; + uint32_t loop; + uint32_t i; + uint32_t sum; + + length = head_p->length; + if ((length & 0x3) != 0) /* must 4-byte-aligned */ + return -1; + buf = (uint32_t *)head_p; + head_p->check_sum = STAMP_VALUE; /* fill stamp */ + loop = length >> 2; + + /* calculate the sum */ + for (i = 0, sum = 0; i < loop; i++) + sum += buf[i]; + + /* write back check sum */ + head_p->check_sum = sum; + + return 0; +} + +#define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a)-1) +#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask)) + +#define SUN4I_SRAM_SIZE 0x7600 /* 0x7748+ is used by BROM */ +#define SRAM_LOAD_MAX_SIZE (SUN4I_SRAM_SIZE - sizeof(struct boot_file_head)) +#define BLOCK_SIZE 512 + +struct boot_img { + struct boot_file_head header; + char code[SRAM_LOAD_MAX_SIZE]; + char pad[BLOCK_SIZE]; +}; + +int main(int argc, char *argv[]) +{ + int fd_in, fd_out; + struct boot_img img; + unsigned file_size, load_size; + int count; + + if (argc < 2) { + printf("\tThis program makes an input bin file to sun4i " \ + "bootable image.\n" \ + "\tUsage: %s input_file out_putfile\n", argv[0]); + return EXIT_FAILURE; + } + + fd_in = open(argv[1], O_RDONLY); + if (fd_in < 0) { + perror("Open input file"); + return EXIT_FAILURE; + } + + memset(img.pad, 0, BLOCK_SIZE); + + /* get input file size */ + file_size = lseek(fd_in, 0, SEEK_END); + + if (file_size > SRAM_LOAD_MAX_SIZE) { + fprintf(stderr, "ERROR: File too large!\n"); + return EXIT_FAILURE; + } else { + load_size = ALIGN(file_size, sizeof(int)); + } + + fd_out = open(argv[2], O_WRONLY | O_CREAT, 0666); + if (fd_out < 0) { + perror("Open output file"); + return EXIT_FAILURE; + } + + /* read file to buffer to calculate checksum */ + lseek(fd_in, 0, SEEK_SET); + count = read(fd_in, img.code, load_size); + if (count != load_size) { + perror("Reading input image"); + return EXIT_FAILURE; + } + + /* fill the header */ + img.header.b_instruction = /* b instruction */ + 0xEA000000 | /* jump to the first instr after the header */ + ((sizeof(struct boot_file_head) / sizeof(int) - 2) + & 0x00FFFFFF); + memcpy(img.header.magic, BOOT0_MAGIC, 8); /* no '0' termination */ + img.header.length = + ALIGN(load_size + sizeof(struct boot_file_head), BLOCK_SIZE); + gen_check_sum(&img.header); + + count = write(fd_out, &img, img.header.length); + if (count != img.header.length) { + perror("Writing output"); + return EXIT_FAILURE; + } + + close(fd_in); + close(fd_out); + + return EXIT_SUCCESS; +} |