diff options
Diffstat (limited to 'drivers/hisi/hifi_mailbox/mailbox/drv_mailbox_cfg.h')
| -rw-r--r-- | drivers/hisi/hifi_mailbox/mailbox/drv_mailbox_cfg.h | 646 |
1 files changed, 646 insertions, 0 deletions
diff --git a/drivers/hisi/hifi_mailbox/mailbox/drv_mailbox_cfg.h b/drivers/hisi/hifi_mailbox/mailbox/drv_mailbox_cfg.h new file mode 100644 index 000000000000..a4329c5c7b87 --- /dev/null +++ b/drivers/hisi/hifi_mailbox/mailbox/drv_mailbox_cfg.h @@ -0,0 +1,646 @@ + +#ifndef __DRV_MAILBOX_CFG_H__ +#define __DRV_MAILBOX_CFG_H__ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#include "../../drivers/hisi/hifi_dsp/hifi_lpp.h" +#include "mdrv_ipc_enum.h" + +#define MAILBOX_CHANNEL_BEGIN(src, dst) \ + enum MAILBOX_CHANNEL_##src##2##dst##_ENUM \ + { \ + MAILBOX_CHANNEL_##src##2##dst##_RSERVED = -1, + +#define MAILBOX_CHANNEL_ITEM(src, dst, channel) \ + MAILBOX_CHANNEL_##src##2##dst##_##channel + +#define MAILBOX_CHANNEL_END(src, dst) \ + MAILBOX_CHANNEL_##src##2##dst##_BUTT \ + }; + + /* CCPU -> HIFI */ + MAILBOX_CHANNEL_BEGIN(CCPU, HIFI) + MAILBOX_CHANNEL_ITEM(CCPU, HIFI, MSG), MAILBOX_CHANNEL_END(CCPU, HIFI) + + /* CCPU -> MCU */ + MAILBOX_CHANNEL_BEGIN(CCPU, MCU) + MAILBOX_CHANNEL_ITEM(CCPU, MCU, MSG), + MAILBOX_CHANNEL_ITEM(CCPU, MCU, IFC), MAILBOX_CHANNEL_END(CCPU, MCU) + + /* CCPU -> ACPU */ + MAILBOX_CHANNEL_BEGIN(CCPU, ACPU) + MAILBOX_CHANNEL_ITEM(CCPU, ACPU, MSG), + MAILBOX_CHANNEL_ITEM(CCPU, ACPU, IFC), + MAILBOX_CHANNEL_END(CCPU, ACPU) + + /* ACPU -> CCPU */ + MAILBOX_CHANNEL_BEGIN(ACPU, CCPU) + MAILBOX_CHANNEL_ITEM(ACPU, CCPU, MSG), + MAILBOX_CHANNEL_ITEM(ACPU, CCPU, IFC), + MAILBOX_CHANNEL_END(ACPU, CCPU) + + /* ACPU -> MCU */ + MAILBOX_CHANNEL_BEGIN(ACPU, MCU) + MAILBOX_CHANNEL_ITEM(ACPU, MCU, MSG), + MAILBOX_CHANNEL_ITEM(ACPU, MCU, IFC), MAILBOX_CHANNEL_END(ACPU, MCU) + + /* ACPU -> HIFI */ + MAILBOX_CHANNEL_BEGIN(ACPU, HIFI) + MAILBOX_CHANNEL_ITEM(ACPU, HIFI, MSG), MAILBOX_CHANNEL_END(ACPU, HIFI) + + /* HIFI -> ACPU */ + MAILBOX_CHANNEL_BEGIN(HIFI, ACPU) + MAILBOX_CHANNEL_ITEM(HIFI, ACPU, MSG), MAILBOX_CHANNEL_END(HIFI, ACPU) + + /* HIFI -> CCPU */ + MAILBOX_CHANNEL_BEGIN(HIFI, CCPU) + MAILBOX_CHANNEL_ITEM(HIFI, CCPU, MSG), MAILBOX_CHANNEL_END(HIFI, CCPU) + + /* HIFI -> BBE16 */ + MAILBOX_CHANNEL_BEGIN(HIFI, BBE16) + MAILBOX_CHANNEL_ITEM(HIFI, BBE16, MSG), MAILBOX_CHANNEL_END(HIFI, BBE16) + + /* MCU -> ACPU */ + MAILBOX_CHANNEL_BEGIN(MCU, ACPU) + MAILBOX_CHANNEL_ITEM(MCU, ACPU, MSG), + MAILBOX_CHANNEL_ITEM(MCU, ACPU, IFC), MAILBOX_CHANNEL_END(MCU, ACPU) + + /* MCU -> CCPU */ + MAILBOX_CHANNEL_BEGIN(MCU, CCPU) + MAILBOX_CHANNEL_ITEM(MCU, CCPU, MSG), + MAILBOX_CHANNEL_ITEM(MCU, CCPU, IFC), MAILBOX_CHANNEL_END(MCU, CCPU) + + /* BBE16 -> HIFI */ + MAILBOX_CHANNEL_BEGIN(BBE16, HIFI) + MAILBOX_CHANNEL_ITEM(BBE16, HIFI, MSG), MAILBOX_CHANNEL_END(BBE16, HIFI) + + enum MAILBOX_GAP_FOR_SI_PARSE { MAILBOX_GAP_FOR_SI_BUTT }; + +#define MAILBOX_ID_SRC_CPU_OFFSET (24) +#define MAILBOX_ID_DST_CPU_OFFSET (16) +#define MAILBOX_ID_CHANNEL_OFFSET (8) + +#define MAILBOX_MAILCODE_CHANNEL(src, dst, channel) \ + (((unsigned int)(src) << MAILBOX_ID_SRC_CPU_OFFSET) \ + | ((unsigned int)(dst) << MAILBOX_ID_DST_CPU_OFFSET) \ + | ((unsigned int)(channel) << MAILBOX_ID_CHANNEL_OFFSET)) + +#define MAILBOX_CPUID(cpu) MAILBOX_CPUID_##cpu + +#define MAILBOX_MAILCODE_RESERVED(src, dst, channel) \ + MAILBOX_MAILCODE_CHANNEL(MAILBOX_CPUID(src), \ + MAILBOX_CPUID(dst), \ + MAILBOX_CHANNEL_ITEM(src, dst, channel)) + +#define MAILBOX_MAILCODE_ITEM_RESERVED(src, dst, channel) \ + MAILBOX_MAILCODE_##src##2##dst##_##channel##_RESERVED + +#define MAILBOX_MAILCODE_ITEM_END(src, dst, channel) \ + MAILBOX_MAILCODE_##src##2##dst##_##channel##_BUTT + +#define MAILBOX_MAILCODE_ITEM_BEGIN(src, dst, channel) \ + MAILBOX_MAILCODE_ITEM_RESERVED(src, dst, channel) = MAILBOX_MAILCODE_RESERVED(src, dst, channel) + + enum MAILBOX_CPUID_ENUM { + MAILBOX_CPUID_RESERVED = -1, + MAILBOX_CPUID_ACPU = IPC_CORE_ACORE, + MAILBOX_CPUID_CCPU = IPC_CORE_CCORE, + MAILBOX_CPUID_MCU = IPC_CORE_ACORE, + MAILBOX_CPUID_BBE16 = IPC_CORE_LDSP, + MAILBOX_CPUID_HIFI = IPC_CORE_HiFi, + MAILBOX_CPUID_BUTT + }; + + enum MAILBOX_MAILCODE_ENUM { + MAILBOX_MAILCODE_ITEM_BEGIN(CCPU, MCU, MSG), + MAILBOX_MAILCODE_CCPU_TO_MCU_VOS_MSG_NORMAL, + MAILBOX_MAILCODE_CCPU_TO_MCU_VOS_MSG_URGENT, + BSP_MAILBOX_CHANNEL_CCPU_TO_MCU_MCA_CH, + + MAILBOX_MAILCODE_ITEM_END(CCPU, MCU, MSG), + + MAILBOX_MAILCODE_ITEM_BEGIN(CCPU, MCU, IFC), + MAILBOX_IFC_CCPU_TO_MCU_TEST_CMP, + MAILBOX_IFC_CCPU_TO_MCU_TEST, + MAILBOX_IFC_CCPU_TO_MCU_MCA, + MAILBOX_MAILCODE_ITEM_END(CCPU, MCU, IFC), + + MAILBOX_MAILCODE_ITEM_BEGIN(CCPU, HIFI, MSG), + MAILBOX_MAILCODE_CCPU_TO_HIFI_VOS_MSG_NORMAL, + MAILBOX_MAILCODE_CCPU_TO_HIFI_VOS_MSG_URGENT, + MAILBOX_MAILCODE_ITEM_END(CCPU, HIFI, MSG), + + MAILBOX_MAILCODE_ITEM_BEGIN(CCPU, ACPU, MSG), + MAILBOX_MAILCODE_ITEM_END(CCPU, ACPU, MSG), + + MAILBOX_MAILCODE_ITEM_BEGIN(CCPU, ACPU, IFC), + MAILBOX_IFC_CCPU_TO_ACPU_TEST_CMP, + MAILBOX_IFC_CCPU_TO_ACPU_TEST, + MAILBOX_IFC_CCPU_TO_ACPU_PRINT, + MAILBOX_IFC_CCPU_TO_ACPU_FOPEN, + MAILBOX_IFC_CCPU_TO_ACPU_FCLOSE, + MAILBOX_IFC_CCPU_TO_ACPU_FREAD, + MAILBOX_IFC_CCPU_TO_ACPU_FWRITE, + MAILBOX_IFC_CCPU_TO_ACPU_FSEEK, + MAILBOX_IFC_CCPU_TO_ACPU_REMOVE, + MAILBOX_IFC_CCPU_TO_ACPU_FTELL, + MAILBOX_IFC_CCPU_TO_ACPU_RENAME, + MAILBOX_IFC_CCPU_TO_ACPU_ACCESS, + MAILBOX_IFC_CCPU_TO_ACPU_MKDIR, + MAILBOX_IFC_CCPU_TO_ACPU_RMDIR, + MAILBOX_IFC_ACPU_TO_CCPU_PMIC_IRQEVENT_REPO, + MAILBOX_MAILCODE_ITEM_END(CCPU, ACPU, IFC), + + MAILBOX_MAILCODE_ITEM_BEGIN(ACPU, MCU, MSG), + MAILBOX_MAILCODE_ACPU_TO_MCU_VOS_MSG_NORMAL, + MAILBOX_MAILCODE_ACPU_TO_MCU_VOS_MSG_URGENT, + BSP_MAILBOX_CHANNEL_ACPU_TO_MCU_IFC_CH, + BSP_MAILBOX_CHANNEL_ACPU_TO_MCU_IFC_RESPONSE_CH, + BSP_MAILBOX_CHANNEL_ACPU_TO_MCU_SENSOR_CH, + BSP_MAILBOX_CHANNEL_ACPU_TO_MCU_TP_CH, + BSP_MAILBOX_CHANNEL_ACPU_TO_MCU_MCA_CH, + BSP_MAILBOX_CHANNEL_ACPU_TO_MCU_RST_CH, + MAILBOX_MAILCODE_ITEM_END(ACPU, MCU, MSG), + + MAILBOX_MAILCODE_ITEM_BEGIN(ACPU, MCU, IFC), + MAILBOX_IFC_ACPU_TO_MCU_TEST_CMP, + MAILBOX_IFC_ACPU_TO_MCU_TEST, + MAILBOX_IFC_ACPU_TO_MCU_HUTAF_HLT, + MAILBOX_IFC_ACPU_TO_MCU_MCA, + MAILBOX_IFC_ACPU_TO_MCU_MNTN, + MAILBOX_IFC_ACPU_TO_MCU_RUN_CMD, + MAILBOX_MAILCODE_ITEM_END(ACPU, MCU, IFC), + + MAILBOX_MAILCODE_ITEM_BEGIN(ACPU, HIFI, MSG), + MAILBOX_MAILCODE_ACPU_TO_HIFI_VOS_MSG_NORMAL, + MAILBOX_MAILCODE_ACPU_TO_HIFI_VOS_MSG_URGENT, + MAILBOX_MAILCODE_ACPU_TO_HIFI_AUDIO, + MAILBOX_MAILCODE_ACPU_TO_HIFI_MISC, + MAILBOX_MAILCODE_ACPU_TO_HIFI_VOICE, + MAILBOX_MAILCODE_ACPU_TO_HIFI_VOICE_RT, + MAILBOX_MAILCODE_ACPU_TO_HIFI_CCORE_RESET_ID, + MAILBOX_MAILCODE_ITEM_END(ACPU, HIFI, MSG), + + MAILBOX_MAILCODE_ITEM_BEGIN(ACPU, CCPU, MSG), + MAILBOX_IFC_ACPU_TO_CCPU_CSHELL_START, + MAILBOX_MAILCODE_ITEM_END(ACPU, CCPU, MSG), + + MAILBOX_MAILCODE_ITEM_BEGIN(ACPU, CCPU, IFC), + MAILBOX_IFC_ACPU_TO_CCPU_TEST_CMP, + MAILBOX_IFC_ACPU_TO_CCPU_TEST, + MAILBOX_IFC_ACPU_TO_CCPU_PRINT, + MAILBOX_IFC_ACPU_TO_CCPU_FOPEN, + MAILBOX_IFC_ACPU_TO_CCPU_FCLOSE, + MAILBOX_IFC_ACPU_TO_CCPU_FREAD, + MAILBOX_IFC_ACPU_TO_CCPU_FWRITE, + MAILBOX_IFC_ACPU_TO_CCPU_FSEEK, + MAILBOX_IFC_ACPU_TO_CCPU_REMOVE, + MAILBOX_IFC_ACPU_TO_CCPU_FTELL, + MAILBOX_IFC_ACPU_TO_CCPU_RENAME, + MAILBOX_IFC_ACPU_TO_CCPU_ACCESS, + MAILBOX_IFC_ACPU_TO_CCPU_MKDIR, + MAILBOX_IFC_ACPU_TO_CCPU_RMDIR, + MAILBOX_IFC_ACPU_TO_CCPU_BASE_TEST2, + MAILBOX_IFC_ACPU_TO_CCPU_BASE_TEST1, + MAILBOX_IFC_ACPU_TO_CCPU_PMIC_IRQEVENT, + MAILBOX_IFC_ACPU_TO_CCPU_READ_EFUSE, + MAILBOX_IFC_ACPU_TO_CCPU_SYSTEMERROR, + MAILBOX_MAILCODE_ITEM_END(ACPU, CCPU, IFC), + + MAILBOX_MAILCODE_ITEM_BEGIN(HIFI, CCPU, MSG), + MAILBOX_MAILCODE_HIFI_TO_CCPU_VOS_MSG_NORMAL, + MAILBOX_MAILCODE_HIFI_TO_CCPU_VOS_MSG_URGENT, + MAILBOX_MAILCODE_ITEM_END(HIFI, CCPU, MSG), + + MAILBOX_MAILCODE_ITEM_BEGIN(HIFI, ACPU, MSG), + MAILBOX_MAILCODE_HIFI_TO_ACPU_VOS_MSG_NORMAL, + MAILBOX_MAILCODE_HIFI_TO_ACPU_VOS_MSG_URGENT, + MAILBOX_MAILCODE_HIFI_TO_ACPU_AUDIO, + MAILBOX_MAILCODE_HIFI_TO_ACPU_MISC, + MAILBOX_MAILCODE_HIFI_TO_ACPU_VOICE, + MAILBOX_MAILCODE_HIFI_TO_ACPU_CCORE_RESET_ID, + MAILBOX_MAILCODE_ITEM_END(HIFI, ACPU, MSG), + + MAILBOX_MAILCODE_ITEM_BEGIN(HIFI, BBE16, MSG), + MAILBOX_MAILCODE_HIFI_TO_BBE16_VOS_MSG_NORMAL, + MAILBOX_MAILCODE_HIFI_TO_BBE16_VOS_MSG_URGENT, + MAILBOX_MAILCODE_ITEM_END(HIFI, BBE16, MSG), + + MAILBOX_MAILCODE_ITEM_BEGIN(MCU, CCPU, MSG), + MAILBOX_MAILCODE_MCU_TO_CCPU_VOS_MSG_NORMAL, + MAILBOX_MAILCODE_MCU_TO_CCPU_VOS_MSG_URGENT, + BSP_MAILBOX_CHANNEL_MCU_TO_CCPU_MCA_CH, + MAILBOX_MAILCODE_ITEM_END(MCU, CCPU, MSG), + + MAILBOX_MAILCODE_ITEM_BEGIN(MCU, CCPU, IFC), + MAILBOX_IFC_MCU_TO_CCPU_TEST_CMP, + MAILBOX_IFC_MCU_TO_CCPU_BASE_TEST2, + MAILBOX_IFC_MCU_TO_CCPU_BASE_TEST1, + MAILBOX_IFC_MCU_TO_CCPU_TEST, + MAILBOX_MAILCODE_ITEM_END(MCU, CCPU, IFC), + + MAILBOX_MAILCODE_ITEM_BEGIN(MCU, ACPU, MSG), + MAILBOX_MAILCODE_MCU_TO_ACPU_VOS_MSG_NORMAL, + MAILBOX_MAILCODE_MCU_TO_ACPU_VOS_MSG_URGENT, + BSP_MAILBOX_CHANNEL_MCU_TO_ACPU_IFC_CH, + BSP_MAILBOX_CHANNEL_MCU_TO_ACPU_IFC_RESPONSE_CH, + BSP_MAILBOX_CHANNEL_MCU_TO_ACPU_SENSOR_CH, + BSP_MAILBOX_CHANNEL_MCU_TO_ACPU_TP_CH, + BSP_MAILBOX_CHANNEL_MCU_TO_ACPU_MCA_CH, + BSP_MAILBOX_CHANNEL_MCU_TO_ACPU_MNTN_CH, + MAILBOX_IFC_MCU_TO_ACPU_HUTAF_HLT, + MAILBOX_MAILCODE_MCU_TO_ACPU_CCORE_RESET_ID, + MAILBOX_MAILCODE_ITEM_END(MCU, ACPU, MSG), + + MAILBOX_MAILCODE_ITEM_BEGIN(MCU, ACPU, IFC), + MAILBOX_IFC_MCU_TO_ACPU_TEST_CMP, + MAILBOX_IFC_MCU_TO_ACPU_TEST, + MAILBOX_IFC_MCU_TO_ACPU_PRINT, + MAILBOX_MAILCODE_ITEM_END(MCU, ACPU, IFC), + + MAILBOX_MAILCODE_ITEM_BEGIN(BBE16, HIFI, MSG), + MAILBOX_MAILCODE_BBE16_TO_HIFI_VOS_MSG_NORMAL, + MAILBOX_MAILCODE_BBE16_TO_HIFI_VOS_MSG_URGENT, + MAILBOX_MAILCODE_ITEM_END(BBE16, HIFI, MSG), + }; + +#define MAILBOX_OK 0 +#define MAILBOX_ERRO 0xF7654321 +#define MAILBOX_FULL 0xF7654322 +#define MAILBOX_NOT_READY 0xF7654323 +#define MAILBOX_TARGET_NOT_READY MAILBOX_NOT_READY +#define MAILBOX_TIME_OUT 0xF7654324 + +#define MAILBOX_SEQNUM_START (0) + +#define MAILBOX_MEM_BASEADDR (HIFI_AP_MAILBOX_BASE_ADDR) + +#define MAILBOX_MEM_LENGTH (HIFI_AP_MAILBOX_TOTAL_SIZE) + + typedef struct mb_head { + unsigned int ulProtectWord1; + unsigned int ulProtectWord2; + unsigned int ulFront; + unsigned int ulRear; + unsigned int ulFrontslice; + unsigned int ulRearslice; + unsigned short ausReserve[4]; + unsigned int ulProtectWord3; + unsigned int ulProtectWord4; + } MAILBOX_HEAD_STRU; + +#define MAILBOX_HEAD_LEN (sizeof(struct mb_head)) +#define MAILBOX_MAX_CHANNEL (30) +#define MAILBOX_MEM_HEAD_LEN (MAILBOX_MAX_CHANNEL * MAILBOX_HEAD_LEN) + +#define MAILBOX_QUEUE_SIZE(src, dst, channel) \ + MAILBOX_QUEUE_SIZE_##src##2##dst##_##channel + enum MAILBOX_QUEUE_SIZE_ENUM { + MAILBOX_QUEUE_SIZE(MCU, ACPU, MSG) = 0x00000000, + MAILBOX_QUEUE_SIZE(ACPU, MCU, MSG) = 0x00000000, + MAILBOX_QUEUE_SIZE(MCU, ACPU, IFC) = 0x00000000, + MAILBOX_QUEUE_SIZE(ACPU, MCU, IFC) = 0x00000000, + + MAILBOX_QUEUE_SIZE(MCU, CCPU, MSG) = 0x00000000, + MAILBOX_QUEUE_SIZE(CCPU, MCU, MSG) = 0x00000000, + MAILBOX_QUEUE_SIZE(MCU, CCPU, IFC) = 0x00000000, + MAILBOX_QUEUE_SIZE(CCPU, MCU, IFC) = 0x00000000, + + MAILBOX_QUEUE_SIZE(ACPU, CCPU, MSG) = 0x00000000, + MAILBOX_QUEUE_SIZE(CCPU, ACPU, MSG) = 0x00000000, + MAILBOX_QUEUE_SIZE(ACPU, CCPU, IFC) = 0x00000000, + MAILBOX_QUEUE_SIZE(CCPU, ACPU, IFC) = 0x00000000, + + MAILBOX_QUEUE_SIZE(ACPU, HIFI, MSG) = 0x00001800, + MAILBOX_QUEUE_SIZE(HIFI, ACPU, MSG) = 0x00001800, + + MAILBOX_QUEUE_SIZE(CCPU, HIFI, MSG) = 0x00000000, + MAILBOX_QUEUE_SIZE(HIFI, CCPU, MSG) = 0x00000000, + + MAILBOX_QUEUE_SIZE(BBE16, HIFI, MSG) = 0x00000000, + MAILBOX_QUEUE_SIZE(HIFI, BBE16, MSG) = 0x00000000 + }; + +#define MAILBOX_HEAD_ADDR(src, dst, channel) \ + MAILBOX_HEAD_ADDR_##src##2##dst##_##channel + enum MAILBOX_HEAD_ADDR_ENUM { + MAILBOX_HEAD_ADDR(MCU, ACPU, MSG) = MAILBOX_MEM_BASEADDR, + MAILBOX_HEAD_ADDR(ACPU, MCU, MSG) = + MAILBOX_HEAD_ADDR(MCU, ACPU, MSG) + MAILBOX_HEAD_LEN, + MAILBOX_HEAD_ADDR(ACPU, HIFI, MSG) = + MAILBOX_HEAD_ADDR(ACPU, MCU, MSG) + MAILBOX_HEAD_LEN, + MAILBOX_HEAD_ADDR(HIFI, ACPU, MSG) = + MAILBOX_HEAD_ADDR(ACPU, HIFI, MSG) + MAILBOX_HEAD_LEN, + MAILBOX_HEAD_ADDR(MCU, CCPU, MSG) = + MAILBOX_HEAD_ADDR(HIFI, ACPU, MSG) + MAILBOX_HEAD_LEN, + MAILBOX_HEAD_ADDR(CCPU, MCU, MSG) = + MAILBOX_HEAD_ADDR(MCU, CCPU, MSG) + MAILBOX_HEAD_LEN, + MAILBOX_HEAD_ADDR(CCPU, HIFI, MSG) = + MAILBOX_HEAD_ADDR(CCPU, MCU, MSG) + MAILBOX_HEAD_LEN, + MAILBOX_HEAD_ADDR(HIFI, CCPU, MSG) = + MAILBOX_HEAD_ADDR(CCPU, HIFI, MSG) + MAILBOX_HEAD_LEN, + + MAILBOX_HEAD_ADDR(ACPU, CCPU, MSG) = + MAILBOX_HEAD_ADDR(HIFI, CCPU, MSG) + MAILBOX_HEAD_LEN, + MAILBOX_HEAD_ADDR(CCPU, ACPU, MSG) = + MAILBOX_HEAD_ADDR(ACPU, CCPU, MSG) + MAILBOX_HEAD_LEN, + MAILBOX_HEAD_ADDR(CCPU, ACPU, IFC) = + MAILBOX_HEAD_ADDR(CCPU, ACPU, MSG) + MAILBOX_HEAD_LEN, + MAILBOX_HEAD_ADDR(ACPU, CCPU, IFC) = + MAILBOX_HEAD_ADDR(CCPU, ACPU, IFC) + MAILBOX_HEAD_LEN, + + MAILBOX_HEAD_ADDR(CCPU, MCU, IFC) = + MAILBOX_HEAD_ADDR(ACPU, CCPU, IFC) + MAILBOX_HEAD_LEN, + MAILBOX_HEAD_ADDR(MCU, CCPU, IFC) = + MAILBOX_HEAD_ADDR(CCPU, MCU, IFC) + MAILBOX_HEAD_LEN, + MAILBOX_HEAD_ADDR(ACPU, MCU, IFC) = + MAILBOX_HEAD_ADDR(MCU, CCPU, IFC) + MAILBOX_HEAD_LEN, + MAILBOX_HEAD_ADDR(MCU, ACPU, IFC) = + MAILBOX_HEAD_ADDR(ACPU, MCU, IFC) + MAILBOX_HEAD_LEN, + + MAILBOX_HEAD_ADDR(BBE16, HIFI, MSG) = + MAILBOX_HEAD_ADDR(MCU, ACPU, IFC) + MAILBOX_HEAD_LEN, + MAILBOX_HEAD_ADDR(HIFI, BBE16, MSG) = + MAILBOX_HEAD_ADDR(BBE16, HIFI, MSG) + MAILBOX_HEAD_LEN, + + MAILBOX_HEAD_BOTTOM_ADDR = + MAILBOX_HEAD_ADDR(HIFI, BBE16, MSG) + MAILBOX_HEAD_LEN + }; + +#define MAILBOX_QUEUE_ADDR(src, dst, channel) \ + MAILBOX_QUEUE_ADDR_##src##2##dst##_##channel +#define MAILBOX_QUEUE_BOTTOM_ADDR(src, dst, channel) \ + (MAILBOX_QUEUE_ADDR(src, dst, channel) + MAILBOX_QUEUE_SIZE(src, dst, channel)) + enum MAILBOX_QUEUE_ADDR_ENUM { + MAILBOX_QUEUE_ADDR(MCU, ACPU, MSG) = + MAILBOX_MEM_BASEADDR + MAILBOX_MEM_HEAD_LEN, + MAILBOX_QUEUE_ADDR(ACPU, MCU, MSG) = + MAILBOX_QUEUE_BOTTOM_ADDR(MCU, ACPU, MSG), + MAILBOX_QUEUE_ADDR(ACPU, HIFI, MSG) = + MAILBOX_QUEUE_BOTTOM_ADDR(ACPU, MCU, MSG), + MAILBOX_QUEUE_ADDR(HIFI, ACPU, MSG) = + MAILBOX_QUEUE_BOTTOM_ADDR(ACPU, HIFI, MSG), + + MAILBOX_QUEUE_ADDR(MCU, CCPU, MSG) = + MAILBOX_QUEUE_BOTTOM_ADDR(HIFI, ACPU, MSG), + MAILBOX_QUEUE_ADDR(CCPU, MCU, MSG) = + MAILBOX_QUEUE_BOTTOM_ADDR(MCU, CCPU, MSG), + MAILBOX_QUEUE_ADDR(CCPU, HIFI, MSG) = + MAILBOX_QUEUE_BOTTOM_ADDR(CCPU, MCU, MSG), + MAILBOX_QUEUE_ADDR(HIFI, CCPU, MSG) = + MAILBOX_QUEUE_BOTTOM_ADDR(CCPU, HIFI, MSG), + + MAILBOX_QUEUE_ADDR(ACPU, CCPU, MSG) = + MAILBOX_QUEUE_BOTTOM_ADDR(HIFI, CCPU, MSG), + MAILBOX_QUEUE_ADDR(CCPU, ACPU, MSG) = + MAILBOX_QUEUE_BOTTOM_ADDR(ACPU, CCPU, MSG), + MAILBOX_QUEUE_ADDR(CCPU, ACPU, IFC) = + MAILBOX_QUEUE_BOTTOM_ADDR(CCPU, ACPU, MSG), + MAILBOX_QUEUE_ADDR(ACPU, CCPU, IFC) = + MAILBOX_QUEUE_BOTTOM_ADDR(CCPU, ACPU, IFC), + + MAILBOX_QUEUE_ADDR(CCPU, MCU, IFC) = + MAILBOX_QUEUE_BOTTOM_ADDR(ACPU, CCPU, IFC), + MAILBOX_QUEUE_ADDR(MCU, CCPU, IFC) = + MAILBOX_QUEUE_BOTTOM_ADDR(CCPU, MCU, IFC), + MAILBOX_QUEUE_ADDR(ACPU, MCU, IFC) = + MAILBOX_QUEUE_BOTTOM_ADDR(MCU, CCPU, IFC), + MAILBOX_QUEUE_ADDR(MCU, ACPU, IFC) = + MAILBOX_QUEUE_BOTTOM_ADDR(ACPU, MCU, IFC), + + MAILBOX_QUEUE_ADDR(BBE16, HIFI, MSG) = + MAILBOX_QUEUE_BOTTOM_ADDR(MCU, ACPU, IFC), + MAILBOX_QUEUE_ADDR(HIFI, BBE16, MSG) = + MAILBOX_QUEUE_BOTTOM_ADDR(BBE16, HIFI, MSG), + + MAILBOX_MEMORY_BOTTOM_ADDR = + MAILBOX_QUEUE_BOTTOM_ADDR(HIFI, BBE16, MSG) + }; + +#define MAILBOX_PROTECT1 (0x55AA55AA) +#define MAILBOX_PROTECT2 (0x5A5A5A5A) +#define MAILBOX_PROTECT_LEN (sizeof(int)) +#define MAILBOX_MSGHEAD_NUMBER (0xA5A5A5A5) + +#define MAILBOX_DATA_BASE_PROTECT_NUM (2) +#define MAILBOX_DATA_TAIL_PROTECT_NUM (2) + +#define MAILBOX_DATA_LEN_PROTECT_NUM (MAILBOX_DATA_BASE_PROTECT_NUM + MAILBOX_DATA_TAIL_PROTECT_NUM) + +#define HIFI_MB_ADDR_PROTECT (0x5a5a5a5a) + +#define MAILBOX_IPC_INT_NUM(src, dst, channel) \ + MAILBOX_IPC_INT_##src##2##dst##_##channel + enum IPC_MAILBOX_INT_ENUM { +#if 0 + MAILBOX_IPC_INT_NUM(CCPU, MCU, MSG) = IPC_MCU_INT_SRC_CCPU_MSG, + MAILBOX_IPC_INT_NUM(MCU, CCPU, MSG) = IPC_CCPU_INT_SRC_MCU_MSG, + + MAILBOX_IPC_INT_NUM(CCPU, HIFI, MSG) = + IPC_HIFI_INT_SRC_CCPU_MSG, + MAILBOX_IPC_INT_NUM(HIFI, CCPU, MSG) = + IPC_CCPU_INT_SRC_HIFI_MSG, + + MAILBOX_IPC_INT_NUM(ACPU, MCU, MSG) = IPC_MCU_INT_SRC_ACPU_MSG, + MAILBOX_IPC_INT_NUM(MCU, ACPU, MSG) = IPC_ACPU_INT_SRC_MCU_MSG, + + MAILBOX_IPC_INT_NUM(ACPU, HIFI, MSG) = + IPC_HIFI_INT_SRC_ACPU_MSG, + MAILBOX_IPC_INT_NUM(HIFI, ACPU, MSG) = + IPC_ACPU_INT_SRC_HIFI_MSG, + + MAILBOX_IPC_INT_NUM(HIFI, MCU, MSG) = IPC_MCU_INT_SRC_HIFI_MSG, + MAILBOX_IPC_INT_NUM(MCU, HIFI, MSG) = IPC_HIFI_INT_SRC_MCU_MSG, + + MAILBOX_IPC_INT_NUM(CCPU, ACPU, MSG) = + IPC_ACPU_INT_SRC_CCPU_MSG, + MAILBOX_IPC_INT_NUM(ACPU, CCPU, MSG) = + IPC_CCPU_INT_SRC_ACPU_MSG, + + MAILBOX_IPC_INT_NUM(CCPU, ACPU, IFC) = + IPC_ACPU_INT_SRC_CCPU_IFC, + MAILBOX_IPC_INT_NUM(ACPU, CCPU, IFC) = + IPC_CCPU_INT_SRC_ACPU_IFC, + + MAILBOX_IPC_INT_NUM(CCPU, MCU, IFC) = IPC_MCU_INT_SRC_CCPU_IFC, + MAILBOX_IPC_INT_NUM(MCU, CCPU, IFC) = IPC_CCPU_INT_SRC_MCU_IFC, + + MAILBOX_IPC_INT_NUM(ACPU, MCU, IFC) = IPC_MCU_INT_SRC_ACPU_IFC, + MAILBOX_IPC_INT_NUM(MCU, ACPU, IFC) = IPC_ACPU_INT_SRC_MCU_IFC, + + MAILBOX_IPC_INT_NUM(BBE16, HIFI, MSG) = + IPC_HIFI_INT_SRC_BBE_MSG, + MAILBOX_IPC_INT_NUM(HIFI, BBE16, MSG) = + IPC_BBE16_INT_SRC_HIFI_MSG +#else + MAILBOX_IPC_INT_NUM(CCPU, HIFI, MSG) = + IPC_HIFI_INT_SRC_CCPU_MSG, + MAILBOX_IPC_INT_NUM(HIFI, CCPU, MSG) = + IPC_CCPU_INT_SRC_HIFI_MSG, + + MAILBOX_IPC_INT_NUM(ACPU, HIFI, MSG) = + IPC_HIFI_INT_SRC_ACPU_MSG, + MAILBOX_IPC_INT_NUM(HIFI, ACPU, MSG) = + IPC_ACPU_INT_SRC_HIFI_MSG, +#endif + }; + +#define MAILBOX_MAILSIZE_MAX(src, dst, channel) \ + MAILBOX_MAILSIZE_MAX_##src##2##dst##_##channel + enum MAILBOX_MAILSIZE_MAX_ENUM { + MAILBOX_MAILSIZE_MAX(MCU, ACPU, MSG) = + MAILBOX_QUEUE_SIZE(MCU, ACPU, MSG) / 4, + MAILBOX_MAILSIZE_MAX(ACPU, MCU, MSG) = + MAILBOX_QUEUE_SIZE(ACPU, MCU, MSG) / 4, + MAILBOX_MAILSIZE_MAX(ACPU, HIFI, MSG) = + MAILBOX_QUEUE_SIZE(ACPU, HIFI, MSG) / 4, + MAILBOX_MAILSIZE_MAX(HIFI, ACPU, MSG) = + MAILBOX_QUEUE_SIZE(HIFI, ACPU, MSG) / 4, + MAILBOX_MAILSIZE_MAX(MCU, CCPU, MSG) = + MAILBOX_QUEUE_SIZE(MCU, CCPU, MSG) / 4, + MAILBOX_MAILSIZE_MAX(CCPU, MCU, MSG) = + MAILBOX_QUEUE_SIZE(CCPU, MCU, MSG) / 4, + MAILBOX_MAILSIZE_MAX(CCPU, HIFI, MSG) = + MAILBOX_QUEUE_SIZE(CCPU, HIFI, MSG) / 4, + MAILBOX_MAILSIZE_MAX(HIFI, CCPU, MSG) = + MAILBOX_QUEUE_SIZE(HIFI, CCPU, MSG) / 4, + + MAILBOX_MAILSIZE_MAX(CCPU, ACPU, MSG) = + MAILBOX_QUEUE_SIZE(CCPU, ACPU, MSG) / 4, + MAILBOX_MAILSIZE_MAX(ACPU, CCPU, MSG) = + MAILBOX_QUEUE_SIZE(ACPU, CCPU, MSG) / 4, + MAILBOX_MAILSIZE_MAX(CCPU, ACPU, IFC) = + MAILBOX_QUEUE_SIZE(CCPU, ACPU, IFC) / 4, + MAILBOX_MAILSIZE_MAX(ACPU, CCPU, IFC) = + MAILBOX_QUEUE_SIZE(ACPU, CCPU, IFC) / 4, + + MAILBOX_MAILSIZE_MAX(CCPU, MCU, IFC) = + MAILBOX_QUEUE_SIZE(CCPU, MCU, IFC) / 4, + MAILBOX_MAILSIZE_MAX(MCU, CCPU, IFC) = + MAILBOX_QUEUE_SIZE(MCU, CCPU, IFC) / 4, + + MAILBOX_MAILSIZE_MAX(ACPU, MCU, IFC) = + MAILBOX_QUEUE_SIZE(ACPU, MCU, IFC) / 4, + MAILBOX_MAILSIZE_MAX(MCU, ACPU, IFC) = + MAILBOX_QUEUE_SIZE(MCU, ACPU, IFC) / 4, + + MAILBOX_MAILSIZE_MAX(BBE16, HIFI, MSG) = + MAILBOX_QUEUE_SIZE(BBE16, HIFI, MSG) / 4, + MAILBOX_MAILSIZE_MAX(HIFI, BBE16, MSG) = + MAILBOX_QUEUE_SIZE(HIFI, BBE16, MSG) / 4, + }; + + typedef struct mb_mail { + unsigned int ulPartition; + unsigned int ulWriteSlice; + unsigned int ulReadSlice; + unsigned int ulSeqNum; + unsigned int ulPriority; + unsigned int ulMailCode; + unsigned int ausReserve[2]; + unsigned int ulMsgLength; + } MAILBOX_MSG_HEADER; + + enum { + HI_SYSCTRL_BASE_ADDR_ID = 0, + HI_SOCP_REGBASE_ADDR_ID, + SOC_IPC_S_BASE_ADDR_ID, + SOC_AP_EDMAC_BASE_ADDR_ID, + SOC_UART3_BASE_ADDR_ID, + SOC_Watchdog1_BASE_ADDR_ID, + SOC_AO_SCTRL_SC_SLICER_COUNT0_ADDR_0_ID, + SOC_HIFI_Timer00_BASE_ADDR_ID, + SOC_HIFI_Timer08_BASE_ADDR_ID, + DDR_HIFI_ADDR_ID, + SOC_BBP_TDS_BASE_ADDR_ID, + }; + + typedef struct { + unsigned int enID; + unsigned int uwAddress; + } SOC_HIFI_ADDR_ITEM_STRU; + + typedef struct { + unsigned int uwProtectWord; /*0x5a5a5a5a */ + SOC_HIFI_ADDR_ITEM_STRU astSocAddr[64]; + } SOC_HIFI_ADDR_SHARE_STRU; + + typedef struct { + unsigned int uwProtectWord; + unsigned int uwAddrPhy; + unsigned int uwSize; + unsigned int uwReserve; + + } MODEM_HIFI_NV_SHARE_STRU; + + typedef struct { + unsigned int uwProtectWord; /*0x5a5a5a5a */ + unsigned int uwHifi2AarmMailBoxLen; + unsigned int uwAarm2HifiMailBoxLen; + unsigned int uwHifiAarmHeadAddr; + unsigned int uwHifiAarmBodyAddr; + unsigned int uwAarmHifiHeadAddr; + unsigned int uwAarmHifiBodyAddr; + unsigned int uwReserved[2]; + } AARM_HIFI_MAILBOX_STRU; + + typedef struct { + unsigned int uwProtectWord; /*0x5a5a5a5a */ + unsigned int uwHifi2CarmMailBoxLen; + unsigned int uwCarm2HifiMailBoxLen; + unsigned int uwHifiCarmHeadAddr; + unsigned int uwHifiCarmBodyAddr; + unsigned int uwCarmHifiHeadAddr; + unsigned int uwCarmHifiBodyAddr; + unsigned int uwReserved[2]; + } CARM_HIFI_MAILBOX_STRU; + + typedef struct { + unsigned int uwProtectWord; + unsigned int uwHifi2CarmIccChannelLen; + unsigned int uwHifi2TphyIccChannelLen; + unsigned int uwHifi2CarmIccChannelAddr; + unsigned int uwCarm2HifiIccChannelAddr; + unsigned int uwHifi2TphyIccChannelAddr; + unsigned int uwTphy2HifiIccChannelAddr; + unsigned int uwReserved[2]; + } CARM_HIFI_ICC_STRU; + + typedef struct { + unsigned int uwProtectWord; /*0x5a5a5a5a */ + CARM_HIFI_ICC_STRU stCarmHifiMB; + AARM_HIFI_MAILBOX_STRU stAarmHifiMB; + unsigned int uwNvBaseAddrPhy; + unsigned int uwNvBaseAddrVirt; + MODEM_HIFI_NV_SHARE_STRU stNVShare; + SOC_HIFI_ADDR_SHARE_STRU stSoCShare; + unsigned int uwReserved[2]; + } CARM_HIFI_DYN_ADDR_SHARE_STRU; + + typedef void (*mb_msg_cb) (void *user_handle, + void *mail_handle, unsigned int mail_len); + + unsigned int DRV_MAILBOX_SENDMAIL(unsigned int MailCode, + void *pData, unsigned int Length); + + unsigned int DRV_MAILBOX_REGISTERRECVFUNC(unsigned int MailCode, + mb_msg_cb pFun, + void *UserHandle); + + unsigned int DRV_MAILBOX_READMAILDATA(void *MailHandle, + unsigned char *pData, + unsigned int *pSize); + + void drv_hifi_fill_mb_info(unsigned int addr); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif +#endif /* end of drv_mailbox_cfg.h */ |