1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
|
/*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
* Based on "omap4.dtsi"
*/
#include "dra7.dtsi"
/ {
compatible = "ti,dra722", "ti,dra72", "ti,dra7";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
operating-points = <
/* kHz uV */
1000000 1060000
>;
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
clock-latency = <300000>; /* From omap-cpufreq driver */
/* cooling options */
cooling-min-level = <0>;
cooling-max-level = <2>;
#cooling-cells = <2>; /* min followed by max */
};
};
iva_coproc {
compatible = "ti,coproc";
clocks = <&dpll_iva_m2_ck>, <&dpll_iva_ck>;
clock-names = "fclk", "dpll";
clock-target-frequency = <532000000>;
operating-points = <
388200 1055000
430000 1150000
532000 1250000
>;
coproc-voltdm = <&voltdm_ivahd>;
voltage-tolerance = <1>;
};
dsp_coproc {
compatible = "ti,coproc";
clocks = <&dpll_dsp_m2_ck>, <&dpll_dsp_ck>;
clock-names = "fclk", "dpll";
clock-target-frequency = <700000000>;
operating-points = <
600000 1055000
700000 1150000
700000 1250000
>;
coproc-voltdm = <&voltdm_dspeve>;
voltage-tolerance = <1>;
};
thermal-zones {
#include "omap5-cpu-thermal.dtsi"
};
aliases {
rproc0 = &ipu1;
rproc1 = &ipu2;
rproc2 = &dsp1;
};
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
};
};
&mailbox1 {
mbox_ipu2: mbox_ipu2 {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
status = "disabled";
};
mbox_dsp1: mbox_dsp1 {
ti,mbox-tx = <3 0 0>;
ti,mbox-rx = <2 0 0>;
status = "disabled";
};
};
&mailbox2 {
mbox_ipu1: mbox_ipu1 {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
status = "disabled";
};
};
&mailbox5 {
mbox_ipu1_legacy: mbox_ipu1_legacy {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
mbox_dsp1_legacy: mbox_dsp1_legacy {
ti,mbox-tx = <5 2 2>;
ti,mbox-rx = <1 2 2>;
status = "disabled";
};
};
&mailbox6 {
mbox_ipu2_legacy: mbox_ipu2_legacy {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
};
|
