diff options
Diffstat (limited to 'drivers/clk/meson/clkc.h')
| -rw-r--r-- | drivers/clk/meson/clkc.h | 179 |
1 files changed, 56 insertions, 123 deletions
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 609ae92cc13f..53326c32e853 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -34,19 +34,16 @@ struct parm { u8 shift; u8 width; }; -#define PARM(_r, _s, _w) \ - { \ - .reg_off = (_r), \ - .shift = (_s), \ - .width = (_w), \ - } \ struct pll_rate_table { unsigned long rate; u16 m; u16 n; u16 od; + u16 od2; + u16 frac; }; + #define PLL_RATE(_r, _m, _n, _od) \ { \ .rate = (_r), \ @@ -55,133 +52,69 @@ struct pll_rate_table { .od = (_od), \ } \ -struct pll_conf { - const struct pll_rate_table *rate_table; - struct parm m; - struct parm n; - struct parm od; -}; +#define PLL_FRAC_RATE(_r, _m, _n, _od, _od2, _frac) \ + { \ + .rate = (_r), \ + .m = (_m), \ + .n = (_n), \ + .od = (_od), \ + .od2 = (_od2), \ + .frac = (_frac), \ + } \ -struct fixed_fact_conf { - unsigned int div; - unsigned int mult; - struct parm div_parm; - struct parm mult_parm; +struct meson_clk_pll { + struct clk_hw hw; + void __iomem *base; + struct parm m; + struct parm n; + struct parm frac; + struct parm od; + struct parm od2; + const struct pll_rate_table *rate_table; + unsigned int rate_count; + spinlock_t *lock; }; -struct fixed_rate_conf { - unsigned long rate; - struct parm rate_parm; -}; +#define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw) -struct composite_conf { - struct parm mux_parm; - struct parm div_parm; - struct parm gate_parm; - struct clk_div_table *div_table; - u32 *mux_table; - u8 mux_flags; - u8 div_flags; - u8 gate_flags; +struct meson_clk_cpu { + struct clk_hw hw; + void __iomem *base; + u16 reg_off; + struct notifier_block clk_nb; + const struct clk_div_table *div_table; }; -#define PNAME(x) static const char *x[] +int meson_clk_cpu_notifier_cb(struct notifier_block *nb, unsigned long event, + void *data); -enum clk_type { - CLK_FIXED_FACTOR, - CLK_FIXED_RATE, - CLK_COMPOSITE, - CLK_CPU, - CLK_PLL, +struct meson_clk_mpll { + struct clk_hw hw; + void __iomem *base; + struct parm sdm; + struct parm n2; + /* FIXME ssen gate control? */ + spinlock_t *lock; }; -struct clk_conf { - u16 reg_off; - enum clk_type clk_type; - unsigned int clk_id; - const char *clk_name; - const char **clks_parent; - int num_parents; - unsigned long flags; - union { - struct fixed_fact_conf fixed_fact; - struct fixed_rate_conf fixed_rate; - const struct composite_conf *composite; - struct pll_conf *pll; - const struct clk_div_table *div_table; - } conf; +#define MESON_GATE(_name, _reg, _bit) \ +struct clk_gate gxbb_##_name = { \ + .reg = (void __iomem *) _reg, \ + .bit_idx = (_bit), \ + .lock = &clk_lock, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &clk_gate_ops, \ + .parent_names = (const char *[]){ "clk81" }, \ + .num_parents = 1, \ + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ + }, \ }; -#define FIXED_RATE_P(_ro, _ci, _cn, _f, _c) \ - { \ - .reg_off = (_ro), \ - .clk_type = CLK_FIXED_RATE, \ - .clk_id = (_ci), \ - .clk_name = (_cn), \ - .flags = (_f), \ - .conf.fixed_rate.rate_parm = _c, \ - } \ - -#define FIXED_RATE(_ci, _cn, _f, _r) \ - { \ - .clk_type = CLK_FIXED_RATE, \ - .clk_id = (_ci), \ - .clk_name = (_cn), \ - .flags = (_f), \ - .conf.fixed_rate.rate = (_r), \ - } \ - -#define PLL(_ro, _ci, _cn, _cp, _f, _c) \ - { \ - .reg_off = (_ro), \ - .clk_type = CLK_PLL, \ - .clk_id = (_ci), \ - .clk_name = (_cn), \ - .clks_parent = (_cp), \ - .num_parents = ARRAY_SIZE(_cp), \ - .flags = (_f), \ - .conf.pll = (_c), \ - } \ - -#define FIXED_FACTOR_DIV(_ci, _cn, _cp, _f, _d) \ - { \ - .clk_type = CLK_FIXED_FACTOR, \ - .clk_id = (_ci), \ - .clk_name = (_cn), \ - .clks_parent = (_cp), \ - .num_parents = ARRAY_SIZE(_cp), \ - .conf.fixed_fact.div = (_d), \ - } \ - -#define CPU(_ro, _ci, _cn, _cp, _dt) \ - { \ - .reg_off = (_ro), \ - .clk_type = CLK_CPU, \ - .clk_id = (_ci), \ - .clk_name = (_cn), \ - .clks_parent = (_cp), \ - .num_parents = ARRAY_SIZE(_cp), \ - .conf.div_table = (_dt), \ - } \ - -#define COMPOSITE(_ro, _ci, _cn, _cp, _f, _c) \ - { \ - .reg_off = (_ro), \ - .clk_type = CLK_COMPOSITE, \ - .clk_id = (_ci), \ - .clk_name = (_cn), \ - .clks_parent = (_cp), \ - .num_parents = ARRAY_SIZE(_cp), \ - .flags = (_f), \ - .conf.composite = (_c), \ - } \ - -struct clk **meson_clk_init(struct device_node *np, unsigned long nr_clks); -void meson_clk_register_clks(const struct clk_conf *clk_confs, - unsigned int nr_confs, void __iomem *clk_base); -struct clk *meson_clk_register_cpu(const struct clk_conf *clk_conf, - void __iomem *reg_base, spinlock_t *lock); -struct clk *meson_clk_register_pll(const struct clk_conf *clk_conf, - void __iomem *reg_base, spinlock_t *lock); +/* clk_ops */ +extern const struct clk_ops meson_clk_pll_ro_ops; +extern const struct clk_ops meson_clk_pll_ops; +extern const struct clk_ops meson_clk_cpu_ops; +extern const struct clk_ops meson_clk_mpll_ro_ops; #endif /* __CLKC_H */ |