diff options
| author | Rob Clark <rob@ti.com> | 2011-11-30 11:16:28 +0800 |
|---|---|---|
| committer | Andy Green <andy.green@linaro.org> | 2011-11-30 11:16:28 +0800 |
| commit | 4a11e8a1244e025586da540097d83409810c7515 (patch) | |
| tree | 20c0e37da0be5902477d5dc2231cf91c0b8c05df | |
| parent | 1a5f36b7a6b798074b350dd86937b7562803f0d8 (diff) | |
pvr: don't rely on bootloader settings for parent clk
In past xloader was configuring this. But with u-boot SPL the setting
was incorrect. The kernel shouldn't rely on bootloader settings.
| -rw-r--r-- | drivers/gpu/pvr/omap4/sysutils_linux.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/gpu/pvr/omap4/sysutils_linux.c b/drivers/gpu/pvr/omap4/sysutils_linux.c index 895b1e615fe..75d8e4eab0c 100644 --- a/drivers/gpu/pvr/omap4/sysutils_linux.c +++ b/drivers/gpu/pvr/omap4/sysutils_linux.c @@ -460,6 +460,34 @@ PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData) if (!psSysSpecData->bSysClocksOneTimeInit) { + struct clk *sgx_clk, *parent_clk; + int res; + + sgx_clk = clk_get(&gpsPVRLDMDev->dev, "gpu_fck"); + if (IS_ERR_OR_NULL(sgx_clk)) { + /* try another name that the sgx clock might be known as.. */ + sgx_clk = clk_get(&gpsPVRLDMDev->dev, "sgx_clk_mux_ck"); + } + if (IS_ERR_OR_NULL(sgx_clk)) { + PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: could not get clock (%ld)", -PTR_ERR(sgx_clk))); + return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK; + } + + parent_clk = clk_get(&gpsPVRLDMDev->dev, "dpll_per_m7x2_ck"); + if (IS_ERR_OR_NULL(parent_clk)) { + PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: could not get clock (%ld)", -PTR_ERR(parent_clk))); + clk_put(sgx_clk); + return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK; + } + + res = clk_set_parent(sgx_clk, parent_clk); + if (IS_ERR_VALUE(res)) { + PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: could not set clock (%d)", -res)); + clk_put(sgx_clk); + clk_put(parent_clk); + return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK; + } + mutex_init(&psSysSpecData->sPowerLock); atomic_set(&psSysSpecData->sSGXClocksEnabled, 0); |