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2014-03-13target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)a64-workingAlex Bennée
This adds support for [UF]RSQRTE instructions. It utilises the existing NEON helpers with some changes. The changes include an explicit passing of fpstatus (so the correct one is used between arm32 and aarch64), denormilzation, more correct error handling and also proper scaling of the fraction going into the estimate. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2014-03-13target-arm: A64: Implement FCVTXNPeter Maydell
Implement the FCVTXN operation, which does a narrowing fp precision conversion using the "round to odd" (von Neumann) mode. This can conveniently be implemented as "do operation using round to zero; then set the LSB of the mantissa to 1 if the Inexact flag was set". Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Implement scalar saturating narrow opsAlex Bennée
This completes the set of integer narrowing saturating ops including: SQXTN, SQXTN2 SQXTUN, SQXTUN2 UQXTN, UQXTN2 Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Move handle_2misc_narrow functionAlex Bennée
Move the handle_2misc_narrow() function up the file so that it can be called from disas_simd_scalar_two_reg_misc(). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée
Implement URECPE and FRECPE instructions in both scalar and vector forms. The actual reciprocal estimate function is shared with the A32/T32 Neon code. However in A64 we aren't using the Neon "standard FPSCR value" so extra checks are necessary to handle non-squashed denormal inputs which can never happen for A32/T32. Calling conventions for the helpers are thus modified to pass the fpst directly; we mark the helpers as TCG_CALL_NO_RWG since we're changing the declarations anyway. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13softfloat: export squash_input_denormal functionsAlex Bennée
I need these available outside of softfloat for some of the reciprocal processing in aarch64 helper functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categoriesPeter Maydell
Implement FCVTZS and FCVTZU in the shift-imm and scalar-shift-imm categories; this completes the implementation of those two groups. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHLPeter Maydell
Implement the saturating left shift instructions SQSHL, SQSHLU and UQSHL for the scalar-shift-imm and shift-imm categories. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoderPeter Maydell
The ARM A64 decoder's worst case number of TCG ops per instruction is 266 (for insn 0x4c800000, a post-indexed ST4 multiple-structures store). Raise the MAX_OP_PER_INSTR define accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Implement FRINT*Peter Maydell
Implement the FRINT* round-to-integral operations from the 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Implement SRIPeter Maydell
Implement SRI (shift right and insert). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Add FRECPX (reciprocal exponent)Alex Bennée
These are fairly simple exponent only estimation functions using helpers. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: List unsupported shift-imm opcodesPeter Maydell
Add the remaining unsupported opcodes to the decode switches for the shift-imm and scalar shift-imm categories so we can see what is still to be implemented. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Implement FCVTLPeter Maydell
Implement FCVTL, the only instruction in the 2-reg-misc group which widens from size to 2*size elements. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Implement FCVTNPeter Maydell
Implement FCVTN (narrowing fp-to-fp conversions) from the SIMD 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructionsPeter Maydell
Implement the floating-point-to-integer conversion instructions FCVT[NMAPZ][SU] in the 2-reg-misc and scalar-2-reg-misc categories. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Implement SHLL, SHLL2Peter Maydell
Implement the SHLL and SHLL2 instructions from the 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALPPeter Maydell
Implement the SADDLP, UADDLP, SADALP and UADALP instructions in the SIMD 2-reg misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Saturating and narrowing shift opsAlex Bennée
This implements the remaining [US][Q][R]SHR[U][N][2] opcodes, which are saturating and narrowing shift right operations. These are used in things like libav. Note signed shifts can have an "unsigned" saturating narrow operation which will floor negative values. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> [PMM: Added the scalar encodings, style tweaks] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Add remaining CLS/Z vector opsAlex Bennée
Implement the CLS, CLZ operations in the 2-reg-misc category. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Add FSQRT to C3.6.17 (two misc)Alex Bennée
Implement FSQRT in the two-reg-misc category. GCC uses this instruction form. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Add last AdvSIMD Integer to FP opsAlex Bennée
This adds the remaining [US]CVTF operations to the SIMD shift-immediate, scalar-shift-immediate, two-reg-misc and scalar-two-reg-misc groups of opcodes. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> [PMM: added scalar 2-misc and scalar-shift-imm encodings] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Fix bug in add_sub_ext handling of rnAlex Bennée
rn == 31 always means SP (not XZR) whether an add_sub_ext instruction is setting the flags or not; only rd has behaviour dependent on whether we are setting flags. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-13target-arm: A64: Implement PMULL instructionPeter Maydell
Implement the PMULL instruction; this is the last unimplemented insn in the three-reg-diff group. Note that PMULL with size 3 is considered part of the AES part of the crypto extensions (see the ID_AA64ISAR0_EL1 register definition in the v8 ARM ARM), so it isn't necessary to burn an extra feature bit on it, even though we're using more feature bits than a single "crypto extension present/not present" toggle. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-11Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
acpi,pc,test bug fixes More small fixes: the issues annoy developers so I thought they are worth fixing quickly. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Tue 11 Mar 2014 11:27:44 GMT using RSA key ID D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: acpi-test: update expected SSDT files acpi-build: don't access unaligned addresses q35: Correct typo BRDIGE -> BRIDGE configure: don't modify .status on error pc: avoid duplicate names for ROM MRs loader: rename in_ram/has_mr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-11Merge remote-tracking branch 'remotes/kvm/uq/master' into stagingPeter Maydell
* remotes/kvm/uq/master: target-i386: bugfix of Intel MPX file_ram_alloc: unify mem-path,mem-prealloc error handling kvm-all: exit in case max vcpus exceeded Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-11qemu-thread-posix: Fix build against older glibc versionJan Kiszka
pthread_setname_np was introduced with 2.12. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-11Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20140310' into staging target-arm queue: * implement WFE as yield (improves performance with emulated SMP) * fixes to avoid undefined behaviour shifting left into sign bit * libvixl format string fixes for 32 bit hosts * fix build error when intptr_t and tcg_target_long are different sizes (eg x32) * implement PMCCNTR register * fix incorrect setting of E bit in CPSR (broke booting under KVM on ARM) # gpg: Signature made Mon 10 Mar 2014 15:05:25 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140310: target-arm: Implement WFE as a yield operation hw/arm/musicpal: Avoid shifting left into sign bit hw/ssi/xilinx_spips.c: Avoid shifting left into sign bit hw/arm/omap1.c: Avoid shifting left into sign bit pxa2xx: Don't shift into sign bit libvixl: Fix format strings for several int64_t values target-arm: Fix intptr_t vs tcg_target_long target-arm: Implements the ARM PMCCNTR register target-arm: Fix incorrect setting of E bit in CPSR Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-11Merge remote-tracking branch 'remotes/spice/tags/pull-spice-4' into stagingPeter Maydell
minor spice patches. # gpg: Signature made Mon 10 Mar 2014 13:13:14 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/spice/tags/pull-spice-4: configure: Prettify message for hosts without spice support spice: QemuUIInfo windup spice: fix simple display surface handling Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-11Merge remote-tracking branch 'remotes/kraxel/tags/pull-input-5' into stagingPeter Maydell
input: fixes for the rewrite. # gpg: Signature made Mon 10 Mar 2014 12:50:25 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-input-5: input: map INPUT_BUTTON_WHEEL_{UP,DOWN} to legacy input z axis moves. input: sdl: fix guest_cursor logic. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-11acpi-test: update expected SSDT filesMichael S. Tsirkin
SSDT doesn't have _SUN for non hotpluggable slots anymore. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-03-11acpi-build: don't access unaligned addressesMichael S. Tsirkin
casting an unaligned address to e.g. uint32_t can trigger undefined behaviour in C. Replace cast + assignment with memcpy. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-03-11q35: Correct typo BRDIGE -> BRIDGEBALATON Zoltan
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-03-11configure: don't modify .status on errorMichael S. Tsirkin
./configure --help make will try to re-run configure with --help which isn't what was intended. The reason is that config.status was written even on configure error. Defer writing config.status until configure has completed successfully. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-11pc: avoid duplicate names for ROM MRsMichael S. Tsirkin
Since commit 04920fc0faa4760f9c4fc0e73b992b768099be70 loader: store FW CFG ROM files in RAM RAM MRs including ROM files in FW CFGs are created and named using the file basename. This becomes problematic if these names are supplied by user, since the basename might not be unique. There are two cases we care about: - option-rom flag. - option ROM for devices. This triggers e.g. when using rombar=0. At the moment we get an assert. E.g qemu -option-rom /usr/share/ipxe/8086100e.rom -option-rom /usr/share/ipxe.efi/8086100e.rom RAMBlock "/rom@genroms/8086100e.rom" already registered, abort! This is a regression from 1.6. For now let's keep it simple and just avoid creating the MRs in case of option ROMs. when using 1.7 machine types, enable option ROMs in RAM to match that version. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-03-11Merge remote-tracking branch 'remotes/kraxel/tags/pull-vnc-1' into stagingPeter Maydell
vnc dirty tracking optinizations. various vnc bugfixes. # gpg: Signature made Mon 10 Mar 2014 12:39:54 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-vnc-1: ui/vnc: disable adaptive update calculations if not needed ui/vnc: optimize setting in vnc_dpy_update() ui/vnc: optimize clearing in find_and_clear_dirty_height() ui/vnc: optimize dirty bitmap tracking ui/vnc: derive cmp_bytes from VNC_DIRTY_PIXELS_PER_BIT ui/vnc: introduce VNC_DIRTY_PIXELS_PER_BIT macro vnc: fix use-after-free in vnc_update_client_sync vnc: Fix qemu crashed when vnc client disconnect suddenly vnc: Fix tight_detect_smooth_image() for lossless case Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-11target-i386: bugfix of Intel MPXLiu, Jinsong
The correct size of cpuid 0x0d sub-leaf 4 is 0x40, not 0x10. This is confirmed by Anvin H Peter and Mallick Asit K. Signed-off-by: Liu Jinsong <jinsong.liu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Asit K Mallick <asit.k.mallick@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
2014-03-10Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
acpi,pc,pci,virtio,memory bug fixes This collects several small fixes from all over the place. Additionally, Marcel's changes make acpi unit tests more robust. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Sun 09 Mar 2014 19:14:57 GMT using RSA key ID D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: qemu: x86: ignore ioapic polarity pckbd: return 'keyboard enabled' on read input port command pam: partly fix write-only mode acpi-test: issue errors instead of warnings when possible acpi-test: retain both asl and aml files on failure MAINTAINERS: drop an out of date address Add a 'name' parameter to qemu_thread_create Add 'debug-threads' suboption to --name Rework --name to use QemuOpts PCIE: fix regression with coldplugged multifunction device memory_region_present: return false if address is not found in child MemoryRegion virtio-net: remove function calls from assert acpi-test-data: update expected files acpi-build: append description for non-hotplug Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-10s390/kvm: Add Maintainers for s390/kvmChristian Borntraeger
Lets add Conny and myself as maintainers for s390/kvm and related code. This does not include any tcg related code, which is maintained by Richard and Alex. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Acked-by: Alexander Graf <agraf@suse.de> Message-id: 1394095765-29686-2-git-send-email-borntraeger@de.ibm.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-10Merge remote-tracking branch 'remotes/riku/linux-user-for-upstream' into stagingPeter Maydell
* remotes/riku/linux-user-for-upstream: linux-user: set minimum kernel version to 2.6.32 linux-user: correct handling of break exception for MIPS linux-user: translate signal number on return from sigtimedwait linux-user: Implement sendmmsg syscall linux-user: Fix getresuid, getresgid if !USE_UID16 linux-user: Don't use UID16 on AArch64 linux-user: AArch64: Implement SA_RESTORER for signal handlers linux-user/signal.c: Fix AArch64 big-endian FP register restore Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-10Merge remote-tracking branch 'remotes/mcayland/qemu-openbios' into stagingPeter Maydell
* remotes/mcayland/qemu-openbios: Update OpenBIOS images Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-10target-arm: Implement WFE as a yield operationpull-target-arm-20140310Peter Maydell
Implement WFE to yield our timeslice to the next CPU. This avoids slowdowns in multicore configurations caused by one core busy-waiting on a spinlock which can't possibly be unlocked until the other core has an opportunity to run. This speeds up my test case A15 dual-core boot by a factor of three (though it is still four or five times slower than a single-core boot). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1393339545-22111-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Richard Henderson <rth@twiddle.net> Tested-by: Rob Herring <rob.herring@linaro.org>
2014-03-10hw/arm/musicpal: Avoid shifting left into sign bitPeter Maydell
Add missing 'U' suffixes to avoid shifting left into sign bit of a signed integer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1392988008-15938-5-git-send-email-peter.maydell@linaro.org
2014-03-10hw/ssi/xilinx_spips.c: Avoid shifting left into sign bitPeter Maydell
Add missing 'U' suffix to avoid shifting left into sign bit of a signed integer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1392988008-15938-4-git-send-email-peter.maydell@linaro.org
2014-03-10hw/arm/omap1.c: Avoid shifting left into sign bitPeter Maydell
Add missing 'U' suffix to avoid shifting left into sign bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1392988008-15938-3-git-send-email-peter.maydell@linaro.org
2014-03-10pxa2xx: Don't shift into sign bitPeter Maydell
Add missing 'U' suffixes to avoid potentially shifting into the sign bit of a signed integer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1392988008-15938-2-git-send-email-peter.maydell@linaro.org
2014-03-10libvixl: Fix format strings for several int64_t valuesStefan Weil
"%d" or "%x" won't work on hosts where int values are smaller than 64 bit. Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-id: 1394219753-26106-1-git-send-email-sw@weilnetz.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-10target-arm: Fix intptr_t vs tcg_target_longRichard Henderson
Fixes a build error when these are different, e.g. x32. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1394043257-4800-1-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-10target-arm: Implements the ARM PMCCNTR registerAlistair Francis
This patch implements the ARM PMCCNTR register including the disable and reset components of the PMCR register. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: bbf405e1feaf352cf39d5db402c9efcbd0f57c78.1393459802.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-10target-arm: Fix incorrect setting of E bit in CPSRPeter Maydell
Commit 4cc35614a moved the exception mask bits out of env->uncached_cpsr and into env->daif. However the env->daif contents are AArch64 style mask bits, which include not just the AArch32 AIF bits but also the new D bit (masks debug exceptions). This means that when reconstructing the AArch32 CPSR value we must not allow the D bit in env->daif to get into the CPSR, because the corresponding bit in the CPSR is E, the endianness bit. This bug didn't affect execution under TCG because we don't implement endianness-swapping and so simply ignored the E bit; however it meant that kernel booting under KVM failed, because KVM does honour the E bit. Reported-by: Alexey Ignatov <lexszero@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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