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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-06-07 17:30:59 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-07 17:31:23 +0100 |
| commit | 99801230e6616da497524016a5fa0f072a1fa084 (patch) | |
| tree | 2e404c8acaada4ecdee9539b978eb5010f701d92 | |
| parent | f01933c05ff6cb7fe9ad62cb9c067a38cf2fb37d (diff) | |
target/arm: Implement MVE VREV16, VREV32, VREV64
Implement the MVE instructions VREV16, VREV32 and VREV64.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/helper-mve.h | 7 | ||||
| -rw-r--r-- | target/arm/mve.decode | 4 | ||||
| -rw-r--r-- | target/arm/mve_helper.c | 13 | ||||
| -rw-r--r-- | target/arm/translate-mve.c | 33 |
4 files changed, 57 insertions, 0 deletions
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index bdd6675ea1..4c89387587 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -40,3 +40,10 @@ DEF_HELPER_FLAGS_3(mve_vclsw, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vclzb, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vclzh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vclzw, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vrev16b, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vrev32b, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vrev32h, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vrev64b, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vrev64h, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vrev64w, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index adceef9159..16ee511a5c 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -70,3 +70,7 @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vstr \ VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ... 0 @1op + +VREV16 1111 1111 1 . 11 .. 00 ... 0 0001 01 . 0 ... 0 @1op +VREV32 1111 1111 1 . 11 .. 00 ... 0 0000 11 . 0 ... 0 @1op +VREV64 1111 1111 1 . 11 .. 00 ... 0 0000 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 071c907059..055606b905 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -223,6 +223,12 @@ static uint32_t mask_to_bytemask4(uint16_t mask) return masks[mask & 0xf]; } +static uint64_t mask_to_bytemask8(uint16_t mask) +{ + return mask_to_bytemask4(mask) | + ((uint64_t)mask_to_bytemask4(mask >> 4) << 32); +} + #define DO_1OP(OP, ESIZE, TYPE, H, FN) \ void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ { \ @@ -251,3 +257,10 @@ DO_1OP(vclsw, 4, int32_t, H4, clrsb32) DO_1OP(vclzb, 1, uint8_t, H1, DO_CLZ_B) DO_1OP(vclzh, 2, uint16_t, H2, DO_CLZ_H) DO_1OP(vclzw, 4, uint32_t, H4, clz32) + +DO_1OP(vrev16b, 2, uint16_t, H2, bswap16) +DO_1OP(vrev32b, 4, uint32_t, H4, bswap32) +DO_1OP(vrev32h, 4, uint32_t, H4, hswap32) +DO_1OP(vrev64b, 8, uint64_t, , bswap64) +DO_1OP(vrev64h, 8, uint64_t, , hswap64) +DO_1OP(vrev64w, 8, uint64_t, , wswap64) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 3c6897548a..6f3d479607 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -211,3 +211,36 @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) DO_1OP(VCLZ, vclz) DO_1OP(VCLS, vcls) + +static bool trans_VREV16(DisasContext *s, arg_1op *a) +{ + MVEGenOneOpFn *fns[] = { + gen_helper_mve_vrev16b, + NULL, + NULL, + NULL, + }; + return do_1op(s, a, fns[a->size]); +} + +static bool trans_VREV32(DisasContext *s, arg_1op *a) +{ + MVEGenOneOpFn *fns[] = { + gen_helper_mve_vrev32b, + gen_helper_mve_vrev32h, + NULL, + NULL, + }; + return do_1op(s, a, fns[a->size]); +} + +static bool trans_VREV64(DisasContext *s, arg_1op *a) +{ + MVEGenOneOpFn *fns[] = { + gen_helper_mve_vrev64b, + gen_helper_mve_vrev64h, + gen_helper_mve_vrev64w, + NULL, + }; + return do_1op(s, a, fns[a->size]); +} |