diff options
| author | Alex Bennée <alex.bennee@linaro.org> | 2014-03-13 14:20:15 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-03-13 14:20:15 +0000 |
| commit | e7e11b22f604c02ed9ecbee50516c69b3a65ac87 (patch) | |
| tree | a368c2e006394bfd7b2010e7e38273a8b67c8be7 | |
| parent | 04e7c023decf3e39ce8f553d1d55f290650952d6 (diff) | |
target-arm: A64: Add FSQRT to C3.6.17 (two misc)
Implement FSQRT in the two-reg-misc category.
GCC uses this instruction form.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target-arm/translate-a64.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 1964c6dc0e..ed7b0c5497 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -6623,6 +6623,9 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u, case 0x6f: /* FNEG */ gen_helper_vfp_negd(tcg_rd, tcg_rn); break; + case 0x7f: /* FSQRT */ + gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env); + break; default: g_assert_not_reached(); } @@ -8392,6 +8395,12 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd); return; + case 0x7f: /* FSQRT */ + if (size == 3 && !is_q) { + unallocated_encoding(s); + return; + } + break; case 0x16: /* FCVTN, FCVTN2 */ case 0x17: /* FCVTL, FCVTL2 */ case 0x18: /* FRINTN */ @@ -8416,7 +8425,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) case 0x7b: /* FCVTZU */ case 0x7c: /* URSQRTE */ case 0x7d: /* FRSQRTE */ - case 0x7f: /* FSQRT */ unsupported_encoding(s, insn); return; default: @@ -8493,6 +8501,9 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ gen_helper_vfp_negs(tcg_res, tcg_op); break; + case 0x7f: /* FSQRT */ + gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); + break; default: g_assert_not_reached(); } |