diff options
| author | John Stultz <john.stultz@linaro.org> | 2017-01-24 16:28:28 -0800 |
|---|---|---|
| committer | John Stultz <john.stultz@linaro.org> | 2017-01-24 20:30:52 -0800 |
| commit | e797cb39b1b8cf5fdf3776c892e3d3836022d4cc (patch) | |
| tree | d121a6c4b94dd7953fa4827550e61dde8f831019 | |
| parent | 2ff92ce375925e939b0be1d05405980b89ae5eb0 (diff) | |
dts: hisi3660-hikey960: Add reboot reason registers to dtsdev/hi3660-aosp
Add reboot reason register to dts, so that reboot bootloader
might be able to work.
Part of the pmic overlapped the memory regiser, so I've shortened
that dts entry. There may be a better way to implement this.
NOTE: Unfortunately, while I was provided the register, I wasn't
provided the reboot values, so I've guessed here. At the moment
system reboot doesn't function properly, so this can't really be
validated, but when hitting the reset button on the serial mezzanine
after system reboot fails, we seem to go into the desired boot mode
reliably.
ALSO: This uses an older method that was used w/ 4.4, upstream
has proper support as of 4.6ish so this will need to be reworked
on newer kernels.
Signed-off-by: John Stultz <john.stultz@linaro.org>
| -rw-r--r-- | arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 35606079a12c..ad023ba20c6c 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -38,6 +38,13 @@ reg = <0x0 0x00400000 0x0 0xBFE00000>; }; + reboot_reason: reboot-reason@0xfff34404{ + compatible = "linux,reboot-reason-sram"; + reg = <0x0 0xFFF34404 0x0 0x4>; + reason,none = <0x0>; + reason,bootloader = <0xff>; + }; + soc { uart5: uart@fdf05000 { status = "ok"; @@ -65,7 +72,7 @@ pmic: pmic@fff34000 { compatible = "hisilicon,hi6421-pmic"; - reg = <0x0 0xfff34000 0x0 0x1000>; + reg = <0x0 0xfff34000 0x0 0x400>; interrupt-controller; #interrupt-cells = <2>; |