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2016-05-05target: armv8: Define extra DSCR constantsarmv8_fix_low_level_accessdev/armv8_fix_low_level_accessPhilip Attfield
Signed-off-by: Philip Attfield <philip.attfield@linaro.org> [daniel.thompson@linaro.org: Decomposed Philip's WIP patches into atomic changes and provided a commit message] Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
2016-05-05target: armv8: Remove obsolete code to substitute registersDaniel Thompson
Currently regnum 16 is secretly switched to regnum 17. This is a hack from 32-bit ARM land (to normalize ARMv7-A and ARMv7-M behaviour) and has no business being in this code. This patch is a re-expression of a bug fix from Philip Attfield. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
2016-05-05target: armv8: Extend register reads to be 64-bitDaniel Thompson
Currently the register read functions extracts 64-bit registers from the target but only stores 32-bits into the register cache. This patch is a re-expression of a bug fix from Philip Attfield. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
2016-05-05target: armv8: Allocate enough space for registersPhilip Attfield
Currently only 32-bits are allocated to hold 64-bit registers. Nothing good can come from that. Fix it. Signed-off-by: Philip Attfield <philip.attfield@linaro.org> [daniel.thompson@linaro.org: Decomposed Philip's WIP patches into atomic changes and provided a commit message] Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
2016-05-05target: aarch64: Replace magic values used during steppingPhilip Attfield
This is a non-functional improvement to boost readability. Signed-off-by: Philip Attfield <philip.attfield@linaro.org> [daniel.thompson@linaro.org: Decomposed Philip's WIP patches into atomic changes and provided a commit message] Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
2016-05-05target: aarch64: Add command to display MMU/cache statusPhilip Attfield
Provide a target specific command to display the state of the MMU: MMU: enabled, D-Cache: enabled, I-Cache: enabled This command is mostly useful during bootloader (and very early kernel boot) development. Signed-off-by: Philip Attfield <philip.attfield@linaro.org> [daniel.thompson@linaro.org: Decomposed Philip's WIP patches into atomic changes and provided a commit message] Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
2016-05-05target: aarch64: Rename the architecture specific cmd prefixPhilip Attfield
Naming the architecture specific commands "cortex_a" is confusing (and wrong since Cortex-A describes a *implementation* not an architecture). Signed-off-by: Philip Attfield <philip.attfield@linaro.org> [daniel.thompson@linaro.org: Decomposed Philip's WIP patches into atomic changes and provided a commit message] Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
2016-05-05target: aarch64: Spelling and formatting correctionsPhilip Attfield
Signed-off-by: Philip Attfield <philip.attfield@linaro.org> [daniel.thompson@linaro.org: Decomposed Philip's WIP patches into atomic changes] Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
2016-05-05gdbserver: Ensure all address handling is 64-bit safePhilip Attfield
Note that addresses for watchpoints and memory CRC are *not* expanded to 32-bits because the watchpoint API has not been extended for 64-bit usage yet. Signed-off-by: Philip Attfield <philip.attfield@linaro.org> [daniel.thompson@linaro.org: Decomposed Philip's WIP patches into atomic changes and provided a commit message] [daniel.thompson@linaro.org: Reviewed file. Identified and fixed additional places where address are truncated.] Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
2015-07-31armv8: Add a working aarch64_read_apb_ab_memory function.Peter Griffin
This fixes the last known problem I had which was stopping OpenOCD / GDB coming to life. Philip provided this read_memory routine from some other armv8 patches which were floating around on the web. Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
2015-07-31gdbinit: Example gdbinit for getting gdb ti automatically connect.Peter Griffin
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
2015-07-31aarch64: Update armv8_regs to match linaro gdb toolchain.Peter Griffin
Patch provided by Philip Attfield. Allows GDB to connect properly. Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
2015-07-31hi6220: Add a gdbattach, and better reset configPeter Griffin
Changes provided by Philip Attfield, enable better reset control. Bump the JTAG clock speed now we have it working. Also add a gdbattach function. Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
2015-07-17hi6220: Add initial TCL support for hi6220Peter Griffin
This patch adds support for the hi6220 SoC which has octocore A53 cpu's. Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
2015-02-03aarch64: Add ARMv8 AARCH64 step, bp, mmu and cache identifypierre Kuo
Based on David Ung's aarch64, I add step, bp mmu and cache identify 1. create armv8_dpm.c for handling v8 dpm operations. 2. add 64-bits address breakpoint support. 3. parsing cspr and record different processor state and modes. 4. add sctlr and cache identity parsing. Below is sp, bp, mmu/cache identity, and processor state and modes parsing > bp 0x220 4 hw breakpoint set at 0x 00000220 > resume target state: halted target halted in ARM64 state due to breakpoint, current mode: EL3H cpsr: 0x600003cd pc: 0x220 MMU: disabled, D-Cache: disabled, I-Cache: disabled > rbp 0x220 > step target state: halted target halted in ARM64 state due to breakpoint, current mode: EL1H cpsr: 0x000001c5 pc: 0x250 MMU: disabled, D-Cache: disabled, I-Cache: disabled > bp 0x3f0 4 hw breakpoint set at 0x 000003f0 > resume target state: halted target halted in ARM64 state due to breakpoint, current mode: EL1H cpsr: 0x60000005 pc: 0x3f0 MMU: enabled, D-Cache: enabled, I-Cache: enabled > ===================================================================================== Below is showing openocd can get different target halt reason, breakpoing or debug-request ===================================================================================== Trying 127.0.0.1... Connected to localhost. Escape character is '^]'. Open On-Chip Debugger > halt number of cache level 2 cache l2 present :not supported fpga_668.cpu cluster 0 core 0 multi core target state: halted target halted in ARM64 state due to debug-request, current mode: EL3H cpsr: 0x000003cd pc: 0x0 MMU: disabled, D-Cache: disabled, I-Cache: disabled > bp 0x220 4 hw breakpoint set at 0x 00000220 > resume target state: halted target halted in ARM64 state due to breakpoint, current mode: EL3H cpsr: 0x600003cd pc: 0x220 MMU: disabled, D-Cache: disabled, I-Cache: disabled > ===================================================================================== Change-Id: I2e659be58965cbfe2435aa990585d9add3046c30 Signed-off-by: pierre Kuo <vichy.kuo@gmail.com>
2015-01-29aarch64: Add ARMv8 AARCH64 support filesDavid Ung
Add new AARCH64 target and ARMv8 support files. This is an instantiation from the cortex_a files but modified to support 64bit ARMv8. Not all features are complete, notably breakpts and single stepping are not yet implemented. Currently it lets you halt of the processors, resume, dump the cpu registers and even get a stack trace with gdb. > halt invalid mode value encountered 5 target state: halted unrecognized psr mode: 0x5 target halted in ARM state due to debug-request, current mode: UNRECOGNIZED cpsr: 0x600001c5 pc: 0x00093528 MMU: disabled, D-Cache: disabled, I-Cache: disabled > targets TargetName Type Endian TapName State -- ------------------ ---------- ------ ------------------ ------------ 0* cpu0 aarch64 little cpu.dap halted > reg ===== arm v8 registers (0) r0 (/64): 0x00000000FFFFFFED (dirty) (1) r1 (/64): 0x00000000F76E4000 (2) r2 (/64): 0x0000000000000000 (3) r3 (/64): 0x0000000000010000 (4) r4 (/64): 0xFFFFFFC06E2939E1 (5) r5 (/64): 0x0000000000000018 (6) r6 (/64): 0x003A699CFB3C8480 (7) r7 (/64): 0x0000000053555555 (8) r8 (/64): 0x00FFFFFFFFFFFFFF (9) r9 (/64): 0x000000001FFEF992 (10) r10 (/64): 0x0000000000000001 (11) r11 (/64): 0x0000000000000000 (12) r12 (/64): 0x00000000000000F0 (13) r13 (/64): 0x00000000EFDFEAC8 (14) r14 (/64): 0x00000000F6DDA659 (15) r15 (/64): 0x0000000000000000 (16) r16 (/64): 0xFFFFFFC0000F9094 (17) r17 (/64): 0x0000000000000000 (18) r18 (/64): 0x0000000000000000 (19) r19 (/64): 0xFFFFFFC00087C000 (20) r20 (/64): 0x0000000000000002 (21) r21 (/64): 0xFFFFFFC000867C28 (22) r22 (/64): 0xFFFFFFC000916A52 (23) r23 (/64): 0xFFFFFFC00116D8B0 (24) r24 (/64): 0xFFFFFFC000774A0C (25) r25 (/64): 0x000000008007B000 (26) r26 (/64): 0x000000008007D000 (27) r27 (/64): 0xFFFFFFC000080450 (28) r28 (/64): 0x0000004080000000 (29) r29 (/64): 0xFFFFFFC00087FF20 (30) r30 (/64): 0xFFFFFFC000085114 (31) sp (/64): 0xFFFFFFC00087FF20 (32) pc (/64): 0xFFFFFFC000093528 (33) xPSR (/64): 0x00000000600001C5 And from gdb (gdb) bt #0 cpu_do_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/mm/proc.S:87 #1 0xffffffc000085114 in arch_cpu_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/kernel/process.c:107 #2 0x0000000000000000 in ?? () Change-Id: Iccb1d15c7d8ace7b9e811dac3c9757ced4d0f618 Signed-off-by: David Ung <davidu@nvidia.com>
2015-01-27arm_dpm: Add 64bit register handling.David Ung
Add various function to read/write ARMv8 registers. Change-Id: I16f2829bdd0e87b050a51e414ff675d5c21bcbae Signed-off-by: David Ung <davidu@nvidia.com>
2015-01-27target: Allow target 64bit addressing readsDavid Ung
Modify various function to allow 64bit addressing reads to memory. Change-Id: I944786ec7eabac4605fad682739bbb25c30d9ba2 Signed-off-by: David Ung <davidu@nvidia.com>
2015-01-23server: Allow 64 address to be send over GBD serverDavid Ung
Accept 64 bit addresses from GDB read memory packet. This is needed for aarch64 support. Change-Id: I9bf7b44affe24839cf30897c55ad17fdd29edf14 Signed-off-by: David Ung <davidu@nvidia.com>
2015-01-23arm_dpm: Add arch_mode parameter to arm_dpm_setupDavid Ung
Extend the arm_dpm_setup function with new arch_mode parameter in anticipation for aarch64 support. Change-Id: I72ce0486b31a2760600fdd2b57b0955b406e4e44 Signed-off-by: David Ung <davidu@nvidia.com>
2015-01-15target/stm32xx: Endian is not configurable.Karl Palsson
So remove it from all the configs, it's misleading, and leads to cargo culting of config files. Change-Id: I2b77e60d5e96f9759c7c9fc91b20e73be2e95d9a Signed-off-by: Karl Palsson <karlp@tweak.net.au> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2446 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-01-15flash: add AT91SAM4SD16C deviceJörg Wunsch
Change-Id: I12f740a1a2d10637b0e5b1e8d054dd912576d190 Signed-off-by: Jörg Wunsch <openocd@uriah.heep.sax.de> Reviewed-on: http://openocd.zylin.com/2455 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-01-15contrib: itmdump: fix multi byte decodingKarl Palsson
Incorrect byte manipulations. Change-Id: Id8c3f457b39f4b2b75613076d403359c4972a69d Signed-off-by: Karl Palsson <karlp@tweak.net.au> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2448 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-01-15tcl/interface/ftdi: add config for the IoT-LAB adapterPaul Fertser
This is an integrated adapter used on the IoT-LAB boards. Schematics are available from https://github.com/iot-lab/iot-lab/wiki/Docs/openm3-schematics.pdf Change-Id: I1c80e72653c3f319bb04d01e3dfddb1c2447c398 Tested-by: Quentin Lampin <quentin.lampin@orange.com> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2415 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-01-15tcl/board: Add TI TMDX570LS20SUSB board configAndreas Färber
It is derived from ti_tmdx570ls31usb.cfg, using a different TAP ID. Change-Id: I2d911995c76ea4f75a780cc230d61f4959825809 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/2440 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-01-15stlink: add reconfigurable speed supportSpencer Oliver
The ability to change the speed has been added to firmware versions J22 and above. Any attempt to change on earlier versions will be ignored without error, as the existing code does. For supported firmware versions the driver will attempt to get as close as possible to supported speeds (never higher). The default stlink speed on power up is 1.8MHz. The driver will now also print supported clocl speeds during init. Change-Id: Iee9bd018bb8b6f94672a12538912d41c23d48a7e Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/2335 Tested-by: jenkins
2015-01-15hla: add ability to change adapter speed (if supported)Spencer Oliver
As a note we need to cache the requested speed setting, as the hla interface may not be ready when the first adapter_khz is called. Change-Id: I2fa6807d5f0bd3f0365cf178bd10a230c39415a7 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/2334 Tested-by: jenkins
2015-01-15cfg: stm32l1: Use specific chipnameKarl Palsson
This should have been corrected earlier with the split of l1/l0 code apart. Change-Id: I87b94a310ae7e76318554a9cd2705348a942d58b Signed-off-by: Karl Palsson <karlp@tweak.net.au> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2447 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-01-15jtag/hla: output possible idcode candidates in case of mismatchPaul Fertser
Output a similar message to what we have on low-level JTAG adapters to avoid confusing users. Reported on IRC by chickensk. Change-Id: I96d58410ef715b966e32d79c0aacf38596c5eb3f Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2451 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-01-15jtag: Avoid extra SRSTn resets when connectingEvan Hunter
Previously the jtag_add_reset(1, 0) caused the processor to be released, and if SRSTn existed then it would then be reset again two lines later. Change-Id: I58b7a12607f46f83caa7ed3b3cebc4195eb51ef6 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/2398 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-01-15docs: update bug tracker URLSpencer Oliver
Change-Id: I6a362020a29ccb9222f7909b5b34e5c35a02ed4b Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/2454 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-01-15lpc2000: Improve lpc2000 flash driver.Nemui Trinomius
This patch adds flash programming support for LPC5410x and LPC82x. And adds auto flash size detection for LPC800 series. Tested on below listed boards/chips. LPC54102(LPCLPC54102Xpresso) LPC824(LPCXpresso824-MAX) LPC812(LPC812MAX) LPC811,LPC810 Change-Id: Ie68b6d425b17ccfa83814607ee61056e99800c1c Signed-off-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp> Reviewed-on: http://openocd.zylin.com/2442 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-01-10cortex_a: Add support for A7 MPCoreAlexander Stein
A7 MPCore needs unlocking the debug registers same as with A15 MPCore. Found out by hacking on the code. Change-Id: I613cb4fb35007b85b4a9a401577b47768bc1a08b Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Reviewed-on: http://openocd.zylin.com/2344 Tested-by: jenkins Reviewed-by: Kamal Dasu <kamal.dasu@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-01-10cortex_a: Add support for A15 MPCoreKamal Dasu
Added Cortex-A15 support for DAP AHB-AP init code as per ADI V5 spec. Also added changes to make the APB MEM-AP to work with A15. Made the the cortex_a target code generic to work with A8, A9 and A15 single core or multicore implementation. Added armv7a code for os_border calculation to work for known A8, A9 and A15 platforms based on the ARM DDI 0344H, ARM DDI 0407F, ARM DDI 0406C ARMV7A architecture docs. Change-Id: Ib2803ab62588bf40f1ae4b9192b619af31525a1a Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-on: http://openocd.zylin.com/1601 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-01-09ChibiOS: struct ChibiOS_params_list[] should not be constTomas Vanek
Procedure ChibiOS_update_memory_signature() sets struct member signature. Change-Id: I45adbd14fa7cda99413fd0b516d45b3fb55e322d Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/2427 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-01-09transport: clarify error message when transport is not selectedKarl Palsson
When no transport is selected, the error message dumps the available transports, but not how to actually select one. Change-Id: I63da2a4b59e3f6cc8d30bd631e41a82636a056ef Signed-off-by: Karl Palsson <karlp@tweak.net.au> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2406 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-01-09flash: fix kinetis driver typosSpencer Oliver
Change-Id: I0a4557f08507c61cb8ab33b38d2b6b069c344c09 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/2385 Tested-by: jenkins
2015-01-09cfg: fix lpc17xx regressionSpencer Oliver
commit b5a6ba46 broke the following board files, update to new cfg. Change-Id: Ic3b776bd32eb72eae6ad1e130e329268ce9ba71a Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/2384 Tested-by: jenkins
2015-01-09avoid segfaulting when attempting to set an unavailable type of breackpointSalvador Arroyo
For example "bp 0x20000000 8 2" makes openocd segfaulting on a stm32f4x Discovery board. Change-Id: I1ddd46b1fa9ade78db2234ed975ccefb72539331 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/2342 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-01-09Mac/PPC: Fix build.Jens Bauer
GCC-4.2 on Mac/PPC complains about size_t is expected for %zx and the build stops. In order to avoid other problems, I've chosen simply to typecast. Change-Id: I99b569c4d1100e729712e31d24d6539f8b5971b6 Signed-off-by: Jens Bauer <jens@gpio.dk> Reviewed-on: http://openocd.zylin.com/2360 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-01-09swd: handle various failure conditionsPaul Fertser
When communication with target fails for whatever reason, it makes sense to do JTAG-to-SWD (in case the target got power-cycled or the DAP method was reset anyhow), SWD line reset sequence (part of JTAG-to-SWD already) and the mandatory IDCODE read. Schedule that to be performed on the next poll. Fix the return values for ftdi and jlink drivers to be consistent with OpenOCD error codes and remove ad-hoc calls to perform DAP method switching (as it's now done from the upper layer automatically). Change-Id: Ie18797d4ce7ac43d8249f8f81f1064a2424e02be Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2371 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Mateusz Manowiecki <segmentation@fault.pl>
2015-01-09target: improve robustness of polling and reexaminationPaul Fertser
When a target was present on OpenOCD start but later disappeared for whatever reason (typically unstable connection or target going to sleep) and reappeared only for a brief period of time, reexamination would fail, and poll would no longer run. This patch fixes it. Change-Id: I61f9b5a3f366a761320e233f4e1689f926b5556d Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2370 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2015-01-09rtos: free gdb packet allocated memorySpencer Oliver
compile tested only. Change-Id: I3bc06c212967a3ce44a875f802b554c178537d1d Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/2382 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-01-08checkpatch: fix check for the FSF addressPaul Fertser
Commit 4525c0a4c4d0aaa199c37a6d2245617e8445f213 cherry-picked check for the FSF address presence from upstream. However, it has a typo resulting in this obscure error when triggered: Use of uninitialized value in concatenation (.) or string at /home/jenkins/.jenkins/jobs/openocd-gerrit/workspace/tools/scripts/checkpatch.pl line 1258. ERROR: This patch fixes it. Change-Id: Ia417ef4782d21c8b3f1d39de88c4ab850a5a6630 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2414 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-01-07jtag: Remove unnecessary global variableAndreas Fritiofson
Change-Id: I96e5f13b12da2970eafc5fca24b7952d427eeca9 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/2235 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-01-07jtag: Fix memory leaks in jtag_tap_free()Andreas Fritiofson
Change-Id: I953fbb346fbf168fb50b349d245f2aa64dbfdcb3 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/2234 Tested-by: jenkins
2014-12-03stm32l: split l0/l1 support no jtag, different HSI settingsKarl Palsson
L0 is cortex m0+, so different id codes, SWD only, different addresses for the clock speedup. It has no endian options, no boundary scan. Removed all L0 specific portions from L1 files, and renamed files to clarify their purpose. The deprecated stm32lx_stlink.cfg is kept as is, as it is only around for backwards compatibility with prior releases. Tested on STM32L053 Discovery and STM32L151 Discovery. Has _not_ been tested with jtag on L1. Change-Id: I8eea890d2f92a302d9e9c8a8832d218ee1b6bcfc Signed-off-by: Karl Palsson <karlp@tweak.net.au> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2405 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Juha Niskanen <juha.niskanen@haltian.com>
2014-12-03stm32: Fix L0/1xx CPUTAPID setting and add new L1xx BSTAPIDsJuha Niskanen
Fix script parse error, when using JTAG, introduced in commit 0187ced9ed2 Add several BS TAPIDs with comments about ST documentation. Change-Id: I8d0370b244ccaf7ea0dbe1919bfad1915f7317d4 Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com> Reviewed-on: http://openocd.zylin.com/2376 Tested-by: jenkins Reviewed-by: Rémi PRUD'HOMME <prudhomme.remi@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-11-24tcl/target/stm32f4: ramp up JTAG speed, HSI is 16MHz thereUwe Bonnes
Since all F4 parts have an internal HSI providing 16MHz, it's safe to use 2MHz JTAG frequency by default. Change-Id: I2702d5a1d642d4acd4af2db54c028949132c6900 Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2383 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-11-24tcl/target/stm32f4x: add F401 and F411 IDsUwe Bonnes
Change-Id: I12079586dafb8a7614bdf4cc0b13cd5030301742 Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-on: http://openocd.zylin.com/2379 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-04 09:22:10 +0000