diff options
author | Pankaj Bansal <pankaj.bansal@nxp.com> | 2019-05-10 20:05:41 +0530 |
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committer | Daniel Thompson <daniel@redfelineninja.org.uk> | 2019-09-17 22:29:33 +0100 |
commit | bab71de4ff33442716c3f2e787c0172fa48743be (patch) | |
tree | 021a024dd9ca31f05b32cd0a987f2f77cf210ce4 | |
parent | bbacac665571200083bd313e7e518c70b8671e21 (diff) |
Documentation: can: flexcan: Add flexcan clocks' information
The clocking information is missing from flexcan device tree bindings.
This information is needed to be able to use flexcan. Document the same.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
-rw-r--r-- | Documentation/devicetree/bindings/net/can/fsl-flexcan.txt | 46 |
1 files changed, 44 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt index bc77477c6878..a0538032b6a7 100644 --- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt +++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt @@ -12,9 +12,42 @@ Required properties: - reg : Offset and length of the register set for this device - interrupts : Interrupt tuple for this device -Optional properties: +Clocking information is must for flexcan. please refer below info for +understanding clocking in flexcan: + +• The FLEXCAN module is divided into two blocks. Controller host interface + ("CHI") and Protocol Engine ("PE") +• Both these blocks require clock. +• CHI is responsible for registers read write including MB read/write. + While PE is responsible for Transfer/receive data on CAN bus. +• The clocks feeding to these two blocks can be synchronous (i.e. same clock) + or asynchronous (i.e. separate clocks). +• Selection is made in the CLK_SRC bit (bit 13) of Control 1 Register. + - CLK_SRC = 0, asynchronous i.e. separate clocks for CHI and PE + - CLK_SRC = 1, synchronous i.e. CHI clock is used for PE and PE + clock is not used. +• If this bit is not implemented in SOC, then SOC only supports asynchronous + clocks. +• Either of the clock can be generated by any of the clock source. +• When the two clocks are asynchronous, then following restrictions apply to + PE clock. + - PE clock must be less than CHI clock. +• If low jitter is required on CAN bus, dedicated oscillator can be used to + provide PE clock, but it must be less than CHI clock. + +Base on above information clocking info in flexcan can be defined in two ways: + +Method 1(Preferred): + - clocks: phandle to the clocks feeding the flexcan. Two can be given: + - "ipg": Protocol Engine clock + - "per": Controller host interface clock + - clock-names: Must contain the clock names described just above. -- clock-frequency : The oscillator frequency driving the flexcan device +Method 2(Not Preferred): + - clock-frequency : The synchronous clock frequency supplied to both + Controller host interface and Protocol Engine + +Optional properties: - xceiver-supply: Regulator that powers the CAN transceiver @@ -41,3 +74,12 @@ Example: interrupt-parent = <&mpic>; clock-frequency = <200000000>; // filled in by bootloader }; + + can@2180000 { + compatible = "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysclk>, <&clockgen 4 7>; + clock-names = "ipg", "per"; + status = "disabled"; + }; |