/*
 * Hisilicon Ltd. Hi3620 SoC
 *
 * Copyright (C) 2012-2013 Linaro Ltd.
 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * publishhed by the Free Software Foundation.
 */

/include/ "skeleton.dtsi"

/ {
	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		mshc0 = &dwmmc_0;
		mshc1 = &dwmmc_1;
		mshc2 = &dwmmc_2;
		mshc3 = &dwmmc_3;
	};

	amba {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "arm,amba-bus";
		interrupt-parent = <&intc>;
		ranges;

		timer@fc000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xfc000600 0x20>;
			interrupts = <1 13 0xf01>;
			clocks = <&armpll0>;
		};

		pmctrl: pmctrl@fca08000 {
			compatible = "hisilicon,pmctrl";
			reg = <0xfca08000 0x1000>;
		};

		pctrl: pctrl@fca09000 {
			compatible = "hisilicon,pctrl";
			reg = <0xfca09000 0x1000>;
		};

		secram: secram@f8000000 {
			compatible = "hisilicon,secram";
			reg = <0xf8000000 0x14000>;
		};

		ddrcfg: ddrcfg@fcd00000 {
			compatible = "hisilicon,ddrcfg";
			reg = <0xfcd00000 0x2000>;
		};

		/*clocks begins*/
		clocks {
			#address-cells = <1>;
			#size-cells = <0>;

			osc32k: osc@0 {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <32768>;
				clock-output-names = "osc32khz";
			};

			osc26m: osc@1 {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <26000000>;
				clock-output-names = "osc26mhz";
			};

			pclk: clk@0 {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <26000000>;
				clock-output-names = "apb_pclk";
			};

			timclk0: clk@1 {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <60000000>;
				clock-output-names = "timer0";
			};

			timclk1: clk@2 {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <60000000>;
				clock-output-names = "timer1";
			};

			/*------pll clk------*/
			armpll0: pll0 {
				compatible = "hisilicon,pll";
				#clock-cells = <0>;
				clocks = <&osc26m>;
				clock-frequency = <1600000000>;
				clock-output-names = "clk_armpll0";
			};
			armpll1: pll1 {
				compatible = "hisilicon,pll";
				#clock-cells = <0>;
				clocks = <&osc26m>;
				clock-frequency = <1600000000>;
				clock-output-names = "clk_armpll1";
			};
			peripll: pll2 {
				compatible = "hisilicon,pll";
				#clock-cells = <0>;
				clocks = <&osc26m>;
				clock-frequency = <1440000000>;
				clock-output-names = "clk_armpll2";
			};
			testsdclk: testsd {
				compatible = "hisilicon,pll";
				#clock-cells = <0>;
				clocks = <&peripll>;
				clock-frequency = <100000000>;
			};
			usbpll: pll3 {
				compatible = "hisilicon,pll";
				#clock-cells = <0>;
				clocks = <&osc26m>;
				clock-frequency = <1440000000>;
				clock-output-names = "clk_armpll3";
			};

			hdmipll: pll4 {
				compatible = "hisilicon,pll";
				#clock-cells = <0>;
				clocks = <&osc26m>;
				clock-frequency = <1188000000>;
				clock-output-names = "clk_armpll4";
			};

			gpupll: pll5 {
				compatible = "hisilicon,pll";
				#clock-cells = <0>;
				clocks = <&osc26m>;
				clock-frequency = <1300000000>;
				clock-output-names = "clk_armpll5";
			};

			/*--------------cfgaxi clock--------------------*/
			clk_cfgaxi: cfgaxi {
				compatible = "hisilicon,cfgaxi";
				#clock-cells = <0>;
				clocks = <&peripll>;
				/*mult, div*/
				hisilicon,fixed-factor = <1 30>;
			};

			/*-------------------mux clock-------------------*/
			clk_uart0_mux: uart0_mux {
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&osc26m &clk_cfgaxi>;
				/*select register offset, mask*/
				hisilicon,hi3620-clkmux = <0x100 0x80>;
			};

			clk_uart1_mux: uart1_mux {
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&osc26m &clk_cfgaxi>;
				hisilicon,hi3620-clkmux = <0x100 0x100>;
			};

			clk_uart2_mux: uart2_mux {
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&osc26m &clk_cfgaxi>;
				hisilicon,hi3620-clkmux = <0x100 0x200>;
			};

			clk_uart3_mux: uart3_mux {
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&osc26m &clk_cfgaxi>;
				hisilicon,hi3620-clkmux = <0x100 0x400>;
			};

			clk_uart4_mux: uart4_mux {
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&osc26m &clk_cfgaxi>;
				hisilicon,hi3620-clkmux = <0x100 0x800>;
			};

			/*---------------------gate clock-------------------*/
			clk_uart0: uart0 {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&clk_uart0_mux>;
				/*enable register, enable bit*/
				hisilicon,hi3620-clkgate = <0x40 16>;
				clock-output-names = "clk_uart0";
			};

			clk_uart1: uart1 {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&clk_uart1_mux>;
				hisilicon,hi3620-clkgate = <0x40 17>;
				clock-output-names = "clk_uart1";
			};

			clk_uart2: uart2 {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&clk_uart2_mux>;
				hisilicon,hi3620-clkgate = <0x40 18>;
				clock-output-names = "clk_uart2";
			};

			clk_uart3: uart3 {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&clk_uart3_mux>;
				hisilicon,hi3620-clkgate = <0x40 19>;
				clock-output-names = "clk_uart3";
			};

			clk_uart4: uart4 {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&clk_uart4_mux>;
				hisilicon,hi3620-clkgate = <0x40 20>;
				clock-output-names = "clk_uart4";
			};

			/*-------------------spi clock----------------*/

			clk_spi0_mux: spi0_mux {
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&osc26m &clk_cfgaxi>;
				hisilicon,hi3620-clkmux = <0x100 0x1000>;
			};

			clk_spi1_mux: spi1_mux {
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&osc26m &clk_cfgaxi>;
				hisilicon,hi3620-clkmux = <0x100 0x2000>;
			};

			clk_spi2_mux: spi2_mux {
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&osc26m &clk_cfgaxi>;
				hisilicon,hi3620-clkmux = <0x100 0x4000>;
			};

			clk_spi0: spi0 {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&clk_spi0_mux>;
				hisilicon,hi3620-clkgate = <0x40 21>;
				clock-output-names = "clk_spi0";
			};

			clk_spi1: spi1 {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&clk_spi1_mux>;
				hisilicon,hi3620-clkgate = <0x40 22>;
				clock-output-names = "clk_spi1";
			};

			clk_spi2: spi2 {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&clk_spi2_mux>;
				hisilicon,hi3620-clkgate = <0x40 23>;
				clock-output-names = "clk_spi2";
			};

			/*-------------------mux clock----------------*/
			clk_pwm0_mux: pwm0_mux{
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&osc32k &osc26m>;
				hisilicon,hi3620-clkmux = <0x104 0x400>;
			};

			clk_venc_mux: venc_mux{
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&peripll &usbpll>;
				hisilicon,hi3620-clkmux = <0x10c 0x800>;
			};

			clk_g2d_mux: g2d_mux{
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&peripll &usbpll>;
				hisilicon,hi3620-clkmux = <0x10c 0x20>;
			};

			clk_vdec_mux: vdec_mux{
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&peripll &usbpll>;
				hisilicon,hi3620-clkmux = <0x110 0x20>;
			};

			clk_vpp_mux: vpp_mux{
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&peripll &usbpll>;
				hisilicon,hi3620-clkmux = <0x110 0x800>;
			};

			clk_ldi0_mux: ldi0_mux{
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&peripll &usbpll &hdmipll>;
				hisilicon,hi3620-clkmux = <0x114 0x6000>;
			};

			clk_ldi1_mux: ldi1_mux{
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&peripll &usbpll &hdmipll>;
				hisilicon,hi3620-clkmux = <0x118 0xc000>;
			};

			/*----periclock: gate clk, reg offset to sctrl-----*/

			clk_sci: sci {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&osc26m>;
				/*enable register, enable bit*/
				hisilicon,hi3620-clkgate = <0x40 26>;
				clock-output-names = "clk_sci";
			};

			clk_dphy0: dphy0 {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&osc26m>;
				hisilicon,hi3620-clkgate = <0x30 15>;
				clock-output-names = "clk_dphy0";
			};

			clk_dphy1: dphy1 {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&osc26m>;
				hisilicon,hi3620-clkgate = <0x30 16>;
			};

			clk_dphy2: dphy2 {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&osc26m>;
				hisilicon,hi3620-clkgate = <0x30 17>;
			};

			clk_kpc: kpc {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&osc32k>;
				hisilicon,hi3620-clkgate = <0x20 6>;
			};

			clk_pwm0_gate: pwm0_gate {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&osc32k &osc26m>;
				hisilicon,hi3620-clkgate = <0x40 7>;
			};

			/*gpio0-----gpio21   gate clock*/
			clk_gpio0: gpio0{
				compatible = "hisilicon,periclock";
				hisilicon,hi3620-clkgate = <0x20 8>;
				clock-output-names = "clk_gpio0";
			};
			clk_gpio1: gpio1{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 9>;
				clock-output-names = "clk_gpio1";
			};
			clk_gpio2: gpio2{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 10>;
				clock-output-names = "clk_gpio2";
			};
			clk_gpio3: gpio3{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 11>;
				clock-output-names = "clk_gpio3";
			};
			clk_gpio4: gpio4{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 12>;
				clock-output-names = "clk_gpio4";
			};
			clk_gpio5: gpio5{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 13>;
				clock-output-names = "clk_gpio5";
			};
			clk_gpio6: gpio6{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 14>;
				clock-output-names = "clk_gpio6";
			};

			clk_gpio7: gpio7{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 15>;
				clock-output-names = "clk_gpio7";
			};
			clk_gpio8: gpio8{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 16>;
				clock-output-names = "clk_gpio8";
			};
			clk_gpio9: gpio9{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 17>;
				clock-output-names = "clk_gpio9";
			};
			clk_gpio10: gpio10{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 18>;
				clock-output-names = "clk_gpio10";
			};
			clk_gpio11: gpio11{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 19>;
				clock-output-names = "clk_gpio11";
			};
			clk_gpio12: gpio12{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 20>;
				clock-output-names = "clk_gpio12";
			};
			clk_gpio13: gpio13{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 21>;
				clock-output-names = "clk_gpio13";
			};
			clk_gpio14: gpio14{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 22>;
				clock-output-names = "clk_gpio14";
			};
			clk_gpio15: gpio15{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 23>;
				clock-output-names = "clk_gpio15";
			};
			clk_gpio16: gpio16{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 24>;
				clock-output-names = "clk_gpio16";
			};
			clk_gpio17: gpio17{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 25>;
				clock-output-names = "clk_gpio17";
			};
			clk_gpio18: gpio18{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 26>;
				clock-output-names = "clk_gpio18";
			};
			clk_gpio19: gpio19{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 27>;
				clock-output-names = "clk_gpio19";
			};
			clk_gpio20: gpio20{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 28>;
				clock-output-names = "clk_gpio20";
			};
			clk_gpio21: gpio21{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				hisilicon,hi3620-clkgate = <0x20 29>;
				clock-output-names = "clk_gpio21";
			};

			/*i2c clk*/
			clk_i2c0: i2c0{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&clk_cfgaxi>;
				hisilicon,hi3620-clkgate = <0x40 24>;
				clock-output-names = "clk_i2c0";
			};
			clk_i2c1: i2c1{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&clk_cfgaxi>;
				hisilicon,hi3620-clkgate = <0x40 25>;
				clock-output-names = "clk_i2c1";
			};
			clk_i2c2: i2c2{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&clk_cfgaxi>;
				hisilicon,hi3620-clkgate = <0x40 28>;
				clock-output-names = "clk_i2c2";
			};
			clk_i2c3: i2c3{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&clk_cfgaxi>;
				hisilicon,hi3620-clkgate = <0x40 29>;
				clock-output-names = "clk_i2c3";
			};

			/* clk_acp */
			clk_acp: acp{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&clk_cfgaxi>;
				hisilicon,hi3620-clkgate = <0x30 28>;
			};

			/*dmac clk*/
			clk_dmac: dmac{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&clk_acp>;
				hisilicon,hi3620-clkgate = <0x50 10>;
				clock-output-names = "clk_dmac";
			};

			/*mmc clk*/
			clk_mmc1_mux: mmc1_mux{
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&peripll &usbpll>;
				hisilicon,hi3620-clkmux = <0x108 0x200>;
			};

			clk_mmc2_mux: mmc2_mux{
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&peripll &usbpll>;
				hisilicon,hi3620-clkmux = <0x140 0x010>;
			};

			clk_mmc3_mux: mmc3_mux{
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&peripll &usbpll>;
				hisilicon,hi3620-clkmux = <0x140 0x200>;
			};

			clk_sd_mux: sd_mux{
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&peripll &usbpll>;
				hisilicon,hi3620-clkmux = <0x108 0x010>;
			};


			/*-----------divider table clk---------------------*/
			clk_div_mmc1: div_mmc1{
				compatible = "hisilicon,divclock";
				#clock-cells = <0>;
				clocks = <&clk_mmc1_mux>;
				hisilicon,clkdiv-table = <&divtable 0x0f 16 &divtable 0x0e 15 &divtable 0x0d 14
							&divtable 0x0c 13 &divtable 0x0b 12 &divtable 0x0a 11
							&divtable 0x09 10 &divtable 0x08 9 &divtable 0x07 8
							&divtable 0x06 7 &divtable 0x05 6 &divtable 0x04 5
							&divtable 0x03 4 &divtable 0x02 3 &divtable 0x01 2
							&divtable 0x00 1>;
				/*divider register offset, shift, width*/
				hisilicon,hi3620-clkdiv = <0x108 5 4>;
			};

			clk_div_mmc2: div_mmc2{
				compatible = "hisilicon,divclock";
				#clock-cells = <0>;
				clocks = <&clk_mmc2_mux>;
				hisilicon,clkdiv-table = <&divtable 0x0f 16 &divtable 0x0e 15 &divtable 0x0d 14
							&divtable 0x0c 13 &divtable 0x0b 12 &divtable 0x0a 11
							&divtable 0x09 10 &divtable 0x08 9 &divtable 0x07 8
							&divtable 0x06 7 &divtable 0x05 6 &divtable 0x04 5
							&divtable 0x03 4 &divtable 0x02 3 &divtable 0x01 2
							&divtable 0x00 1>;
				/*divider register offset, shift, width*/
				hisilicon,hi3620-clkdiv = <0x140 0 4>;
			};

			clk_div_mmc3: div_mmc3{
				compatible = "hisilicon,divclock";
				#clock-cells = <0>;
				clocks = <&clk_mmc3_mux>;
				hisilicon,clkdiv-table = <&divtable 0x0f 16 &divtable 0x0e 15 &divtable 0x0d 14
							&divtable 0x0c 13 &divtable 0x0b 12 &divtable 0x0a 11
							&divtable 0x09 10 &divtable 0x08 9 &divtable 0x07 8
							&divtable 0x06 7 &divtable 0x05 6 &divtable 0x04 5
							&divtable 0x03 4 &divtable 0x02 3 &divtable 0x01 2
							&divtable 0x00 1>;
				/*divider register offset, shift, width*/
				hisilicon,hi3620-clkdiv = <0x140 5 4>;
			};

			clk_div_sd: div_sd{
				compatible = "hisilicon,divclock";
				#clock-cells = <0>;
				clocks = <&clk_sd_mux>;
				hisilicon,clkdiv-table = <&divtable 0x0f 16 &divtable 0x0e 15 &divtable 0x0d 14&divtable 0x0c 13
							&divtable 0x0b 12 &divtable 0x0a 11 &divtable 0x09 10 &divtable 0x08 9
							&divtable 0x07 8 &divtable 0x06 7 &divtable 0x05 6 &divtable 0x04 5
							&divtable 0x03 4 &divtable 0x02 3 &divtable 0x01 2 &divtable 0x00 1>;
				/*divider register offset, shift, width*/
				hisilicon,hi3620-clkdiv = <0x108 0 4>;
			};

			/*---------------gate--------------------*/
			clk_mmc1_parent: mmc1_parent{
				compatible = "hisilicon,muxclock";
				#clock-cells = <0>;
				clocks = <&osc26m &clk_div_mmc1>;
				hisilicon,hi3620-clkmux = <0x108 0x400>;
			};

			clk_mmc1: mmc1 {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&testsdclk>;
				/* clocks = <&clk_mmc1_parent>; */
				hisilicon,hi3620-clkgate = <0x50 21>;
			};

			clk_mmc2: mmc2 {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&clk_div_mmc2>;
				hisilicon,hi3620-clkgate = <0x50 22>;
			};

			clk_mmc3: mmc3 {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&clk_div_mmc3>;
				hisilicon,hi3620-clkgate = <0x50 23>;
			};

			clk_sd: sd {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				/* clocks = <&clk_div_sd>; */
				clocks = <&testsdclk>;
				hisilicon,hi3620-clkgate = <0x50 20>;
			};

			clk_ddrc_per: ddrc_per {
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&clk_cfgaxi>;
				hisilicon,hi3620-clkgate = <0x50 9>;
			};

			clk_mcu: mcu{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&clk_cfgaxi>;
				hisilicon,hi3620-clkgate = <0x50 24>;
				clock-output-names = "clk_mcu";
			};

			/*rtc clk*/
			clk_rtc: rtc{
				compatible = "hisilicon,periclock";
				#clock-cells = <0>;
				clocks = <&pclk>;
				hisilicon,hi3620-clkgate = <0x20 5>;
				clock-output-names = "clk_rtc";
			};

			/*--------------------divider clock -------------------*/
			divtable: clkdiv {
				#hisilicon,clkdiv-table-cells = <2>;
			};

			clk_div_shaxi: div_shaxi{
				compatible = "hisilicon,divclock";
				#clock-cells = <0>;
				clocks = <&peripll>;
				hisilicon,clkdiv-table = <&divtable 0x04 5>;
				/*divider register offset, shift, width*/
				hisilicon,hi3620-clkdiv = <0x100 0 5>;
			};

			clk_div_cfgaxi: div_cfgaxi{
				compatible = "hisilicon,divclock";
				#clock-cells = <0>;
				clocks = <&clk_div_shaxi>;
				hisilicon,clkdiv-table = <&divtable 0x01 2>;
				hisilicon,hi3620-clkdiv = <0x100 5 2>;
			};
		};

		rtc0: rtc@fc804000 {
			compatible = "arm,rtc-pl031", "arm,primecell";
			reg = <0xfc804000 0x1000>;
			interrupts = <0 9 0x4>;
			clocks = <&clk_rtc>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		l2: l2-cache {
			compatible = "arm,pl310-cache";
			reg = <0xfc100000 0x100000>;
			interrupts = <0 15 4>;
			cache-unified;
			cache-level = <2>;
			hisilicon,l2cache-aux = <0x30070000 0xf00f0000>;
		};

		intc: interrupt-controller@fc001000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			/* gic dist base, gic cpu base */
			reg = <0xfc001000 0x1000>, <0xfc000100 0x100>;
		};

		timer0: timer@fc800000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0xfc800000 0x1000>;
			/* timer00 & timer01 */
			interrupts = <0 0 4>, <0 1 4>;
			clocks = <&timclk0 &timclk1 &pclk>;
			clock-names = "timer0", "timer1", "apb_pclk";
			status = "disabled";
		};

		timer1: timer@fc801000 {
			/*
			 * Only used in NORMAL state, not available ins
			 * SLOW or DOZE state.
			 * The rate is fixed in 24MHz.
			 */
			compatible = "arm,sp804", "arm,primecell";
			reg = <0xfc801000 0x1000>;
			/* timer10 & timer11 */
			interrupts = <0 2 4>, <0 3 4>;
			clocks = <&timclk0 &timclk1 &pclk>;
			clock-names = "timer0", "timer1", "apb_pclk";
			status = "disabled";
		};

		timer2: timer@fca01000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0xfca01000 0x1000>;
			/* timer20 & timer21 */
			interrupts = <0 4 4>, <0 5 4>;
			clocks = <&timclk0 &timclk1 &pclk>;
			clock-names = "timer0", "timer1", "apb_pclk";
			status = "disabled";
		};

		timer3: timer@fca02000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0xfca02000 0x1000>;
			/* timer30 & timer31 */
			interrupts = <0 6 4>, <0 7 4>;
			clocks = <&timclk0 &timclk1 &pclk>;
			clock-names = "timer0", "timer1", "apb_pclk";
			status = "disabled";
		};

		timer4: timer@fca03000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0xfca03000 0x1000>;
			/* timer40 & timer41 */
			interrupts = <0 96 4>, <0 97 4>;
			clocks = <&timclk0 &timclk1 &pclk>;
			clock-names = "timer0", "timer1", "apb_pclk";
			status = "disabled";
		};

		uart0: uart@fcb00000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0xfcb00000 0x1000>;
			interrupts = <0 20 4>;
			clocks = <&clk_uart0>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		uart1: uart@fcb01000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0xfcb01000 0x1000>;
			interrupts = <0 21 4>;
			clocks = <&clk_uart1>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		uart2: uart@fcb02000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0xfcb02000 0x1000>;
			interrupts = <0 22 4>;
			clocks = <&clk_uart2>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		uart3: uart@fcb03000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0xfcb03000 0x1000>;
			interrupts = <0 23 4>;
			clocks = <&clk_uart3>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		uart4: uart@fcb04000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0xfcb04000 0x1000>;
			interrupts = <0 24 4>;
			clocks = <&clk_uart4>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio0: gpio@fc806000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc806000 0x1000>;
			interrupts = <0 64 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
					&pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio1: gpio@fc807000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc807000 0x1000>;
			interrupts = <0 65 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
					&pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1
					&pmx0 6 5 1 &pmx0 7 6 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio2: gpio@fc808000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc808000 0x1000>;
			interrupts = <0 66 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
					&pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1
					&pmx0 6 3 1 &pmx0 7 3 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio3: gpio@fc809000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc809000 0x1000>;
			interrupts = <0 67 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
					&pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1
					&pmx0 6 11 1 &pmx0 7 11 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio4: gpio@fc80a000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc80a000 0x1000>;
			interrupts = <0 68 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
					&pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1
					&pmx0 6 13 1 &pmx0 7 13 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio5: gpio@fc80b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc80b000 0x1000>;
			interrupts = <0 69 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
					&pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
					&pmx0 6 16 1 &pmx0 7 16 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio6: gpio@fc80c000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc80c000 0x1000>;
			interrupts = <0 70 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
					&pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1
					&pmx0 6 18 1 &pmx0 7 19 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio7: gpio@fc80d000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc80d000 0x1000>;
			interrupts = <0 71 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
					&pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1
					&pmx0 6 25 1 &pmx0 7 26 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio8: gpio@fc80e000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc80e000 0x1000>;
			interrupts = <0 72 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
					&pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1
					&pmx0 6 33 1 &pmx0 7 34 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio9: gpio@fc80f000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc80f000 0x1000>;
			interrupts = <0 73 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
					&pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1
					&pmx0 6 41 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio10: gpio@fc810000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc810000 0x1000>;
			interrupts = <0 74 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
					&pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio11: gpio@fc811000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc811000 0x1000>;
			interrupts = <0 75 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
					&pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1
					&pmx0 6 49 1 &pmx0 7 49 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio12: gpio@fc812000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc812000 0x1000>;
			interrupts = <0 76 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
					&pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1
					&pmx0 6 51 1 &pmx0 7 52 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio13: gpio@fc813000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc813000 0x1000>;
			interrupts = <0 77 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
					&pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1
					&pmx0 6 55 1 &pmx0 7 56 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio14: gpio@fc814000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc814000 0x1000>;
			interrupts = <0 78 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
					&pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1
					&pmx0 6 60 1 &pmx0 7 61 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio15: gpio@fc815000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc815000 0x1000>;
			interrupts = <0 79 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
					&pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1
					&pmx0 6 64 1 &pmx0 7 65 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio16: gpio@fc816000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc816000 0x1000>;
			interrupts = <0 80 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
					&pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1
					&pmx0 6 72 1 &pmx0 7 73 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio17: gpio@fc817000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc817000 0x1000>;
			interrupts = <0 81 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
					&pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1
					&pmx0 6 80 1 &pmx0 7 81 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio18: gpio@fc818000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc818000 0x1000>;
			interrupts = <0 82 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
					&pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1
					&pmx0 6 86 1 &pmx0 7 87 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio19: gpio@fc819000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc819000 0x1000>;
			interrupts = <0 83 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
					&pmx0 3 88 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio20: gpio@fc81a000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc81a000 0x1000>;
			interrupts = <0 84 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
					&pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		gpio21: gpio@fc81b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0xfc81b000 0x1000>;
			interrupts = <0 85 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <	&pmx0 3 94 1 &pmx0 7 96 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disable";
		};

		pmx0: pinmux@fc803000 {
			compatible = "pinctrl-single";
			reg = <0xfc803000 0x188>;
			#address-cells = <1>;
			#size-cells = <1>;
			#gpio-range-cells = <3>;
			ranges;

			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <7>;
			/* pin base, nr pins & gpio function */
			pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
						&range 12 1 0 &range 13 29 1
						&range 43 1 0 &range 44 49 1
						&range 94 1 1 &range 96 2 1>;

			range: gpio-range {
				#pinctrl-single,gpio-range-cells = <3>;
			};
		};

		pmx1: pinmux@fc803800 {
			compatible = "pinconf-single";
			reg = <0xfc803800 0x2dc>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			pinctrl-single,register-width = <32>;
		};

		sysctrl@fc802000 {
			compatible = "hisilicon,sysctrl";
			reg = <0xfc802000 0x1000>;
			smp_reg = <0x31c>;
			reboot_reg = <0x4>;
		};

		dma0: dma@fcd02000 {
			compatible = "hisilicon,k3-dma-1.0";
			reg = <0xfcd02000 0x1000>;
			#dma-cells = <1>;
			dma-channels = <27>;
			interrupts = <0 12 4>;
			clocks = <&clk_dmac>;
			status = "disable";
		};

		i2c0: i2c@fcb08000 {
			compatible = "hisilicon,designware-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xfcb08000 0x1000>;
			interrupts = <0 28 4>;
			clocks = <&clk_i2c0>;
			dmas =	<&dma0 18          /* read channel */
				 &dma0 19>;        /* write channel */
			dma-names = "rx", "tx";
			status = "disabled";
		};

		i2c1: i2c@fcb09000 {
			compatible = "hisilicon,designware-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xfcb09000 0x1000>;
			interrupts = <0 29 4>;
			clocks = <&clk_i2c1>;
			dmas =	<&dma0 20          /* read channel */
				 &dma0 21>;        /* write channel */
			dma-names = "rx", "tx";
			status = "disabled";
		};

		i2c2: i2c@fcb0c000 {
			compatible = "hisilicon,designware-i2c";
			reg = <0xfcb0c000 0x1000>;
			interrupts = <0 62 4>;
			clocks = <&clk_i2c2>;
			status = "disabled";
		};

		i2c3: i2c@fcb0d000 {
			compatible = "hisilicon,designware-i2c";
			reg = <0xfcb0d000 0x1000>;
			interrupts = <0 63 4>;
			clocks = <&clk_i2c3>;
			status = "disabled";
		};

		mcu: mcu@fd000000 {
			compatible = "hisilicon,hi3620-mcu";
			reg = <0xfd000000 0x00010000>;
			interrupts = <0 89 4>;
			clocks = <&clk_mcu>;
			status = "disabled";
		};

		/* unremovable emmc as mmcblk0 */
		dwmmc_1: dwmmc1@fcd04000 {
			compatible = "hisilicon,hi4511-dw-mshc";
			reg = <0xfcd04000 0x1000>;
			interrupts = <0 17 4>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clk_mmc1>, <&clk_ddrc_per>;
			clock-names = "ciu", "biu";
		};

		/* sd as mmcblk1 */
		dwmmc_0: dwmmc0@fcd03000 {
			compatible = "hisilicon,hi4511-dw-mshc";
			reg = <0xfcd03000 0x1000>;
			interrupts = <0 16 4>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clk_sd>, <&clk_ddrc_per>;
			clock-names = "ciu", "biu";
		};

		dwmmc_2: dwmmc2@fcd05000 {
			compatible = "hisilicon,hi4511-dw-mshc";
			reg = <0xfcd05000 0x1000>;
			interrupts = <0 18 4>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clk_mmc2>;
		};

		dwmmc_3: dwmmc3@fcd06000 {
			compatible = "hisilicon,hi4511-dw-mshc";
			reg = <0xfcd06000 0x1000>;
			interrupts = <0 19 4>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clk_mmc3>;
		};
		kpc: kpc@fc805000 {
			compatible = "hisilicon,k3_keypad";
			reg = <0xfc805000 0x1000>;
			interrupts = <0 10 4>;
			clocks = <&clk_kpc>;
			status = "disabled";
		};
	};
};