refactor(build): renaming BL2_AT_EL3 to RESET_TO_BL2

Along with e09da7be3fe5f7a59f16abc6008a8a97c3e1c247 that introduces a
breaking refactoring change we have to rename the build option in the CI
scripts.
Renaming BL2_AT_EL3 to RESET_TO_BL2.

Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Change-Id: I57fe6c8e289a71d8d3cea3a6d71760d7df43112e

9 files changed, 11 insertions, 11 deletions

diff --git a/script/build_package.sh b/script/build_package.sh
index dcbd9e55..d2195283 100755
--- a/script/build_package.sh
+++ b/script/build_package.sh
@@ -438,7 +438,7 @@ update_fip_hw_config() {
 		"$(get_tf_opt RESET_TO_BL31)" | \
 		"$(get_tf_opt ARM_LINUX_KERNEL_AS_BL33)" | \
 		"$(get_tf_opt RESET_TO_SP_MIN)" | \
-		"$(get_tf_opt BL2_AT_EL3)")
+		"$(get_tf_opt RESET_TO_BL2)")
 			return 0;;
 	esac
 
diff --git a/script/tf-coverity/tf-cov-make b/script/tf-coverity/tf-cov-make
index 48c1569c..7892bafc 100755
--- a/script/tf-coverity/tf-cov-make
+++ b/script/tf-coverity/tf-cov-make
@@ -141,9 +141,9 @@ clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=1 ARM_ARCH_MINOR=4 \
 clean_build $fvp_common_flags SPD=spmd SPMD_SPM_AT_SEL2=0 SPMC_AT_EL3=1
 
 #BL2 at EL3 support
-clean_build $fvp_common_flags BL2_AT_EL3=1
+clean_build $fvp_common_flags RESET_TO_BL2=1
 clean_build $fvp_common_flags CROSS_COMPILE=arm-none-eabi- \
-    ARCH=aarch32 AARCH32_SP=sp_min BL2_AT_EL3=1
+    ARCH=aarch32 AARCH32_SP=sp_min RESET_TO_BL2=1
 
 # RAS Extension Support
 clean_build $fvp_common_flags EL3_EXCEPTION_HANDLING=1 \
@@ -308,7 +308,7 @@ make $(common_flags) \
      TARGET_PLATFORM=fpga \
      ENABLE_STACK_PROTECTOR=strong \
      ENABLE_PIE=1 \
-     BL2_AT_EL3=1 \
+     RESET_TO_BL2=1 \
      SPMD_SPM_AT_SEL2=0 \
      ${ARM_TBB_OPTIONS} \
      CREATE_KEYS=1 \
diff --git a/tf_config/corstone1000-fpga-default b/tf_config/corstone1000-fpga-default
index df7899e7..d0b8b234 100644
--- a/tf_config/corstone1000-fpga-default
+++ b/tf_config/corstone1000-fpga-default
@@ -1,5 +1,5 @@
 ARM_ROTPK_LOCATION=devel_rsa
-BL2_AT_EL3=1
+RESET_TO_BL2=1
 CROSS_COMPILE=aarch64-none-elf-
 ENABLE_PIE=1
 GENERATE_COT=1
diff --git a/tf_config/corstone1000-fvp-default b/tf_config/corstone1000-fvp-default
index df7899e7..d0b8b234 100644
--- a/tf_config/corstone1000-fvp-default
+++ b/tf_config/corstone1000-fvp-default
@@ -1,5 +1,5 @@
 ARM_ROTPK_LOCATION=devel_rsa
-BL2_AT_EL3=1
+RESET_TO_BL2=1
 CROSS_COMPILE=aarch64-none-elf-
 ENABLE_PIE=1
 GENERATE_COT=1
diff --git a/tf_config/fvp-aarch32-bl2-el3 b/tf_config/fvp-aarch32-bl2-el3
index 1cc311f2..d5a278d9 100644
--- a/tf_config/fvp-aarch32-bl2-el3
+++ b/tf_config/fvp-aarch32-bl2-el3
@@ -1,5 +1,5 @@
 AARCH32_SP=sp_min
 ARCH=aarch32
-BL2_AT_EL3=1
+RESET_TO_BL2=1
 CROSS_COMPILE=arm-none-eabi-
 PLAT=fvp
diff --git a/tf_config/fvp-aarch32-tbb-mbedtls-bl2-el3 b/tf_config/fvp-aarch32-tbb-mbedtls-bl2-el3
index 889a16e6..f30cecb4 100644
--- a/tf_config/fvp-aarch32-tbb-mbedtls-bl2-el3
+++ b/tf_config/fvp-aarch32-tbb-mbedtls-bl2-el3
@@ -1,7 +1,7 @@
 AARCH32_SP=sp_min
 ARCH=aarch32
 ARM_ROTPK_LOCATION=devel_rsa
-BL2_AT_EL3=1
+RESET_TO_BL2=1
 CROSS_COMPILE=arm-none-eabi-
 GENERATE_COT=1
 PLAT=fvp
diff --git a/tf_config/fvp-bl2-el3 b/tf_config/fvp-bl2-el3
index 011094b6..79f25397 100644
--- a/tf_config/fvp-bl2-el3
+++ b/tf_config/fvp-bl2-el3
@@ -1,3 +1,3 @@
-BL2_AT_EL3=1
+RESET_TO_BL2=1
 CROSS_COMPILE=aarch64-none-elf-
 PLAT=fvp
diff --git a/tf_config/fvp-bl2-el3-pie b/tf_config/fvp-bl2-el3-pie
index 793c8f4f..d838a3d2 100644
--- a/tf_config/fvp-bl2-el3-pie
+++ b/tf_config/fvp-bl2-el3-pie
@@ -1,4 +1,4 @@
-BL2_AT_EL3=1
+RESET_TO_BL2=1
 CROSS_COMPILE=aarch64-none-elf-
 PLAT=fvp
 ENABLE_PIE=1
diff --git a/tf_config/fvp-tbb-mbedtls-bl2-el3 b/tf_config/fvp-tbb-mbedtls-bl2-el3
index 7b461d43..fd2141b7 100644
--- a/tf_config/fvp-tbb-mbedtls-bl2-el3
+++ b/tf_config/fvp-tbb-mbedtls-bl2-el3
@@ -1,5 +1,5 @@
 ARM_ROTPK_LOCATION=devel_rsa
-BL2_AT_EL3=1
+RESET_TO_BL2=1
 CROSS_COMPILE=aarch64-none-elf-
 GENERATE_COT=1
 PLAT=fvp