Revert "smmu: testing hacks"

This reverts commit 6d465fb20773e1d1e436ed8e9d36c10b6eeb9793.

10 files changed, 28 insertions, 760 deletions

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 87c30f02c8aa..246473a244f6 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -653,8 +653,7 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += \
 	vexpress-v2p-ca5s.dtb \
 	vexpress-v2p-ca9.dtb \
 	vexpress-v2p-ca15-tc1.dtb \
-	vexpress-v2p-ca15_a7.dtb \
-	rtsm_ve-cortex_a15x4_a7x4.dtb
+	vexpress-v2p-ca15_a7.dtb
 dtb-$(CONFIG_ARCH_VIRT) += \
 	xenvm-4.2.dtb
 dtb-$(CONFIG_ARCH_VT8500) += \
diff --git a/arch/arm/boot/dts/rtsm_ve-cortex_a15x4_a7x4.dts b/arch/arm/boot/dts/rtsm_ve-cortex_a15x4_a7x4.dts
deleted file mode 100644
index 897dbd76b323..000000000000
--- a/arch/arm/boot/dts/rtsm_ve-cortex_a15x4_a7x4.dts
+++ /dev/null
@@ -1,356 +0,0 @@
-/*
- * ARM Ltd. Fast Models
- *
- * Versatile Express (VE) system model
- * ARMCortexA7x4CT
- * ARMCortexA15x4CT
- *
- * RTSM_VE_Cortex_A15x4_A7x4.lisa
- */
-
-/dts-v1/;
-
-/ {
-	model = "RTSM_VE_Cortex_A15x4_A7x4";
-	compatible = "arm,rtsm_ve,cortex_a15x4_a7x4", "arm,vexpress";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	chosen { };
-
-	aliases {
-		serial0 = &v2m_serial0;
-		serial1 = &v2m_serial1;
-		serial2 = &v2m_serial2;
-		serial3 = &v2m_serial3;
-	};
-
-	clusters {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cluster0: cluster@0 {
-			reg = <0>;
-			cores {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				core0: core@0 {
-					reg = <0>;
-				};
-
-				core1: core@1 {
-					reg = <1>;
-				};
-
-				core2: core@2 {
-					reg = <2>;
-				};
-
-				core3: core@3 {
-					reg = <3>;
-				};
-			};
-		};
-
-		cluster1: cluster@1 {
-			reg = <1>;
-			cores {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				core4: core@0 {
-					reg = <0>;
-				};
-
-				core5: core@1 {
-					reg = <1>;
-				};
-
-				core6: core@2 {
-					reg = <2>;
-				};
-
-				core7: core@3 {
-					reg = <3>;
-				};
-			};
-		};
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			reg = <0>;
-			cluster = <&cluster0>;
-			core = <&core0>;
-		};
-
-		cpu1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			reg = <1>;
-			cluster = <&cluster0>;
-			core = <&core1>;
-		};
-
-		cpu2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			reg = <2>;
-			cluster = <&cluster0>;
-			core = <&core2>;
-		};
-
-		cpu3: cpu@3 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			reg = <3>;
-			cluster = <&cluster0>;
-			core = <&core3>;
-		};
-
-		cpu4: cpu@4 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x100>;
-			cluster = <&cluster1>;
-			core = <&core4>;
-		};
-
-		cpu5: cpu@5 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x101>;
-			cluster = <&cluster1>;
-			core = <&core5>;
-		};
-
-		cpu6: cpu@6 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x102>;
-			cluster = <&cluster1>;
-			core = <&core6>;
-		};
-
-		cpu7: cpu@7 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x103>;
-			cluster = <&cluster1>;
-			core = <&core7>;
-		};
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0 0x80000000 0 0x80000000>;
-	};
-
-	gic: interrupt-controller@2c001000 {
-		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
-		#interrupt-cells = <3>;
-		#address-cells = <0>;
-		interrupt-controller;
-		reg = <0 0x2c001000 0 0x1000>,
-		      <0 0x2c002000 0 0x1000>,
-		      <0 0x2c004000 0 0x2000>,
-		      <0 0x2c006000 0 0x2000>;
-		interrupts = <1 9 0xf04>;
-	};
-
-	cci@2c090000 {
-		compatible = "arm,cci";
-		reg = <0 0x2c090000 0 0x8000>;
-	};
-
-	dcscb@60000000 {
-		compatible = "arm,dcscb";
-		reg = <0 0x60000000 0 0x1000>;
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		interrupts = <1 13 0xf08>,
-			     <1 14 0xf08>,
-			     <1 11 0xf08>,
-			     <1 10 0xf08>;
-	};
-/*
-	smmu@2c0b0000 {
-                compatible = "arm,smmu-v1";
-                reg = <0x0 0x2c0b0000 0x0 0x10000>;
-                #global-interrupts = <4>;
-                interrupts = <0 56 4>,
-                             <0 57 4>,
-			     <0 58 4>,
-			     <0 59 4>,
-                             <0 60 4>;
-                mmu-masters = <&dma0 0x0 0x8>,
-                              <&dma1 0x1 0x9>,
-                              <&dma2 0x2 0xa>,
-                              <&dma3 0x3 0xb>;
-        };
-*/
-	smmu@2c0b0000 {
-                compatible = "arm,smmu-v2";
-                reg = <0x0 0x2c0b0000 0x0 0x10000>;
-                #global-interrupts = <2>;
-                interrupts = <0 58 4>,
-                             <0 59 4>,
-                             <0 60 4>,
-                             <0 60 4>,
-                             <0 60 4>,
-                             <0 60 4>,
-                             <0 60 4>,
-                             <0 60 4>,
-                             <0 60 4>;
-                mmu-masters = <&dma0 0x0 0x8>,
-                              <&dma1 0x1 0x9>,
-                              <&dma2 0x2 0xa>,
-                              <&dma3 0x3 0xb>;
-        };
-
-	dma0: dma@2c0a0000 {
-		compatible = "arm,pl330", "arm,primecell";
-		reg = <0 0x2c0a0000 0 0x1000>;
-		interrupts = <0 64 4>,
-			     <0 65 4>,
-			     <0 66 4>,
-			     <0 67 4>,
-			     <0 68 4>,
-			     <0 69 4>,
-			     <0 70 4>,
-			     <0 71 4>;
-		#dma-cells = <1>;
-		#stream-id-cells = <2>;
-		clocks = <&oscclk6a>;
-		clock-names = "apb_pclk";
-	};
-
-	dma1: dma@2c0a1000 {
-		compatible = "arm,pl330", "arm,primecell";
-		reg = <0 0x2c0a1000 0 0x1000>;
-		interrupts = <0 96 4>,
-			     <0 97 4>,
-			     <0 98 4>,
-			     <0 99 4>,
-			     <0 100 4>,
-			     <0 101 4>,
-			     <0 102 4>,
-			     <0 103 4>;
-		#dma-cells = <1>;
-		#stream-id-cells = <2>;
-		clocks = <&oscclk6a>;
-		clock-names = "apb_pclk";
-	};
-
-	dma2: dma@2c0a2000 {
-		compatible = "arm,pl330", "arm,primecell";
-		reg = <0 0x2c0a2000 0 0x1000>;
-		interrupts = <0 128 4>,
-			     <0 129 4>,
-			     <0 130 4>,
-			     <0 131 4>,
-			     <0 132 4>,
-			     <0 133 4>,
-			     <0 134 4>,
-			     <0 135 4>;
-		#dma-cells = <1>;
-		#stream-id-cells = <2>;
-		clocks = <&oscclk6a>;
-		clock-names = "apb_pclk";
-	};
-
-	dma3: dma@2c0a3000 {
-		compatible = "arm,pl330", "arm,primecell";
-		reg = <0 0x2c0a3000 0 0x1000>;
-		interrupts = <0 160 4>,
-			     <0 161 4>,
-			     <0 162 4>,
-			     <0 163 4>,
-			     <0 164 4>,
-			     <0 165 4>,
-			     <0 166 4>,
-			     <0 167 4>;
-		#dma-cells = <1>;
-		#stream-id-cells = <2>;
-		clocks = <&oscclk6a>;
-		clock-names = "apb_pclk";
-	};
-
-	oscclk6a: oscclk6a {
-		/* Reference 24MHz clock */
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <24000000>;
-		clock-output-names = "oscclk6a";
-	};
-
-	smb {
-		compatible = "simple-bus";
-
-		#address-cells = <2>;
-		#size-cells = <1>;
-		ranges = <0 0 0 0x08000000 0x04000000>,
-			 <1 0 0 0x14000000 0x04000000>,
-			 <2 0 0 0x18000000 0x04000000>,
-			 <3 0 0 0x1c000000 0x04000000>,
-			 <4 0 0 0x0c000000 0x04000000>,
-			 <5 0 0 0x10000000 0x04000000>;
-
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0 0 63>;
-		interrupt-map = <0 0  0 &gic 0  0 4>,
-				<0 0  1 &gic 0  1 4>,
-				<0 0  2 &gic 0  2 4>,
-				<0 0  3 &gic 0  3 4>,
-				<0 0  4 &gic 0  4 4>,
-				<0 0  5 &gic 0  5 4>,
-				<0 0  6 &gic 0  6 4>,
-				<0 0  7 &gic 0  7 4>,
-				<0 0  8 &gic 0  8 4>,
-				<0 0  9 &gic 0  9 4>,
-				<0 0 10 &gic 0 10 4>,
-				<0 0 11 &gic 0 11 4>,
-				<0 0 12 &gic 0 12 4>,
-				<0 0 13 &gic 0 13 4>,
-				<0 0 14 &gic 0 14 4>,
-				<0 0 15 &gic 0 15 4>,
-				<0 0 16 &gic 0 16 4>,
-				<0 0 17 &gic 0 17 4>,
-				<0 0 18 &gic 0 18 4>,
-				<0 0 19 &gic 0 19 4>,
-				<0 0 20 &gic 0 20 4>,
-				<0 0 21 &gic 0 21 4>,
-				<0 0 22 &gic 0 22 4>,
-				<0 0 23 &gic 0 23 4>,
-				<0 0 24 &gic 0 24 4>,
-				<0 0 25 &gic 0 25 4>,
-				<0 0 26 &gic 0 26 4>,
-				<0 0 27 &gic 0 27 4>,
-				<0 0 28 &gic 0 28 4>,
-				<0 0 29 &gic 0 29 4>,
-				<0 0 30 &gic 0 30 4>,
-				<0 0 31 &gic 0 31 4>,
-				<0 0 32 &gic 0 32 4>,
-				<0 0 33 &gic 0 33 4>,
-				<0 0 34 &gic 0 34 4>,
-				<0 0 35 &gic 0 35 4>,
-				<0 0 36 &gic 0 36 4>,
-				<0 0 37 &gic 0 37 4>,
-				<0 0 38 &gic 0 38 4>,
-				<0 0 39 &gic 0 39 4>,
-				<0 0 40 &gic 0 40 4>,
-				<0 0 41 &gic 0 41 4>,
-				<0 0 42 &gic 0 42 4>;
-
-		/include/ "rtsm_ve-motherboard.dtsi"
-	};
-};
diff --git a/arch/arm/boot/dts/rtsm_ve-motherboard.dtsi b/arch/arm/boot/dts/rtsm_ve-motherboard.dtsi
deleted file mode 100644
index 62a20d1eaa13..000000000000
--- a/arch/arm/boot/dts/rtsm_ve-motherboard.dtsi
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * ARM Ltd. Fast Models
- *
- * Versatile Express (VE) system model
- * Motherboard component
- *
- * VEMotherBoard.lisa
- */
-
-	motherboard {
-		arm,v2m-memory-map = "rs1";
-		compatible = "arm,vexpress,v2m-p1", "simple-bus";
-		#address-cells = <2>; /* SMB chipselect number and offset */
-		#size-cells = <1>;
-		#interrupt-cells = <1>;
-		ranges;
-
-		flash@0,00000000 {
-			compatible = "arm,vexpress-flash", "cfi-flash";
-			reg = <0 0x00000000 0x04000000>,
-			      <4 0x00000000 0x04000000>;
-			bank-width = <4>;
-		};
-
-		vram@2,00000000 {
-			compatible = "arm,vexpress-vram";
-			reg = <2 0x00000000 0x00800000>;
-		};
-
-		ethernet@2,02000000 {
-			compatible = "smsc,lan91c111";
-			reg = <2 0x02000000 0x10000>;
-			interrupts = <15>;
-		};
-
-		iofpga@3,00000000 {
-			compatible = "arm,amba-bus", "simple-bus";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 3 0 0x200000>;
-
-			v2m_sysreg: sysreg@010000 {
-				compatible = "arm,vexpress-sysreg";
-				reg = <0x010000 0x1000>;
-				gpio-controller;
-				#gpio-cells = <2>;
-			};
-
-			v2m_sysctl: sysctl@020000 {
-				compatible = "arm,sp810", "arm,primecell";
-				reg = <0x020000 0x1000>;
-				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
-				clock-names = "refclk", "timclk", "apb_pclk";
-				#clock-cells = <1>;
-				clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
-			};
-
-			aaci@040000 {
-				compatible = "arm,pl041", "arm,primecell";
-				reg = <0x040000 0x1000>;
-				interrupts = <11>;
-				clocks = <&v2m_clk24mhz>;
-				clock-names = "apb_pclk";
-			};
-
-			mmci@050000 {
-				compatible = "arm,pl180", "arm,primecell";
-				reg = <0x050000 0x1000>;
-				interrupts = <9 10>;
-				cd-gpios = <&v2m_sysreg 0 0>;
-				wp-gpios = <&v2m_sysreg 1 0>;
-				max-frequency = <12000000>;
-				vmmc-supply = <&v2m_fixed_3v3>;
-				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
-				clock-names = "mclk", "apb_pclk";
-			};
-
-			kmi@060000 {
-				compatible = "arm,pl050", "arm,primecell";
-				reg = <0x060000 0x1000>;
-				interrupts = <12>;
-				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
-				clock-names = "KMIREFCLK", "apb_pclk";
-			};
-
-			kmi@070000 {
-				compatible = "arm,pl050", "arm,primecell";
-				reg = <0x070000 0x1000>;
-				interrupts = <13>;
-				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
-				clock-names = "KMIREFCLK", "apb_pclk";
-			};
-
-			v2m_serial0: uart@090000 {
-				compatible = "arm,pl011", "arm,primecell";
-				reg = <0x090000 0x1000>;
-				interrupts = <5>;
-				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
-				clock-names = "uartclk", "apb_pclk";
-			};
-
-			v2m_serial1: uart@0a0000 {
-				compatible = "arm,pl011", "arm,primecell";
-				reg = <0x0a0000 0x1000>;
-				interrupts = <6>;
-				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
-				clock-names = "uartclk", "apb_pclk";
-			};
-
-			v2m_serial2: uart@0b0000 {
-				compatible = "arm,pl011", "arm,primecell";
-				reg = <0x0b0000 0x1000>;
-				interrupts = <7>;
-				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
-				clock-names = "uartclk", "apb_pclk";
-			};
-
-			v2m_serial3: uart@0c0000 {
-				compatible = "arm,pl011", "arm,primecell";
-				reg = <0x0c0000 0x1000>;
-				interrupts = <8>;
-				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
-				clock-names = "uartclk", "apb_pclk";
-			};
-
-			wdt@0f0000 {
-				compatible = "arm,sp805", "arm,primecell";
-				reg = <0x0f0000 0x1000>;
-				interrupts = <0>;
-				clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
-				clock-names = "wdogclk", "apb_pclk";
-			};
-
-			v2m_timer01: timer@110000 {
-				compatible = "arm,sp804", "arm,primecell";
-				reg = <0x110000 0x1000>;
-				interrupts = <2>;
-				clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
-				clock-names = "timclken1", "timclken2", "apb_pclk";
-			};
-
-			v2m_timer23: timer@120000 {
-				compatible = "arm,sp804", "arm,primecell";
-				reg = <0x120000 0x1000>;
-				interrupts = <3>;
-				clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
-				clock-names = "timclken1", "timclken2", "apb_pclk";
-			};
-
-			rtc@170000 {
-				compatible = "arm,pl031", "arm,primecell";
-				reg = <0x170000 0x1000>;
-				interrupts = <4>;
-				clocks = <&v2m_clk24mhz>;
-				clock-names = "apb_pclk";
-			};
-
-			clcd@1f0000 {
-				compatible = "arm,pl111", "arm,primecell";
-				reg = <0x1f0000 0x1000>;
-				interrupts = <14>;
-				clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
-				clock-names = "clcdclk", "apb_pclk";
-			};
-		};
-
-		v2m_fixed_3v3: fixedregulator@0 {
-			compatible = "regulator-fixed";
-			regulator-name = "3V3";
-			regulator-min-microvolt = <3300000>;
-			regulator-max-microvolt = <3300000>;
-			regulator-always-on;
-		};
-
-		v2m_clk24mhz: clk24mhz {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <24000000>;
-			clock-output-names = "v2m:clk24mhz";
-		};
-
-		v2m_refclk1mhz: refclk1mhz {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <1000000>;
-			clock-output-names = "v2m:refclk1mhz";
-		};
-
-		v2m_refclk32khz: refclk32khz {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <32768>;
-			clock-output-names = "v2m:refclk32khz";
-		};
-
-		mcc {
-			compatible = "arm,vexpress,config-bus", "simple-bus";
-			arm,vexpress,config-bridge = <&v2m_sysreg>;
-
-			v2m_oscclk1: osc@1 {
-				/* CLCD clock */
-				compatible = "arm,vexpress-osc";
-				arm,vexpress-sysreg,func = <1 1>;
-				freq-range = <23750000 63500000>;
-				#clock-cells = <0>;
-				clock-output-names = "v2m:oscclk1";
-			};
-
-			reset@0 {
-				compatible = "arm,vexpress-reset";
-				arm,vexpress-sysreg,func = <5 0>;
-			};
-
-			muxfpga@0 {
-				compatible = "arm,vexpress-muxfpga";
-				arm,vexpress-sysreg,func = <7 0>;
-			};
-
-			shutdown@0 {
-				compatible = "arm,vexpress-shutdown";
-				arm,vexpress-sysreg,func = <8 0>;
-			};
-
-			reboot@0 {
-				compatible = "arm,vexpress-reboot";
-				arm,vexpress-sysreg,func = <9 0>;
-			};
-
-			dvimode@0 {
-				compatible = "arm,vexpress-dvimode";
-				arm,vexpress-sysreg,func = <11 0>;
-			};
-		};
-	};
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 7c40167876a1..10f9389572da 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -21,7 +21,6 @@ menuconfig ARCH_VEXPRESS
 	select VEXPRESS_CONFIG
 	select VEXPRESS_SYSCFG
 	select MFD_VEXPRESS_SYSREG
-	select ZONE_DMA if ARM_LPAE
 	help
 	  This option enables support for systems using Cortex processor based
 	  ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 7fc00d40512c..7c6b976ab8d3 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -648,7 +648,7 @@ config ARCH_PHYS_ADDR_T_64BIT
 	def_bool ARM_LPAE
 
 config ARCH_DMA_ADDR_T_64BIT
-	def_bool ARM_LPAE
+	bool
 
 config ARM_THUMB
 	bool "Support Thumb user binaries" if !CPU_THUMBONLY
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
index c9dd0071ac68..20addabbd127 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
@@ -42,7 +42,23 @@
 		cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,armv8";
-			reg = <0x0 0x100>;
+			reg = <0x0 0x1>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x8000fff8>;
+			next-level-cache = <&L2_0>;
+		};
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x2>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x8000fff8>;
+			next-level-cache = <&L2_0>;
+		};
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x3>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x8000fff8>;
 			next-level-cache = <&L2_0>;
@@ -65,8 +81,8 @@
 		#address-cells = <0>;
 		interrupt-controller;
 		reg = <0x0 0x2c001000 0 0x1000>,
-		      <0x0 0x2c002000 0 0x2000>,
-		      <0x0 0x2c004000 0 0x1000>,
+		      <0x0 0x2c002000 0 0x1000>,
+		      <0x0 0x2c004000 0 0x2000>,
 		      <0x0 0x2c006000 0 0x2000>;
 		interrupts = <1 9 0xf04>;
 	};
@@ -88,101 +104,6 @@
 			     <0 63 4>;
 	};
 
-	smmu@3c0b0000 {
-                compatible = "arm,smmu-v2";
-                reg = <0x0 0x3c0e0000 0x0 0x10000>;
-                #global-interrupts = <2>;
-                interrupts = <0 128 4>,
-                             <0 129 4>,
-                             <0 130 4>,
-                             <0 131 4>,
-                             <0 132 4>,
-                             <0 133 4>,
-                             <0 134 4>,
-                             <0 135 4>,
-                             <0 136 4>;
-                mmu-masters = <&dma0 0x0 0x8>,
-                              <&dma1 0x1 0x9>,
-                              <&dma2 0x2 0xa>,
-                              <&dma3 0x3 0xb>;
-        };
-
-	dma0: dma@3c0a0000 {
-		compatible = "arm,pl330", "arm,primecell";
-		reg = <0 0x3c0a0000 0 0x10000>;
-		interrupts = <0 160 4>,
-			     <0 161 4>,
-			     <0 162 4>,
-			     <0 163 4>,
-			     <0 164 4>,
-			     <0 165 4>,
-			     <0 166 4>,
-			     <0 167 4>;
-		#dma-cells = <1>;
-		#stream-id-cells = <2>;
-		clocks = <&oscclk6a>;
-		clock-names = "apb_pclk";
-	};
-
-	dma1: dma@3c0b0000 {
-		compatible = "arm,pl330", "arm,primecell";
-		reg = <0 0x3c0b0000 0 0x10000>;
-		interrupts = <0 192 4>,
-			     <0 193 4>,
-			     <0 194 4>,
-			     <0 195 4>,
-			     <0 196 4>,
-			     <0 197 4>,
-			     <0 198 4>,
-			     <0 199 4>;
-		#dma-cells = <1>;
-		#stream-id-cells = <2>;
-		clocks = <&oscclk6a>;
-		clock-names = "apb_pclk";
-	};
-
-	dma2: dma@3c0c0000 {
-		compatible = "arm,pl330", "arm,primecell";
-		reg = <0 0x3c0c0000 0 0x10000>;
-		interrupts = <0 224 4>,
-			     <0 225 4>,
-			     <0 226 4>,
-			     <0 227 4>,
-			     <0 228 4>,
-			     <0 229 4>,
-			     <0 230 4>,
-			     <0 231 4>;
-		#dma-cells = <1>;
-		#stream-id-cells = <2>;
-		clocks = <&oscclk6a>;
-		clock-names = "apb_pclk";
-	};
-
-	dma3: dma@3c0d0000 {
-		compatible = "arm,pl330", "arm,primecell";
-		reg = <0 0x3c0d0000 0 0x10000>;
-		interrupts = <0 256 4>,
-			     <0 257 4>,
-			     <0 258 4>,
-			     <0 259 4>,
-			     <0 260 4>,
-			     <0 261 4>,
-			     <0 262 4>,
-			     <0 263 4>;
-		#dma-cells = <1>;
-		#stream-id-cells = <2>;
-		clocks = <&oscclk6a>;
-		clock-names = "apb_pclk";
-	};
-
-	oscclk6a: oscclk6a {
-		/* Reference 24MHz clock */
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <24000000>;
-		clock-output-names = "oscclk6a";
-	};
-
 	smb {
 		compatible = "simple-bus";
 
diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c
index 15290bd0a4d3..b8576fd6bd0e 100644
--- a/drivers/dma/dmatest.c
+++ b/drivers/dma/dmatest.c
@@ -15,7 +15,6 @@
 #include <linux/dmaengine.h>
 #include <linux/freezer.h>
 #include <linux/init.h>
-#include <linux/iommu.h>
 #include <linux/kthread.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
@@ -23,9 +22,6 @@
 #include <linux/slab.h>
 #include <linux/wait.h>
 
-#include <linux/platform_device.h>
-#include <asm/dma-iommu.h>
-
 static unsigned int test_buf_size = 16384;
 module_param(test_buf_size, uint, S_IRUGO | S_IWUSR);
 MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
@@ -724,8 +720,6 @@ static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
 {
 	struct dmatest_thread	*thread;
 	struct dmatest_thread	*_thread;
-	struct dma_device	*dma_dev = dtc->chan->device;
-	struct dma_iommu_mapping *mapping;
 	int			ret;
 
 	list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
@@ -740,14 +734,6 @@ static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
 	/* terminate all transfers on specified channels */
 	dmaengine_terminate_all(dtc->chan);
 
-	mapping = dma_dev->dev->archdata.mapping;
-	if (mapping) {
-		arm_iommu_detach_device(dma_dev->dev);
-		arm_iommu_release_mapping(mapping);
-		pr_info("device %s released mapping (%p)\n",
-			dev_name(dma_dev->dev), mapping);
-	}
-
 	kfree(dtc);
 }
 
@@ -798,22 +784,6 @@ static int dmatest_add_threads(struct dmatest_info *info,
 	return i;
 }
 
-static int iommu_fault_handler(struct iommu_domain *domain, struct device *dev,
-			       unsigned long iova, int flags, void *token)
-{
-	phys_addr_t paddr;
-
-	pr_info("dmatest fault handler invoked for at iova 0x%lx fault %d)\n",
-		iova, flags);
-
-	iova &= PAGE_MASK;
-	paddr = iommu_iova_to_phys(domain, iova);
-	iommu_map(domain, iova, paddr, PAGE_SIZE, IOMMU_READ | IOMMU_WRITE);
-
-	pr_info("remapped page as rw\n");
-	return 0;
-}
-
 static int dmatest_add_channel(struct dmatest_info *info,
 		struct dma_chan *chan)
 {
@@ -831,32 +801,6 @@ static int dmatest_add_channel(struct dmatest_info *info,
 	dtc->chan = chan;
 	INIT_LIST_HEAD(&dtc->threads);
 
-	if (!dma_dev->dev->archdata.mapping) {
-		int err;
-		struct dma_iommu_mapping *mapping = arm_iommu_create_mapping(&platform_bus_type, 0, 0xffffffff);
-		if (IS_ERR(mapping)) {
-			pr_info("failed to create mapping for %s, continuing without translation...\n",
-				dev_name(dma_dev->dev));
-			goto no_iommu;
-		}
-
-		iommu_set_fault_handler(mapping->domain, iommu_fault_handler, NULL);
-
-		err = arm_iommu_attach_device(dma_dev->dev, mapping);
-		if (err) {
-			pr_info("failed to attach %s to mapping (%p), continuing without translation\n",
-				dev_name(dma_dev->dev), mapping);
-			arm_iommu_release_mapping(mapping);
-			goto no_iommu;
-		}
-		pr_info("device %s attached to mapping (%p)\n",
-			dev_name(dma_dev->dev), dma_dev->dev->archdata.mapping);
-	} else  {
-		pr_info("device %s already has mapping (%p)\n",
-			dev_name(dma_dev->dev), dma_dev->dev->archdata.mapping);
-	}
-
-no_iommu:
 	if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
 		cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
 		thread_count += cnt > 0 ? cnt : 0;
@@ -960,8 +904,6 @@ static void restart_threaded_test(struct dmatest_info *info, bool run)
 	if (!info->did_init)
 		return;
 
-	pr_info("restart_threaded_test\n");
-
 	/* Stop any running test first */
 	stop_threaded_test(info);
 
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 46d1498f27e9..ecab4ea059b4 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -2804,21 +2804,19 @@ pl330_probe(struct amba_device *adev, const struct amba_id *id)
 
 	amba_set_drvdata(adev, pl330);
 
-	ret = 0;
-	for (i = 0; i < AMBA_NR_IRQS; ++i) {
+	for (i = 0; i < AMBA_NR_IRQS; i++) {
 		irq = adev->irq[i];
 		if (irq) {
-			ret |= devm_request_irq(&adev->dev, irq,
-						pl330_irq_handler, IRQF_SHARED,
-						dev_name(&adev->dev), pl330);
+			ret = devm_request_irq(&adev->dev, irq,
+					       pl330_irq_handler, 0,
+					       dev_name(&adev->dev), pl330);
+			if (ret)
+				return ret;
 		} else {
 			break;
 		}
 	}
 
-	if (ret)
-		return ret;
-
 	pcfg = &pl330->pcfg;
 
 	pcfg->periph_id = adev->periphid;
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index f5ea26a6062f..ddf8e42c9367 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -239,7 +239,6 @@ static struct amba_device *of_amba_device_create(struct device_node *node,
 	}
 
 	/* setup generic device info */
-	dev->dev.coherent_dma_mask = ~0U;
 	dev->dev.of_node = of_node_get(node);
 	dev->dev.parent = parent ? : &platform_bus;
 	dev->dev.platform_data = platform_data;
diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h
index 475e09066073..50fc66868402 100644
--- a/include/linux/amba/bus.h
+++ b/include/linux/amba/bus.h
@@ -21,7 +21,7 @@
 #include <linux/resource.h>
 #include <linux/regulator/consumer.h>
 
-#define AMBA_NR_IRQS	32
+#define AMBA_NR_IRQS	9
 #define AMBA_CID	0xb105f00d
 #define CORESIGHT_CID	0xb105900d