diff options
| author | Will Deacon <will.deacon@arm.com> | 2014-04-24 17:03:01 +0100 |
|---|---|---|
| committer | Graeme Gregory <graeme.gregory@linaro.org> | 2015-08-31 12:14:15 +0100 |
| commit | 88a12d18b2de9f7af4825e4fba10cbd1b94fa160 (patch) | |
| tree | 0befcff5ccb6319108b58f3f38b0cc89bc24de4c | |
| parent | 9e05e584c78f6c4d6f56be8e224a5ee8c1751eea (diff) | |
arm64: dts: add SMMU to dts and remove commented-out nodes
In the spirit of describing what the model actually has, modify the
.dts to describe all 8 CPUs, both memory banks and the MMU-500.
Signed-off-by: Will Deacon <will.deacon@arm.com>
| -rw-r--r-- | arch/arm64/boot/dts/arm/fvp-base.dts | 31 |
1 files changed, 23 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/arm/fvp-base.dts b/arch/arm64/boot/dts/arm/fvp-base.dts index b804571f803f..9e8af20de5a1 100644 --- a/arch/arm64/boot/dts/arm/fvp-base.dts +++ b/arch/arm64/boot/dts/arm/fvp-base.dts @@ -53,7 +53,7 @@ compatible = "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; - }; /* + }; cpu@2 { device_type = "cpu"; compatible = "arm,armv8"; @@ -65,7 +65,7 @@ compatible = "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; - }; */ + }; cpu@100 { device_type = "cpu"; compatible = "arm,armv8"; @@ -77,7 +77,7 @@ compatible = "arm,armv8"; reg = <0x0 0x101>; enable-method = "psci"; - }; /* + }; cpu@102 { device_type = "cpu"; compatible = "arm,armv8"; @@ -89,15 +89,13 @@ compatible = "arm,armv8"; reg = <0x0 0x103>; enable-method = "psci"; - };*/ + }; }; memory@80000000 { device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>; - /* + reg = <0x00000000 0x80000000 0 0x80000000>, <0x00000008 0x80000000 0 0x80000000>; - */ }; gic: interrupt-controller@2f000000 { @@ -138,7 +136,7 @@ <0 63 4>; }; - pci@40000000 { + pci: pci@40000000 { #address-cells = <0x3>; #size-cells = <0x2>; #interrupt-cells = <0x1>; @@ -155,6 +153,23 @@ <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0xab 0x4>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; msi-parent = <&its>; + #stream-id-cells = <0>; + }; + + smmu@2b500000 { + compatible = "arm,mmu-500"; + reg = <0x0 0x2b500000 0x0 0x10000>; + #global-interrupts = <1>; + interrupts = <0 71 4>, + <0 71 4>, + <0 71 4>, + <0 71 4>, + <0 71 4>, + <0 71 4>, + <0 71 4>, + <0 71 4>, + <0 71 4>; + mmu-masters = <&pci>; }; smb { |