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authorTushar Behera <tushar.behera@linaro.org>2014-04-25 14:56:28 +0530
committerTushar Behera <tushar.behera@linaro.org>2014-05-02 13:51:36 +0530
commitac66bba02ba1d5ec419f4e531d468d592c65191a (patch)
treef24f79cdf084386a2acd5b142043cabd4a870917
parent876a86703fe91e34179135a3e197f4dbab13fb92 (diff)
ARM: dts: Add usb2phy node for Exynos5420
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi32
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 56c483136ef..2fc4623502c 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -684,6 +684,11 @@
samsung,power-domain = <&gsc_pd>;
};
+ sys_system_controller: system-controller@10050000 {
+ compatible = "samsung,exynos5420-pmu", "syscon";
+ reg = <0x10050000 0x5000>;
+ };
+
pmu_system_controller: system-controller@10040000 {
compatible = "samsung,exynos5420-pmu", "syscon";
reg = <0x10040000 0x5000>;
@@ -985,6 +990,33 @@
#phy-cells = <1>;
};
+ usb@12110000 {
+ compatible = "samsung,exynos4210-ehci";
+ reg = <0x12110000 0x100>;
+ interrupts = <0 71 0>;
+
+ clocks = <&clock CLK_USBH20>;
+ clock-names = "usbhost";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ phys = <&usb2_phy 1>;
+ phy-names = "host";
+ status = "ok";
+ };
+ };
+
+ usb2_phy: phy@12130000 {
+ compatible = "samsung,exynos5250-usb2-phy";
+ reg = <0x12130000 0x100>;
+ clocks = <&clock CLK_USBH20>, <&clock CLK_FIN_PLL>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,sysreg-phandle = <&sys_system_controller>;
+ samsung,pmureg-phandle = <&pmu_system_controller>;
+ };
+
usb@12400000 {
compatible = "samsung,exynos5250-dwusb3";
clocks = <&clock CLK_USBD301>;