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authorParth Dixit <parthd@codeaurora.org>2016-02-19 17:01:15 +0530
committerGerrit - the friendly Code Review server <code-review@localhost>2016-03-29 07:05:56 -0700
commit76d3674e860a91412c1139a68f07e7213f4881b5 (patch)
treebd99bfa6b728f21c980a0c9924a274421850e317
parent6b06d2a562b4b743911776c995029cc32b12770b (diff)
platform:msm_shared: Dont enable CDR for tuning commands
Currently we enable CDR for every read command including for tuning procedure which is not correct (as CDR if enabled might correct the phase during tuning and we wont be able to detect the correct phase during tuning). So, disable CDR for read tuning commands. Change-Id: I3b5148833efe4d84886c4c6b33107017edcba63e
-rw-r--r--platform/msm_shared/sdhci.c7
-rw-r--r--platform/msm_shared/sdhci_msm.c2
2 files changed, 7 insertions, 2 deletions
diff --git a/platform/msm_shared/sdhci.c b/platform/msm_shared/sdhci.c
index f114b47b..c0f307ed 100644
--- a/platform/msm_shared/sdhci.c
+++ b/platform/msm_shared/sdhci.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -859,7 +859,10 @@ uint32_t sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
if (cmd->trans_mode == SDHCI_MMC_READ)
{
trans_mode |= SDHCI_READ_MODE;
- sdhci_msm_toggle_cdr(host, true);
+ if(cmd->cmd_index == CMD21_SEND_TUNING_BLOCK)
+ sdhci_msm_toggle_cdr(host, false);
+ else
+ sdhci_msm_toggle_cdr(host, true);
}
else
{
diff --git a/platform/msm_shared/sdhci_msm.c b/platform/msm_shared/sdhci_msm.c
index eaeb744a..ea3ddcac 100644
--- a/platform/msm_shared/sdhci_msm.c
+++ b/platform/msm_shared/sdhci_msm.c
@@ -388,10 +388,12 @@ void sdhci_msm_toggle_cdr(struct sdhci_host *host, bool enable)
if (enable)
{
core_cfg |= SDCC_DLL_CDR_EN;
+ core_cfg &= ~SDCC_DLL_CDR_EXT_EN;
}
else
{
core_cfg &= ~SDCC_DLL_CDR_EN;
+ core_cfg |= SDCC_DLL_CDR_EXT_EN;
}
REG_WRITE32(host, core_cfg, SDCC_DLL_CONFIG_REG);