From 5a0ca5280bec97e879e1232409bcd707b5f2519e Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 29 Apr 2014 08:33:52 +0100 Subject: ARM: DT: apq8064: Add sdcc support via mcci driver. This patch adds support to SD card controller using generic pl180 mmci driver. This patch also adds temporary fixed regulator to get it going till the actual regulator is mainlined. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 11 +++++++ arch/arm/boot/dts/qcom-apq8064.dtsi | 52 +++++++++++++++++++++++++++++- 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 7c2441d526bc..999139180853 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -12,5 +12,16 @@ status = "ok"; }; }; + amba { + /* eMMC */ + sdcc1: sdcc@12400000 { + status = "okay"; + }; + + /* External micro SD card */ + sdcc3: sdcc@12180000 { + status = "okay"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 92bf793622c3..b9fbad42b5b6 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1,6 +1,7 @@ /dts-v1/; - #include "skeleton.dtsi" + +#include #include #include @@ -166,5 +167,54 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + /* Temporary fixed regulator */ + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sdcc1: sdcc@12400000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12400000 0x2000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&vsdcc_fixed>; + }; + + sdcc3: sdcc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12180000 0x2000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <192000000>; + no-1-8-v; + vmmc-supply = <&vsdcc_fixed>; + }; + }; }; }; -- cgit v1.2.3 From f0df546e0a83f8ee1aab9eacd211d6fd05394a97 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 16 May 2014 20:18:53 +0100 Subject: ARM: DT: QCOM: apq8064: Add dma support for sdcc node This patch adds dma support in both sdcc1 and sdcc3 device node. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index b9fbad42b5b6..611aeec38260 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -177,6 +177,26 @@ regulator-always-on; }; + sdcc1bam:dma@12402000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12402000 0x8000>; + interrupts = <0 98 0>; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc3bam:dma@12182000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x8000>; + interrupts = <0 96 0>; + clocks = <&gcc SDC3_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + amba { compatible = "arm,amba-bus"; #address-cells = <1>; @@ -197,6 +217,8 @@ cap-sd-highspeed; cap-mmc-highspeed; vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; }; sdcc3: sdcc@12180000 { @@ -214,6 +236,8 @@ max-frequency = <192000000>; no-1-8-v; vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; + dma-names = "tx", "rx"; }; }; }; -- cgit v1.2.3 From 616127b363ed035c97b51798b63b388b94ba32f4 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 16 Jun 2014 09:23:37 +0100 Subject: ARM: DT: apq8064: Add board memory range. This patch adds memory details of IFC6410 as this is necessary to overwrite the in-correct memory start comming from ATAGs. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 999139180853..3c3b43ef12e6 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -4,6 +4,11 @@ model = "Qualcomm APQ8064/IFC6410"; compatible = "qcom,apq8064-ifc6410", "qcom,apq8064"; + memory{ + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + soc { gsbi@16600000 { status = "ok"; -- cgit v1.2.3 From 65a92a4cf5e19c097f53b26d03166bcf9ce05275 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 18 Jun 2014 16:23:40 +0100 Subject: DT: ARM: APQ8064: Add usb host support. This patch adds device tree nodes to support two usb hosts on APQ8064 SOC. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 17 +++++ arch/arm/boot/dts/qcom-apq8064.dtsi | 105 +++++++++++++++++++++++++++++ 2 files changed, 122 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 3c3b43ef12e6..c2376b261e34 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -17,6 +17,23 @@ status = "ok"; }; }; + + usb3_phy:phy@12520000 { + status = "ok"; + }; + + usb4_phy:phy@12530000 { + status = "ok"; + }; + + usb3: usb@12520000 { + status = "ok"; + }; + + usb4: usb@12530000 { + status = "ok"; + }; + amba { /* eMMC */ sdcc1: sdcc@12400000 { diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 611aeec38260..13cf1a778f85 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -4,6 +4,8 @@ #include #include #include +#include +#include / { model = "Qualcomm APQ8064"; @@ -168,6 +170,109 @@ #reset-cells = <1>; }; + apcs: syscon@2011000 { + compatible = "syscon"; + reg = <0x2011000 0x1000>; + }; + + rpm@108000 { + compatible = "qcom,rpm-apq8064"; + reg = <0x108000 0x1000>; + qcom,ipc = <&apcs 0x8 2>; + + interrupts = <0 19 0>, <0 21 0>, <0 22 0>; + interrupt-names = "ack", "err", "wakeup"; + + #address-cells = <1>; + #size-cells = <0>; + + pm8921_s3: pm8921-s3 { + compatible = "qcom,rpm-pm8921-smps"; + reg = ; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + qcom,boot-load = <49360>; + qcom,switch-mode-frequency = <3200000>; + regulator-always-on; + }; + + pm8921_l3: pm8921-l3 { + compatible = "qcom,rpm-pm8921-pldo"; + reg = ; + + regulator-min-microvolt = <3050000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + qcom,boot-load = <50000>; + }; + + pm8921_l23: pm8921-l23 { + compatible = "qcom,rpm-pm8921-pldo"; + reg = ; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + qcom,boot-load = <50000>; + regulator-always-on; + }; + + }; + + usb3_phy:phy@12520000 { + compatible = "qcom,usb-otg-ci"; + reg = <0x12520000 0x400>; + interrupts = <0 188 0>; + status = "disabled"; + dr_mode = "host"; + + clocks = <&gcc USB_HS3_XCVR_CLK>, + <&gcc USB_HS3_H_CLK>; + clock-names = "core", "iface"; + + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + + resets = <&gcc USB_HS3_RESET>; + reset-names = "link"; + }; + + usb4_phy:phy@12530000 { + compatible = "qcom,usb-otg-ci"; + reg = <0x12530000 0x400>; + interrupts = <0 215 0>; + status = "disabled"; + dr_mode = "host"; + + clocks = <&gcc USB_HS4_XCVR_CLK>, + <&gcc USB_HS4_H_CLK>; + clock-names = "core", "iface"; + + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + + resets = <&gcc USB_HS4_RESET>; + reset-names = "link"; + }; + + usb3: usb@12520000 { + compatible = "qcom,ehci-host"; + reg = <0x12520000 0x400>; + interrupts = <0 188 0>; + status = "disabled"; + usb-phy = <&usb3_phy>; + }; + + usb4: usb@12530000 { + compatible = "qcom,ehci-host"; + reg = <0x12530000 0x400>; + interrupts = <0 215 0>; + status = "disabled"; + usb-phy = <&usb4_phy>; + }; + /* Temporary fixed regulator */ vsdcc_fixed: vsdcc-regulator { compatible = "regulator-fixed"; -- cgit v1.2.3 From c1633bfb1a87786474d5c0a731bdb43e170f4d31 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 19 Jun 2014 13:16:48 +0100 Subject: ARM: DT: APQ8064: Add USB OTG support This patch adds USB OTG support on USB1 of APQ8064 SOC. Tested on IFC6410 with ethernet gadget. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 14 +++++++++ arch/arm/boot/dts/qcom-apq8064.dtsi | 46 ++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index c2376b261e34..fb126f10019d 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -18,6 +18,11 @@ }; }; + /* OTG */ + usb1_phy:phy@12500000 { + status = "ok"; + }; + usb3_phy:phy@12520000 { status = "ok"; }; @@ -26,6 +31,15 @@ status = "ok"; }; + gadget1:gadget@12500000 { + status = "ok"; + }; + + /* OTG */ + usb1: usb@12500000 { + status = "ok"; + }; + usb3: usb@12520000 { status = "ok"; }; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 13cf1a778f85..bb6e27a09ca4 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -207,6 +207,16 @@ qcom,boot-load = <50000>; }; + pm8921_l4: pm8921-l4 { + compatible = "qcom,rpm-pm8921-pldo"; + reg = ; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + qcom,boot-load = <50000>; + }; + pm8921_l23: pm8921-l23 { compatible = "qcom,rpm-pm8921-pldo"; reg = ; @@ -219,6 +229,25 @@ }; + usb1_phy:phy@12500000 { + compatible = "qcom,usb-otg-ci"; + reg = <0x12500000 0x400>; + interrupts = <0 100 0>; + status = "disabled"; + dr_mode = "host"; + + clocks = <&gcc USB_HS1_XCVR_CLK>, + <&gcc USB_HS1_H_CLK>; + clock-names = "core", "iface"; + + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; + + resets = <&gcc USB_HS1_RESET>; + reset-names = "link"; + }; + usb3_phy:phy@12520000 { compatible = "qcom,usb-otg-ci"; reg = <0x12520000 0x400>; @@ -257,6 +286,23 @@ reset-names = "link"; }; + gadget1:gadget@12500000 { + compatible = "qcom,ci-hdrc"; + reg = <0x12500000 0x400>; + status = "disabled"; + dr_mode = "peripheral"; + interrupts = <0 100 0>; + usb-phy = <&usb1_phy>; + }; + + usb1: usb@12500000 { + compatible = "qcom,ehci-host"; + reg = <0x12500000 0x400>; + interrupts = <0 100 0>; + status = "disabled"; + usb-phy = <&usb1_phy>; + }; + usb3: usb@12520000 { compatible = "qcom,ehci-host"; reg = <0x12520000 0x400>; -- cgit v1.2.3 From 96e055e29fc4a24e2e429e3070da448a69f6e012 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 23 Jun 2014 18:14:38 +0100 Subject: DT:ARM:APQ8064: Add SATA controller support. This patch adds AHCI based SATA controller support to APQ8064. Tested on IFC6410 board. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064.dtsi | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index bb6e27a09ca4..8d8c8d72af27 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -197,6 +197,17 @@ regulator-always-on; }; + pm8921_s4: pm8921-s4 { + compatible = "qcom,rpm-pm8921-smps"; + reg = ; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,boot-load = <200000>; + qcom,switch-mode-frequency = <3200000>; + regulator-always-on; + }; + pm8921_l3: pm8921-l3 { compatible = "qcom,rpm-pm8921-pldo"; reg = ; @@ -319,6 +330,32 @@ usb-phy = <&usb4_phy>; }; + sata_phy0:sata-phy@1b400000{ + compatible = "qcom,apq8064-sata-phy"; + reg = <0x1b400000 0x200>; + reg-names = "phy_mem"; + clocks = <&gcc SATA_PHY_CFG_CLK>; + clock-names = "cfg"; + #phy-cells = <0>; + }; + + sata0: sata@29000000 { + compatible = "qcom,msm-ahci"; + reg = <0x29000000 0x180>; + interrupts = <0 209 0>; + clocks = <&gcc SFAB_SATA_S_H_CLK>, <&gcc SATA_H_CLK>, + <&gcc SATA_A_CLK>, <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + + clock-names = "slave_iface", "iface", + "bus", "rxoob", + "core_pmalive"; + + phys = <&sata_phy0>; + phy-names = "sata-phy"; + target-supply = <&pm8921_s4>; + }; + /* Temporary fixed regulator */ vsdcc_fixed: vsdcc-regulator { compatible = "regulator-fixed"; -- cgit v1.2.3 From 48c1959ad665b32836b02dfc6e0f1cc0763c8736 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 9 Jul 2014 18:08:32 +0100 Subject: DT: ARM: APQ8064: add pci support This patch adds PCIE support to APQ8064, tested on IFC6410 board. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 18 ++++++++++ arch/arm/boot/dts/qcom-apq8064.dtsi | 58 ++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index fb126f10019d..13de7f79ca04 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -48,6 +48,24 @@ status = "ok"; }; + /* on board fixed 3.3v supply */ + v3p3_pcieclk: v3p3-pcieclk { + compatible = "regulator-fixed"; + regulator-name = "PCIE V3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + pci@1b500000 { + status = "ok"; + pcie-clk-supply = <&v3p3_pcieclk>; + avdd-supply = <&pm8921_s3>; + vdd-supply = <&pm8921_lvs6>; + qcom,external-phy-refclk; + reset-gpio = <&qcom_pinmux 27 GPIO_ACTIVE_LOW>; + }; + amba { /* eMMC */ sdcc1: sdcc@12400000 { diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 8d8c8d72af27..d124d762041b 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { model = "Qualcomm APQ8064"; @@ -238,8 +239,65 @@ regulator-always-on; }; + + pm8921_lvs6: pm8921-lvs6 { + compatible = "qcom,rpm-pm8921-switch"; + reg = ; + regulator-always-on; + }; + + + }; + + /* PCIE */ + qcom_pinmux: pinctrl@800000 { + compatible = "qcom,apq8064-pinctrl"; + gpio-controller; + #gpio-cells = <2>; + ngpio = <150>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x00800000 0x4000>; + }; + pci@1b500000 { + compatible = "qcom,pcie-ipq8064"; + reg = <0x1b500000 0x1000>, <0x1b502000 0x100>, <0x1b600000 0x80>; + reg-names = "base", "elbi", "parf"; + status = "disabled"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + interrupts = <0 35 0x0 + 0 36 0x0 + 0 37 0x0 + 0 38 0x0 + 0 39 0x0 + 0 238 0x0>; + interrupt-names = "irq1", "irq2", "irq3", "irq4", "iqr5", "msi"; + + resets = <&gcc PCIE_ACLK_RESET>, + <&gcc PCIE_HCLK_RESET>, + <&gcc PCIE_POR_RESET>, + <&gcc PCIE_PCI_RESET>, + <&gcc PCIE_PHY_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy"; + + clocks = <&gcc PCIE_A_CLK>, + <&gcc PCIE_H_CLK>, + <&gcc PCIE_PHY_REF_CLK>; + clock-names = "core", "iface", "phy"; + + ranges = <0x00000000 0 0 0x0ff00000 0 0x00100000 /* configuration space */ + 0x81000000 0 0 0x0fe00000 0 0x00100000 /* downstream I/O */ + 0x82000000 0 0 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ + + }; + + + usb1_phy:phy@12500000 { compatible = "qcom,usb-otg-ci"; reg = <0x12500000 0x400>; -- cgit v1.2.3