/* Copyright (c) 2014-2015,2018 The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/interconnect/qcom.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/soc/qcom,apr.h>

/ {
	model = "Qualcomm Technologies, Inc. MSM8996";

	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	memory {
		device_type = "memory";
		/* We expect the bootloader to fill in the reg */
		reg = <0 0 0 0>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		mba_region: mba@91500000 {
			reg = <0x0 0x91500000 0x0 0x200000>;
			no-map;
		};

		venus_region: venus@90400000 {
			reg = <0x0 0x90400000 0x0 0x700000>;
			no-map;
		};

		adsp_region: adsp@8ea00000 {
			reg = <0x0 0x8ea00000 0x0 0x1a00000>;
			no-map;
		};

		mpss_region: mpss@88800000 {
			reg = <0x0 0x88800000 0x0 0x6200000>;
			no-map;
		};

		smem_mem: smem-mem@86000000 {
			reg = <0x0 0x86000000 0x0 0x200000>;
			no-map;
		};

		memory@85800000 {
			reg = <0x0 0x85800000 0x0 0x800000>;
			no-map;
		};

		memory@86200000 {
			reg = <0x0 0x86200000 0x0 0x2600000>;
			no-map;
		};

		rmtfs@86700000 {
			compatible = "qcom,rmtfs-mem";

			size = <0x0 0x200000>;
			alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
			no-map;

			qcom,client-id = <1>;
			qcom,vmid = <15>;
		};

		zap_shader_region: gpu@8f200000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x90b00000 0x0 0xa00000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x0>;
			enable-method = "psci";
			clocks = <&kryocc 0>;
			operating-points-v2 = <&cluster0_opp>;
			/* cooling options */
			cooling-min-level = <0>;
			cooling-max-level = <15>;
			#cooling-cells = <2>;
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			};
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x1>;
			enable-method = "psci";
			clocks = <&kryocc 0>;
			operating-points-v2 = <&cluster0_opp>;
			/* cooling options */
			cooling-min-level = <0>;
			cooling-max-level = <15>;
			#cooling-cells = <2>;
			next-level-cache = <&L2_0>;
		};

		CPU2: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x100>;
			enable-method = "psci";
			clocks = <&kryocc 1>;
			operating-points-v2 = <&cluster1_opp>;
			/* cooling options */
			cooling-min-level = <0>;
			cooling-max-level = <15>;
			#cooling-cells = <2>;
			next-level-cache = <&L2_1>;
			L2_1: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			};
		};

		CPU3: cpu@101 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x101>;
			enable-method = "psci";
			clocks = <&kryocc 1>;
			operating-points-v2 = <&cluster1_opp>;
			/* cooling options */
			cooling-min-level = <0>;
			cooling-max-level = <15>;
			#cooling-cells = <2>;
			next-level-cache = <&L2_1>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU2>;
				};

				core1 {
					cpu = <&CPU3>;
				};
			};
		};
	};

	cluster0_opp: opp_table0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp@307200000 {
			opp-hz = /bits/ 64 <  307200000 >;
			clock-latency-ns = <200000>;
		};
		opp@422400000 {
			opp-hz = /bits/ 64 <  422400000 >;
			clock-latency-ns = <200000>;
		};
		opp@480000000 {
			opp-hz = /bits/ 64 <  480000000 >;
			clock-latency-ns = <200000>;
		};
		opp@556800000 {
			opp-hz = /bits/ 64 <  556800000 >;
			clock-latency-ns = <200000>;
		};
		opp@652800000 {
			opp-hz = /bits/ 64 <  652800000 >;
			clock-latency-ns = <200000>;
		};
		opp@729600000 {
			opp-hz = /bits/ 64 <  729600000 >;
			clock-latency-ns = <200000>;
		};
		opp@844800000 {
			opp-hz = /bits/ 64 <  844800000 >;
			clock-latency-ns = <200000>;
		};
		opp@960000000 {
			opp-hz = /bits/ 64 <  960000000 >;
			clock-latency-ns = <200000>;
		};
		opp@1036800000 {
			opp-hz = /bits/ 64 < 1036800000 >;
			clock-latency-ns = <200000>;
		};
		opp@1113600000 {
			opp-hz = /bits/ 64 < 1113600000 >;
			clock-latency-ns = <200000>;
		};
		opp@1190400000 {
			opp-hz = /bits/ 64 < 1190400000 >;
			clock-latency-ns = <200000>;
		};
		opp@1228800000 {
			opp-hz = /bits/ 64 < 1228800000 >;
			clock-latency-ns = <200000>;
		};
		opp@1324800000 {
			opp-hz = /bits/ 64 < 1324800000 >;
			clock-latency-ns = <200000>;
		};
		opp@1401600000 {
			opp-hz = /bits/ 64 < 1401600000 >;
			clock-latency-ns = <200000>;
		};
		opp@1478400000 {
			opp-hz = /bits/ 64 < 1478400000 >;
			clock-latency-ns = <200000>;
		};
		opp@1593600000 {
			opp-hz = /bits/ 64 < 1593600000 >;
			clock-latency-ns = <200000>;
		};
	};

	cluster1_opp: opp_table1 {
		compatible = "operating-points-v2";
		opp-shared;

		opp@307200000 {
			opp-hz = /bits/ 64 <  307200000 >;
			clock-latency-ns = <200000>;
		};
		opp@403200000 {
			opp-hz = /bits/ 64 <  403200000 >;
			clock-latency-ns = <200000>;
		};
		opp@480000000 {
			opp-hz = /bits/ 64 <  480000000 >;
			clock-latency-ns = <200000>;
		};
		opp@556800000 {
			opp-hz = /bits/ 64 <  556800000 >;
			clock-latency-ns = <200000>;
		};
		opp@652800000 {
			opp-hz = /bits/ 64 <  652800000 >;
			clock-latency-ns = <200000>;
		};
		opp@729600000 {
			opp-hz = /bits/ 64 <  729600000 >;
			clock-latency-ns = <200000>;
		};
		opp@806400000 {
			opp-hz = /bits/ 64 <  806400000 >;
			clock-latency-ns = <200000>;
		};
		opp@883200000 {
			opp-hz = /bits/ 64 <  883200000 >;
			clock-latency-ns = <200000>;
		};
		opp@940800000 {
			opp-hz = /bits/ 64 <  940800000 >;
			clock-latency-ns = <200000>;
		};
		opp@1036800000 {
			opp-hz = /bits/ 64 < 1036800000 >;
			clock-latency-ns = <200000>;
		};
		opp@1113600000 {
			opp-hz = /bits/ 64 < 1113600000 >;
			clock-latency-ns = <200000>;
		};
		opp@1190400000 {
			opp-hz = /bits/ 64 < 1190400000 >;
			clock-latency-ns = <200000>;
		};
		opp@1248000000 {
			opp-hz = /bits/ 64 < 1248000000 >;
			clock-latency-ns = <200000>;
		};
		opp@1324800000 {
			opp-hz = /bits/ 64 < 1324800000 >;
			clock-latency-ns = <200000>;
		};
		opp@1401600000 {
			opp-hz = /bits/ 64 < 1401600000 >;
			clock-latency-ns = <200000>;
		};
		opp@1478400000 {
			opp-hz = /bits/ 64 < 1478400000 >;
			clock-latency-ns = <200000>;
		};
		opp@1552000000 {
			opp-hz = /bits/ 64 < 1552000000 >;
			clock-latency-ns = <200000>;
		};
		opp@1632000000 {
			opp-hz = /bits/ 64 < 1632000000 >;
			clock-latency-ns = <200000>;
		};
		opp@1708800000 {
			opp-hz = /bits/ 64 < 1708800000 >;
			clock-latency-ns = <200000>;
		};
		opp@1785600000 {
			opp-hz = /bits/ 64 < 1785600000 >;
			clock-latency-ns = <200000>;
		};
		opp@1824000000 {
			opp-hz = /bits/ 64 < 1824000000 >;
			clock-latency-ns = <200000>;
		};
		opp@1920000000 {
			opp-hz = /bits/ 64 < 1920000000 >;
			clock-latency-ns = <200000>;
		};
		opp@1996800000 {
			opp-hz = /bits/ 64 < 1996800000 >;
			clock-latency-ns = <200000>;
		};
		opp@2073600000 {
			opp-hz = /bits/ 64 < 2073600000 >;
			clock-latency-ns = <200000>;
		};
		opp@2150400000 {
			opp-hz = /bits/ 64 < 2150400000 >;
			clock-latency-ns = <200000>;
		};

	};
	thermal-zones {
		cpu-thermal0 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 3>;

			trips {
				cpu_alert0: cpu_alert0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "active";
				};
				cpu_warn0: cpu_warn0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit0: cpu_crit0 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device = <&CPU0 THERMAL_NO_LIMIT 7>;
				};
				map1 {
					trip = <&cpu_warn0>;
					cooling-device = <&CPU0 8 THERMAL_NO_LIMIT>;
				};
			};
		};

		cpu-thermal1 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 5>;

			trips {
				cpu_alert1: cpu_alert1 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "active";
				};
				cpu_warn1: cpu_warn1 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit1: cpu_crit1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert1>;
					cooling-device = <&CPU0 THERMAL_NO_LIMIT 7>;
				};
				map1 {
					trip = <&cpu_warn1>;
					cooling-device = <&CPU0 8 THERMAL_NO_LIMIT>;
				};
			};
		};

		cpu-thermal2 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 8>;

			trips {
				cpu_alert2: cpu_alert2 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "active";
				};
				cpu_warn2: cpu_warn2 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit2: cpu_crit2 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
			cooling-maps {
				map0 {
					trip = <&cpu_alert2>;
					cooling-device = <&CPU2 THERMAL_NO_LIMIT 7>;
				};
				map1 {
					trip = <&cpu_warn2>;
					cooling-device = <&CPU2 8 THERMAL_NO_LIMIT>;
				};
			};
		};

		cpu-thermal3 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 10>;

			trips {
				cpu_alert3: cpu_alert3 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "active";
				};
				cpu_warn3: cpu_warn3 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit3: trip1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert3>;
					cooling-device = <&CPU2 THERMAL_NO_LIMIT 7>;
				};
				map1 {
					trip = <&cpu_warn3>;
					cooling-device = <&CPU2 8 THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
			clock-output-names = "xo_board";
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32764>;
			clock-output-names = "sleep_clk";
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	firmware {
		scm {
			compatible = "qcom,scm-msm8996";

			qcom,dload-mode = <&tcsr 0x13000>;
		};
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_regs 0 0x1000>;
		#hwlock-cells = <1>;
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		hwlocks = <&tcsr_mutex 3>;
	};

	rpm-glink {
		compatible = "qcom,glink-rpm";

		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;

		qcom,rpm-msg-ram = <&rpm_msg_ram>;

		mboxes = <&apcs_glb 0>;

		rpm_requests {
			compatible = "qcom,rpm-msm8996";
			qcom,glink-channels = "rpm_requests";

			rpmcc: qcom,rpmcc {
				compatible = "qcom,rpmcc-msm8996";
				#clock-cells = <1>;
			};

			interconnect-smd-rpm {
				compatible = "qcom,interconnect-smd-rpm";
			};

			pm8994-regulators {
				compatible = "qcom,rpm-pm8994-regulators";

				pm8994_s1: s1 {};
				pm8994_s2: s2 {};
				pm8994_s3: s3 {};
				pm8994_s4: s4 {};
				pm8994_s5: s5 {};
				pm8994_s6: s6 {};
				pm8994_s7: s7 {};
				pm8994_s8: s8 {};
				pm8994_s9: s9 {};
				pm8994_s10: s10 {};
				pm8994_s11: s11 {};
				pm8994_s12: s12 {};

				pm8994_l1: l1 {};
				pm8994_l2: l2 {};
				pm8994_l3: l3 {};
				pm8994_l4: l4 {};
				pm8994_l5: l5 {};
				pm8994_l6: l6 {};
				pm8994_l7: l7 {};
				pm8994_l8: l8 {};
				pm8994_l9: l9 {};
				pm8994_l10: l10 {};
				pm8994_l11: l11 {};
				pm8994_l12: l12 {};
				pm8994_l13: l13 {};
				pm8994_l14: l14 {};
				pm8994_l15: l15 {};
				pm8994_l16: l16 {};
				pm8994_l17: l17 {};
				pm8994_l18: l18 {};
				pm8994_l19: l19 {};
				pm8994_l20: l20 {};
				pm8994_l21: l21 {};
				pm8994_l22: l22 {};
				pm8994_l23: l23 {};
				pm8994_l24: l24 {};
				pm8994_l25: l25 {};
				pm8994_l26: l26 {};
				pm8994_l27: l27 {};
				pm8994_l28: l28 {};
				pm8994_l29: l29 {};
				pm8994_l30: l30 {};
				pm8994_l31: l31 {};
				pm8994_l32: l32 {};
			};
		};
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";

		rpm_msg_ram: memory@68000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0x68000 0x6000>;
		};

		tcsr_mutex_regs: syscon@740000 {
			compatible = "syscon";
			reg = <0x740000 0x40000>;
		};

		tcsr: syscon@7a0000 {
			compatible = "qcom,tcsr-msm8996", "syscon";
			reg = <0x7a0000 0x18000>;
		};

		intc: interrupt-controller@9bc0000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			interrupt-controller;
			#redistributor-regions = <1>;
			redistributor-stride = <0x0 0x40000>;
			reg = <0x09bc0000 0x10000>,
			      <0x09c00000 0x100000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};

		apcs_glb: mailbox@9820000 {
			compatible = "qcom,msm8996-apcs-hmss-global";
			reg = <0x9820000 0x1000>;

			#mbox-cells = <1>;
		};

		gcc: clock-controller@300000 {
			compatible = "qcom,gcc-msm8996";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0x300000 0x90000>;
		};

		kryocc: clock-controller@6400000 {
			compatible = "qcom-msm8996-apcc";
			reg = <0x6400000 0x90000>;
			#clock-cells = <1>;
		};

		blsp1_uart1: serial@7570000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x07570000 0x1000>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp1_spi0: spi@7575000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x07575000 0x600>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp1_spi0_default>;
			pinctrl-1 = <&blsp1_spi0_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp2_i2c0: i2c@75b5000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x075b5000 0x1000>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
				<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp2_i2c0_default>;
			pinctrl-1 = <&blsp2_i2c0_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		tsens0: thermal-sensor@4a8000 {
			compatible = "qcom,msm8996-tsens";
			reg = <0x4a8000 0x2000>;
			#thermal-sensor-cells = <1>;
		};

		blsp2_uart1: serial@75b0000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x75b0000 0x1000>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp2_i2c1: i2c@75b6000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x075b6000 0x1000>;
			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
				<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp2_i2c1_default>;
			pinctrl-1 = <&blsp2_i2c1_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp2_uart2: serial@75b1000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x075b1000 0x1000>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp1_i2c2: i2c@7577000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x07577000 0x1000>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp1_i2c2_default>;
			pinctrl-1 = <&blsp1_i2c2_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp2_spi5: spi@75ba000{
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x075ba000 0x600>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp2_spi5_default>;
			pinctrl-1 = <&blsp2_spi5_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		sdhc2: sdhci@74a4900 {
			 status = "disabled";
			 compatible = "qcom,sdhci-msm-v4";
			 reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
			 reg-names = "hc_mem", "core_mem";

			 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
				      <0 221 IRQ_TYPE_LEVEL_HIGH>;
			 interrupt-names = "hc_irq", "pwr_irq";

			 clock-names = "iface", "core", "xo";
			 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
			 <&gcc GCC_SDCC2_APPS_CLK>,
			 <&xo_board>;
			 bus-width = <4>;
		 };

		msmgpio: pinctrl@1010000 {
			compatible = "qcom,msm8996-pinctrl";
			reg = <0x01010000 0x300000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		timer@9840000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0x09840000 0x1000>;
			clock-frequency = <19200000>;

			frame@9850000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x09850000 0x1000>,
				      <0x09860000 0x1000>;
			};

			frame@9870000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x09870000 0x1000>;
				status = "disabled";
			};

			frame@9880000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x09880000 0x1000>;
				status = "disabled";
			};

			frame@9890000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x09890000 0x1000>;
				status = "disabled";
			};

			frame@98a0000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x098a0000 0x1000>;
				status = "disabled";
			};

			frame@98b0000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x098b0000 0x1000>;
				status = "disabled";
			};

			frame@98c0000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x098c0000 0x1000>;
				status = "disabled";
			};
		};

		spmi_bus: qcom,spmi@400f000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0x400f000 0x1000>,
			      <0x4400000 0x800000>,
			      <0x4c00000 0x800000>,
			      <0x5800000 0x200000>,
			      <0x400a000 0x002100>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};

		ufsphy: phy@627000 {
			compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
			reg = <0x627000 0xda8>;
			reg-names = "phy_mem";
			#phy-cells = <0>;

			vdda-phy-supply = <&pm8994_l28>;
			vdda-pll-supply = <&pm8994_l12>;

			vdda-phy-max-microamp = <18380>;
			vdda-pll-max-microamp = <9440>;

			vddp-ref-clk-supply = <&pm8994_l25>;
			vddp-ref-clk-max-microamp = <100>;
			vddp-ref-clk-always-on;

			clock-names = "ref_clk_src", "ref_clk";
			clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
				 <&gcc GCC_UFS_CLKREF_CLK>;
			status = "disabled";
		};

		ufshc@624000 {
			compatible = "qcom,ufshc";
			reg = <0x624000 0x2500>;
			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;

			phys = <&ufsphy>;
			phy-names = "ufsphy";

			vcc-supply = <&pm8994_l20>;
			vccq-supply = <&pm8994_l25>;
			vccq2-supply = <&pm8994_s4>;

			vcc-max-microamp = <600000>;
			vccq-max-microamp = <450000>;
			vccq2-max-microamp = <450000>;

			power-domains = <&gcc UFS_GDSC>;

			clock-names =
				"core_clk_src",
				"core_clk",
				"bus_clk",
				"bus_aggr_clk",
				"iface_clk",
				"core_clk_unipro_src",
				"core_clk_unipro",
				"core_clk_ice",
				"ref_clk",
				"tx_lane0_sync_clk",
				"rx_lane0_sync_clk";
			clocks =
				<&gcc UFS_AXI_CLK_SRC>,
				<&gcc GCC_UFS_AXI_CLK>,
				<&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
				<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
				<&gcc GCC_UFS_AHB_CLK>,
				<&gcc UFS_ICE_CORE_CLK_SRC>,
				<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
				<&gcc GCC_UFS_ICE_CORE_CLK>,
				<&rpmcc RPM_SMD_LN_BB_CLK>,
				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
			freq-table-hz =
				<100000000 200000000>,
				<0 0>,
				<0 0>,
				<0 0>,
				<0 0>,
				<150000000 300000000>,
				<0 0>,
				<0 0>,
				<0 0>,
				<0 0>,
				<0 0>;

			lanes-per-direction = <1>;
			status = "disabled";

			ufs_variant {
				compatible = "qcom,ufs_variant";
			};
		};

		mmcc: clock-controller@8c0000 {
			compatible = "qcom,mmcc-msm8996";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0x8c0000 0x40000>;
			assigned-clocks = <&mmcc MMPLL9_PLL>,
					  <&mmcc MMPLL1_PLL>,
					  <&mmcc MMPLL3_PLL>,
					  <&mmcc MMPLL4_PLL>,
					  <&mmcc MMPLL5_PLL>;
			assigned-clock-rates = <624000000>,
					       <810000000>,
					       <980000000>,
					       <960000000>,
					       <825000000>;
		};

		qfprom@74000 {
			compatible = "qcom,qfprom";
			reg = <0x74000 0x8ff>;
			#address-cells = <1>;
			#size-cells = <1>;

			qusb2p_hstx_trim: hstx_trim@24e {
				reg = <0x24e 0x2>;
				bits = <5 4>;
			};

			qusb2s_hstx_trim: hstx_trim@24f {
				reg = <0x24f 0x1>;
				bits = <1 4>;
			};
		};

		phy@34000 {
			compatible = "qcom,msm8996-qmp-pcie-phy";
			reg = <0x34000 0x488>;
			#clock-cells = <1>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
				<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
				<&gcc GCC_PCIE_CLKREF_CLK>;
			clock-names = "aux", "cfg_ahb", "ref";

			vdda-phy-supply = <&pm8994_l28>;
			vdda-pll-supply = <&pm8994_l12>;

			resets = <&gcc GCC_PCIE_PHY_BCR>,
				<&gcc GCC_PCIE_PHY_COM_BCR>,
				<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
			reset-names = "phy", "common", "cfg";
			status = "disabled";

			pciephy_0: lane@35000 {
				reg = <0x035000 0x130>,
					<0x035200 0x200>,
					<0x035400 0x1dc>;
				#phy-cells = <0>;

				clock-output-names = "pcie_0_pipe_clk_src";
				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
				clock-names = "pipe0";
				resets = <&gcc GCC_PCIE_0_PHY_BCR>;
				reset-names = "lane0";
			};

			pciephy_1: lane@36000 {
				reg = <0x036000 0x130>,
					<0x036200 0x200>,
					<0x036400 0x1dc>;
				#phy-cells = <0>;

				clock-output-names = "pcie_1_pipe_clk_src";
				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
				clock-names = "pipe1";
				resets = <&gcc GCC_PCIE_1_PHY_BCR>;
				reset-names = "lane1";
			};

			pciephy_2: lane@37000 {
				reg = <0x037000 0x130>,
					<0x037200 0x200>,
					<0x037400 0x1dc>;
				#phy-cells = <0>;

				clock-output-names = "pcie_2_pipe_clk_src";
				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
				clock-names = "pipe2";
				resets = <&gcc GCC_PCIE_2_PHY_BCR>;
				reset-names = "lane2";
			};
		};

		phy@7410000 {
			compatible = "qcom,msm8996-qmp-usb3-phy";
			reg = <0x7410000 0x1c4>;
			#clock-cells = <1>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
				<&gcc GCC_USB3_CLKREF_CLK>;
			clock-names = "aux", "cfg_ahb", "ref";

			vdda-phy-supply = <&pm8994_l28>;
			vdda-pll-supply = <&pm8994_l12>;

			resets = <&gcc GCC_USB3_PHY_BCR>,
				<&gcc GCC_USB3PHY_PHY_BCR>;
			reset-names = "phy", "common";
			status = "disabled";

			ssusb_phy_0: lane@7410200 {
				reg = <0x7410200 0x200>,
					<0x7410400 0x130>,
					<0x7410600 0x1a8>;
				#phy-cells = <0>;

				clock-output-names = "usb3_phy_pipe_clk_src";
				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
				clock-names = "pipe0";
			};
		};

		hsusb_phy1: phy@7411000 {
			compatible = "qcom,msm8996-qusb2-phy";
			reg = <0x7411000 0x180>;
			#phy-cells = <0>;

			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
				<&gcc GCC_RX1_USB2_CLKREF_CLK>;
			clock-names = "cfg_ahb", "ref";

			vdda-pll-supply = <&pm8994_l12>;
			vdda-phy-dpdm-supply = <&pm8994_l24>;

			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
			nvmem-cells = <&qusb2p_hstx_trim>;
			status = "disabled";
		};

		hsusb_phy2: phy@7412000 {
			compatible = "qcom,msm8996-qusb2-phy";
			reg = <0x7412000 0x180>;
			#phy-cells = <0>;

			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
				<&gcc GCC_RX2_USB2_CLKREF_CLK>;
			clock-names = "cfg_ahb", "ref";

			vdda-pll-supply = <&pm8994_l12>;
			vdda-phy-dpdm-supply = <&pm8994_l24>;

			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
			nvmem-cells = <&qusb2s_hstx_trim>;
			status = "disabled";
		};

		usb2: usb@7600000 {
			compatible = "qcom,dwc3";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
				<&gcc GCC_USB20_MASTER_CLK>,
				<&gcc GCC_USB20_MOCK_UTMI_CLK>,
				<&gcc GCC_USB20_SLEEP_CLK>,
				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;

			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB20_MASTER_CLK>;
			assigned-clock-rates = <19200000>, <60000000>;

			power-domains = <&gcc USB30_GDSC>;
			status = "disabled";

			dwc3@7600000 {
				compatible = "snps,dwc3";
				reg = <0x7600000 0xcc00>;
				interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&hsusb_phy2>;
				phy-names = "usb2-phy";
			};
		};

		usb3: usb@6a00000 {
			compatible = "qcom,dwc3";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
				<&gcc GCC_USB30_MASTER_CLK>,
				<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
				<&gcc GCC_USB30_MOCK_UTMI_CLK>,
				<&gcc GCC_USB30_SLEEP_CLK>,
				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;

			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB30_MASTER_CLK>;
			assigned-clock-rates = <19200000>, <120000000>;

			power-domains = <&gcc USB30_GDSC>;
			status = "disabled";

			dwc3@6a00000 {
				compatible = "snps,dwc3";
				reg = <0x6a00000 0xcc00>;
				interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&hsusb_phy1>, <&ssusb_phy_0>;
				phy-names = "usb2-phy", "usb3-phy";
			};
		};

		agnoc@0 {
			power-domains = <&gcc AGGRE0_NOC_GDSC>;
			compatible = "simple-pm-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			pcie0: pcie@600000 {
				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
				status = "disabled";
				power-domains = <&gcc PCIE0_GDSC>;
				bus-range = <0x00 0xff>;
				num-lanes = <1>;

				reg = <0x00600000 0x2000>,
				      <0x0c000000 0xf1d>,
				      <0x0c000f20 0xa8>,
				      <0x0c100000 0x100000>;
				reg-names = "parf", "dbi", "elbi","config";

				phys = <&pciephy_0>;
				phy-names = "pciephy";

				#address-cells = <3>;
				#size-cells = <2>;
				ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
					<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;

				interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "msi";
				#interrupt-cells = <1>;
				interrupt-map-mask = <0 0 0 0x7>;
				interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
						<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
						<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
						<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

				pinctrl-names = "default", "sleep";
				pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
				pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;


				vdda-supply = <&pm8994_l28>;

				linux,pci-domain = <0>;

				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
					<&gcc GCC_PCIE_0_AUX_CLK>,
					<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
					<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
					<&gcc GCC_PCIE_0_SLV_AXI_CLK>;

				clock-names =  "pipe",
						"aux",
						"cfg",
						"bus_master",
						"bus_slave";

			};

			pcie1: pcie@608000 {
				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
				power-domains = <&gcc PCIE1_GDSC>;
				bus-range = <0x00 0xff>;
				num-lanes = <1>;

				status  = "disabled";

				reg = <0x00608000 0x2000>,
				      <0x0d000000 0xf1d>,
				      <0x0d000f20 0xa8>,
				      <0x0d100000 0x100000>;

				reg-names = "parf", "dbi", "elbi","config";

				phys = <&pciephy_1>;
				phy-names = "pciephy";

				#address-cells = <3>;
				#size-cells = <2>;
				ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
					<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;

				interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "msi";
				#interrupt-cells = <1>;
				interrupt-map-mask = <0 0 0 0x7>;
				interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
						<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
						<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
						<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

				pinctrl-names = "default", "sleep";
				pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
				pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;


				vdda-supply = <&pm8994_l28>;
				linux,pci-domain = <1>;

				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
					<&gcc GCC_PCIE_1_AUX_CLK>,
					<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
					<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
					<&gcc GCC_PCIE_1_SLV_AXI_CLK>;

				clock-names =  "pipe",
						"aux",
						"cfg",
						"bus_master",
						"bus_slave";
			};

			pcie2: pcie@610000 {
				compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
				power-domains = <&gcc PCIE2_GDSC>;
				bus-range = <0x00 0xff>;
				num-lanes = <1>;
				status = "disabled";
				reg = <0x00610000 0x2000>,
				      <0x0e000000 0xf1d>,
				      <0x0e000f20 0xa8>,
				      <0x0e100000 0x100000>;

				reg-names = "parf", "dbi", "elbi","config";

				phys = <&pciephy_2>;
				phy-names = "pciephy";

				#address-cells = <3>;
				#size-cells = <2>;
				ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
					<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;

				device_type = "pci";

				interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "msi";
				#interrupt-cells = <1>;
				interrupt-map-mask = <0 0 0 0x7>;
				interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
						<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
						<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
						<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

				pinctrl-names = "default", "sleep";
				pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
				pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;

				vdda-supply = <&pm8994_l28>;

				linux,pci-domain = <2>;
				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
					<&gcc GCC_PCIE_2_AUX_CLK>,
					<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
					<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
					<&gcc GCC_PCIE_2_SLV_AXI_CLK>;

				clock-names =  "pipe",
						"aux",
						"cfg",
						"bus_master",
						"bus_slave";
			};
		};

		slimbam:dma@9184000
		{
			compatible = "qcom,bam-v1.7.0";
			qcom,controlled-remotely;
			reg = <0x9184000 0x32000>;
			num-channels  = <31>;
			interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			qcom,ee = <1>;
			qcom,num-ees = <2>;
		};

		slim_msm: slim@91c0000 {
			compatible = "qcom,slim-ngd-v1.5.0";
			reg = <0x91c0000 0x2C000>;
			reg-names = "ctrl";
			interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
			qcom,apps-ch-pipes = <0x60000000>;
			qcom,ea-pc = <0x160>;
			dmas =	<&slimbam 3>, <&slimbam 4>,
				<&slimbam 5>, <&slimbam 6>;
			dma-names = "rx", "tx", "tx2", "rx2";
			#address-cells = <1>;
			#size-cells = <0>;
			ngd@1 {
				reg = <1>;
				#address-cells = <1>;
				#size-cells = <1>;
	
				tasha_ifd: tas-ifd {
					compatible = "slim217,1a0";
					reg  = <0 0>;
				};
	
				tasha_codec: tas {
					pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
					pinctrl-1 = <&cdc_reset_sleep>;
					pinctrl-names = "default", "sleep";
	
					compatible = "slim217,1a0";
					reg  = <1 0>;
					qcom,gpio-int2 = <&msmgpio 54 0>;
					qcom,cdc-reset-gpio = <&msmgpio 64 0>;
					ifd  = <&tasha_ifd>;
					clock-names = "mclk", "native";
					clocks = <&rpmcc RPM_SMD_DIV_CLK1>,
						 <&rpmcc RPM_SMD_BB_CLK1>;
	
					vdd-buck-supply = <&pm8994_s4>;
					qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
					qcom,cdc-vdd-buck-current = <650000>;
	
					buck-sido-supply = <&pm8994_s4>;
					qcom,cdc-buck-sido-voltage = <1800000 1800000>;
					qcom,cdc-buck-sido-current = <250000>;
	
					vdd-tx-h-supply = <&pm8994_s4>;
					qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
					qcom,cdc-vdd-tx-h-current = <25000>;
	
					vdd-rx-h-supply = <&pm8994_s4>;
					qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
					qcom,cdc-vdd-rx-h-current = <25000>;
	
					vddpx-1-supply = <&pm8994_s4>;
					qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
					qcom,cdc-vddpx-1-current = <10000>;
	
					qcom,cdc-micbias1-mv = <1800>;
					qcom,cdc-micbias2-mv = <1800>;
					qcom,cdc-micbias3-mv = <1800>;
					qcom,cdc-micbias4-mv = <1800>;
	
					qcom,cdc-mclk-clk-rate = <9600000>;
	
					qcom,cdc-dmic-sample-rate = <4800000>;
					qcom,cdc-mad-dmic-rate = <600000>;
	
					wcd9335:wcd {
						compatible = "qcom,wcd9335";
						#sound-dai-cells = <1>;
					};
				};
			};
		};

		adreno_smmu: arm,smmu@b40000 {
			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
			reg = <0xb40000 0x10000>;

			#global-interrupts = <1>;
			interrupts = <0 334 IRQ_TYPE_LEVEL_HIGH>,
				     <0 329 IRQ_TYPE_LEVEL_HIGH>,
				     <0 330 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <1>;

			clocks = <&mmcc GPU_AHB_CLK>,
				<&gcc GCC_MMSS_BIMC_GFX_CLK>;
			clock-names = "bus", "iface";

			power-domains = <&mmcc GPU_GDSC>;

			status = "okay";
		};

		gpu@b00000 {
			compatible = "qcom,adreno-530.2", "qcom,adreno";
			#stream-id-cells = <16>;

			reg = <0xb00000 0x3f000>;
			reg-names = "kgsl_3d0_reg_memory";

			interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "kgsl_3d0_irq";

			clocks = <&mmcc GPU_GX_GFX3D_CLK>,
				<&mmcc GPU_AHB_CLK>,
				<&mmcc GPU_GX_RBBMTIMER_CLK>,
				<&gcc GCC_BIMC_GFX_CLK>,
				<&gcc GCC_MMSS_BIMC_GFX_CLK>;

			clock-names = "core",
				"iface",
				"rbbmtimer",
				"mem",
				"mem_iface";

			power-domains = <&mmcc GPU_GDSC>;
			iommus = <&adreno_smmu 0>;

			qcom,gpu-quirk-two-pass-use-wfi;
			qcom,gpu-quirk-fault-detect-mask;

			/* This is a safe speed for bring up in all bin levels.
			 * This isn't the fastest the chip can go, but we can
			 * get there eventually */
			qcom,gpu-pwrlevels {
				compatible = "qcom,gpu-pwrlevels";
				qcom,gpu-pwrlevel@0 {
					qcom,gpu-freq = <510000000>;
				};
				qcom,gpu-pwrlevel@1 {
					qcom,gpu-freq = <27000000>;
				};
			};

			zap-shader {
				memory-region = <&zap_shader_region>;
			};
		};

		mdp_smmu: arm,smmu@d00000 {
			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
			reg = <0xd00000 0x10000>;

			#global-interrupts = <1>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <1>;

			power-domains = <&mmcc MDSS_GDSC>;

			clocks = <&mmcc SMMU_MDP_AHB_CLK>,
				 <&mmcc SMMU_MDP_AXI_CLK>;
			clock-names = "iface", "bus";

			status = "okay";
		};

		mdss: mdss@900000 {
			compatible = "qcom,mdss";

			reg = <0x900000 0x1000>,
			      <0x9b0000 0x1040>,
			      <0x9b8000 0x1040>;
			reg-names = "mdss_phys",
				    "vbif_phys",
				    "vbif_nrt_phys";

			power-domains = <&mmcc MDSS_GDSC>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;
			#interrupt-cells = <1>;

			clocks = <&mmcc MDSS_AHB_CLK>;
			clock-names = "iface_clk";

			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			mdp: mdp@901000 {
				compatible = "qcom,mdp5";
				reg = <0x901000 0x90000>;
				reg-names = "mdp_phys";

				interrupt-parent = <&mdss>;
				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&mmcc MDSS_AHB_CLK>,
					 <&mmcc MDSS_AXI_CLK>,
					 <&mmcc MDSS_MDP_CLK>,
					 <&mmcc SMMU_MDP_AXI_CLK>,
					 <&mmcc MDSS_VSYNC_CLK>;
				clock-names = "iface_clk",
					      "bus_clk",
					      "core_clk",
					      "iommu_clk",
					      "vsync_clk";

				iommus = <&mdp_smmu 0>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						mdp5_intf3_out: endpoint {
							remote-endpoint = <&hdmi_in>;
						};
					};
				};
			};

			hdmi: hdmi-tx@9a0000 {
				compatible = "qcom,hdmi-tx-8996";
				reg =	<0x009a0000 0x50c>,
					<0x00070000 0x6158>,
					<0x009e0000 0xfff>;
				reg-names = "core_physical",
					    "qfprom_physical",
					    "hdcp_physical";

				interrupt-parent = <&mdss>;
				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&mmcc MDSS_MDP_CLK>,
					 <&mmcc MDSS_AHB_CLK>,
					 <&mmcc MDSS_HDMI_CLK>,
					 <&mmcc MDSS_HDMI_AHB_CLK>,
					 <&mmcc MDSS_EXTPCLK_CLK>;
				clock-names =
					"mdp_core_clk",
					"iface_clk",
					"core_clk",
					"alt_iface_clk",
					"extp_clk";

				phys = <&hdmi_phy>;
				phy-names = "hdmi_phy";
				#sound-dai-cells = <1>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						hdmi_in: endpoint {
							remote-endpoint = <&mdp5_intf3_out>;
						};
					};
				};
			};

			hdmi_phy: hdmi-phy@9a0600 {
				compatible = "qcom,hdmi-phy-8996";
				reg = <0x9a0600 0x1c4>,
				      <0x9a0a00 0x124>,
				      <0x9a0c00 0x124>,
				      <0x9a0e00 0x124>,
				      <0x9a1000 0x124>,
				      <0x9a1200 0x0c8>;
				reg-names = "hdmi_pll",
					    "hdmi_tx_l0",
					    "hdmi_tx_l1",
					    "hdmi_tx_l2",
					    "hdmi_tx_l3",
					    "hdmi_phy";

				clocks = <&mmcc MDSS_AHB_CLK>,
					 <&gcc GCC_HDMI_CLKREF_CLK>;
				clock-names = "iface_clk",
					      "ref_clk";
			};
		};

	        lpass_q6_smmu: arm,smmu-lpass_q6@1600000 {
			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
	                reg = <0x1600000 0x20000>;
	                #iommu-cells = <1>;
                        power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;

			#global-interrupts = <1>;
		        interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
				 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
			clock-names = "iface", "bus";
                        status = "okay";
		};

		remoteproc@2080000 {
			compatible = "qcom,msm8996-mss-pil";

			reg = <0x2080000 0x100>,
			      <0x2180000 0x040>;
			reg-names = "qdsp6", "rmb";

			interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready",
					  "handover", "stop-ack";

			clocks = <&xo_board>,
				 <&gcc GCC_MSS_CFG_AHB_CLK>,
				 <&rpmcc RPM_SMD_PCNOC_CLK>,
				 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
				 <&gcc GCC_MSS_GPLL0_DIV_CLK>,
				 <&gcc GCC_MSS_SNOC_AXI_CLK>,
				 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
				 <&rpmcc RPM_SMD_QDSS_CLK>;

			clock-names = "xo", "iface", "pnoc", "bus",
				      "mem", "gpll0_mss_clk", "snoc_axi_clk",
				      "mnoc_axi_clk", "qdss";

			mx-supply = <&pm8994_s2>;
			cx-supply = <&pm8994_s1>;
			pll-supply = <&pm8994_l12>;

			resets = <&gcc GCC_MSS_RESTART>;
			reset-names = "mss_restart";

			qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;

			qcom,smem-states = <&modem_smp2p_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			mba {
				memory-region = <&mba_region>;
			};

			mpss {
				memory-region = <&mpss_region>;
			};

			smd-edge {
				interrupts = <0 449 IRQ_TYPE_EDGE_RISING>;

				label = "modem";
				mboxes = <&apcs_glb 12>;
				qcom,smd-edge = <0>;
				qcom,remote-pid = <1>;
			};
		};

		bimc: bimc@400000 {
			compatible = "qcom,msm8996-bimc";
			#interconnect-cells = <1>;
			reg = <0x400000 0x62000>;
			type = <2>;
			base-offset = <0x8000>;
			qos-offset = <0x4000>;
			clock-names = "bus_clk", "bus_a_clk";
			clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
				 <&rpmcc RPM_SMD_BIMC_A_CLK>;
			status = "okay";
		};

		cnoc: cnoc@500000 {
			compatible = "qcom,msm8996-cnoc";
			#interconnect-cells = <1>;
			reg = <0x500000 0x80>;
			type = <1>;
			clock-names = "bus_clk", "bus_a_clk";
			clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
				 <&rpmcc RPM_SMD_CNOC_A_CLK>;
			status = "okay";
		};

		snoc: snoc@520000 {
			compatible = "qcom,msm8996-snoc";
			#interconnect-cells = <1>;
			reg = <0x520000 0xa100>;
			type = <1>;
			base-offset = <0x4000>;
			qos-offset = <0x1000>;
			clock-names = "bus_clk", "bus_a_clk";
			clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
				 <&rpmcc RPM_SMD_SNOC_A_CLK>;
			status = "okay";
		};

		a0noc: a0noc@540000 {
			compatible = "qcom,msm8996-a0noc";
			#interconnect-cells = <1>;
			reg = <0x540000 0x5100>;
			type = <1>;
			qcom,base-offset = <0x3000>;
			qos-offset = <0x1000>;
			clock-names = "bus_clk", "bus_a_clk";
			clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
				 <&gcc GCC_AGGRE0_SNOC_AXI_CLK>;
			power-domains = <&gcc AGGRE0_NOC_GDSC>;
			status = "okay";
		};

		a1noc: a1noc@560000 {
			compatible = "qcom,msm8996-a1noc";
			#interconnect-cells = <1>;
			reg = <0x560000 0x3100>;
			type = <1>;
			base-offset = <0x2000>;
			qos-offset = <0x1000>;
			clock-names = "bus_clk", "bus_a_clk";
			clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>,
				 <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>;
			status = "okay";
		};

		a2noc: a2noc@580000 {
			compatible = "qcom,msm8996-a2noc";
			#interconnect-cells = <1>;
			reg = <0x580000 0x8100>;
			base-offset = <0x3000>;
			qos-offset = <0x1000>;
			type = <1>;
			clock-names = "bus_clk", "bus_a_clk";
			clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
				 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>;
			status = "okay";
		};

		mmnoc: mmnoc@5a0000 {
			compatible = "qcom,msm8996-mmnoc";
			#interconnect-cells = <1>;
			reg = <0x5a0000 0xb080>;
			type = <1>;
			base-offset = <0x4000>;
			qos-offset = <0x1000>;
			clock-names = "bus_clk", "bus_a_clk";
			clocks = <&rpmcc RPM_SMD_MMAXI_CLK>,
				 <&rpmcc RPM_SMD_MMAXI_A_CLK>;
			power-domains = <&mmcc MMAGIC_BIMC_GDSC>;
			status = "okay";
		};

		pnoc: pnoc@5c0000 {
			compatible = "qcom,msm8996-pnoc";
			#interconnect-cells = <1>;
			reg = <0x5c0000 0x2480>;
			type = <1>;
			clock-names = "bus_clk", "bus_a_clk";
			clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
				 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
			status = "okay";
		};
	};

	sound: sound {
	};

	adsp-pil {
		compatible = "qcom,msm8996-adsp-pil";

		interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
				      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
				      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
				      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
				      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "wdog", "fatal", "ready",
				  "handover", "stop-ack";

		clocks = <&xo_board>;
		clock-names = "xo";

		memory-region = <&adsp_region>;

		qcom,smem-states = <&adsp_smp2p_out 0>;
		qcom,smem-state-names = "stop";

		smd-edge {
			interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;

			label = "lpass";
			mboxes = <&apcs_glb 8>;
			qcom,smd-edge = <1>;
			qcom,remote-pid = <2>;
			#address-cells = <1>;
			#size-cells = <0>;

			apr {
	                        power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
				compatible = "qcom,apr-v2";
				qcom,smd-channels = "apr_audio_svc";
				reg = <APR_DOMAIN_ADSP>;
				#address-cells = <1>;
				#size-cells = <0>;

				q6core {
					reg = <APR_SVC_ADSP_CORE>;
					compatible = "qcom,q6core";
				};

				q6afe: q6afe {
					compatible = "qcom,q6afe";
					reg = <APR_SVC_AFE>;
					q6afedai: dais {
						#address-cells = <1>;
						#size-cells = <0>;
						#sound-dai-cells = <1>;
						hdmi@1 {
							reg = <1>;
						};
					};
				};

				q6asm: q6asm {
					compatible = "qcom,q6asm";
					reg = <APR_SVC_ASM>;
					q6asmdai: dais {
						#sound-dai-cells = <1>;
						iommus = <&lpass_q6_smmu 1>;
					};
				};

				q6adm: q6adm {
					compatible = "qcom,q6adm";
					reg = <APR_SVC_ADM>;
					q6routing: routing {
						#sound-dai-cells = <0>;
					};
				};

			};
		};
	};

	adsp-smp2p {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;

		interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;

		mboxes = <&apcs_glb 10>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	modem-smp2p {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;

		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;

		qcom,ipc = <&apcs_glb 14>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-slpi {
		compatible = "qcom,smp2p";
		qcom,smem = <481>, <430>;

		interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;

		mboxes = <&apcs_glb 26>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <3>;

		slpi_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		slpi_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};
	};

};
#include "msm8996-pins.dtsi"
#include "pm8994.dtsi"
#include "pmi8994.dtsi"