From 8958575a5d8bccdf81f1992a19b026db5a80eb3a Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Wed, 16 Nov 2016 17:20:24 +0530 Subject: HACK: don't break GIC --- drivers/irqchip/irq-gic-v3.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index e5d101418390..8c32e679eca0 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -139,6 +139,8 @@ static void gic_enable_redist(bool enable) u32 count = 1000000; /* 1s! */ u32 val; + return; + rbase = gic_data_rdist_rd_base(); val = readl_relaxed(rbase + GICR_WAKER); @@ -674,8 +676,8 @@ static void gic_cpu_init(void) gic_cpu_config(rbase, gic_redist_wait_for_rwp); /* Give LPIs a spin */ - if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) - its_cpu_init(); + //if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) + // its_cpu_init(); /* initialise system registers */ gic_cpu_sys_reg_init(); @@ -1116,8 +1118,8 @@ static int __init gic_init_bases(void __iomem *dist_base, gic_update_vlpi_properties(); - if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) - its_init(handle, &gic_data.rdists, gic_data.domain); + //if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) + // its_init(handle, &gic_data.rdists, gic_data.domain); gic_smp_init(); gic_dist_init(); -- cgit v1.2.3 From 8536d030e0a4213e6c73190196d18e1b40872320 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Mon, 18 Aug 2014 06:06:46 +0100 Subject: mmc: mmci: Support any block sizes for ux500v2 and qcom variant For the ux500v2 variant of the PL18x block, any block sizes are supported. This will make it possible to decrease data overhead for SDIO transfers. This patch is based on Ulf Hansson patch http://www.spinics.net/lists/linux-mmc/msg12160.html Signed-off-by: Srinivas Kandagatla enabled this support on qcom variant. Signed-off-by: Ulf Hansson Signed-off-by: Linus Walleij --- drivers/mmc/host/mmci.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 70b0df8b9c78..6bf6dd51b38d 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -86,6 +86,7 @@ static unsigned int fmax = 515633; * @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS * register. * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register + * @any_blksize: true if block any sizes are supported */ struct variant_data { unsigned int clkreg; @@ -118,6 +119,7 @@ struct variant_data { bool mmcimask1; u32 start_err; u32 opendrain; + bool any_blksize; }; static struct variant_data variant_arm = { @@ -242,6 +244,7 @@ static struct variant_data variant_ux500v2 = { .mmcimask1 = true, .start_err = MCI_STARTBITERR, .opendrain = MCI_OD, + .any_blksize = true, }; static struct variant_data variant_stm32 = { @@ -280,6 +283,7 @@ static struct variant_data variant_qcom = { .mmcimask1 = true, .start_err = MCI_STARTBITERR, .opendrain = MCI_ROD, + .any_blksize = true, }; /* Busy detection for the ST Micro variant */ @@ -303,10 +307,11 @@ static int mmci_card_busy(struct mmc_host *mmc) static int mmci_validate_data(struct mmci_host *host, struct mmc_data *data) { + struct variant_data *variant = host->variant; + if (!data) return 0; - - if (!is_power_of_2(data->blksz)) { + if (!is_power_of_2(data->blksz) && !variant->any_blksize) { dev_err(mmc_dev(host->mmc), "unsupported block size (%d bytes)\n", data->blksz); return -EINVAL; @@ -863,7 +868,6 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) writel(host->size, base + MMCIDATALENGTH); blksz_bits = ffs(data->blksz) - 1; - BUG_ON(1 << blksz_bits != data->blksz); if (variant->blksz_datactrl16) datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); -- cgit v1.2.3 From 0ad3ccc658516a2d7b2895dce75e6237b6b6c016 Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Fri, 18 Sep 2015 11:44:09 +0300 Subject: Input: pm8941: Add RESIN_N input handling RESIN_N PMIC input is commonly used as "Volume Down" button on Quallcom platforms. Add support for it. TODO: Do it better. Signed-off-by: Ivan T. Ivanov --- .../bindings/input/qcom,pm8941-pwrkey.txt | 11 ++++ drivers/input/misc/pm8941-pwrkey.c | 64 ++++++++++++++++++++++ 2 files changed, 75 insertions(+) diff --git a/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.txt b/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.txt index 07bf55f6e0b9..f3ae70b50b1e 100644 --- a/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.txt +++ b/Documentation/devicetree/bindings/input/qcom,pm8941-pwrkey.txt @@ -32,6 +32,17 @@ PROPERTIES Definition: presence of this property indicates that the KPDPWR_N pin should be configured for pull up. +- resin-pull-up: + Usage: optional + Value type: + Definition: presence of this property indicates that the RESIN_N pin + should be configured for pull up. + +- linux,code: + Usage: optional + Value type: + Definition: Keycode to emit when RESIN_N input change its state. + EXAMPLE pwrkey@800 { diff --git a/drivers/input/misc/pm8941-pwrkey.c b/drivers/input/misc/pm8941-pwrkey.c index 18ad956454f1..fa21c4d67678 100644 --- a/drivers/input/misc/pm8941-pwrkey.c +++ b/drivers/input/misc/pm8941-pwrkey.c @@ -28,6 +28,7 @@ #define PON_RT_STS 0x10 #define PON_KPDPWR_N_SET BIT(0) +#define PON_RESIN_N_SET BIT(1) #define PON_PS_HOLD_RST_CTL 0x5a #define PON_PS_HOLD_RST_CTL2 0x5b @@ -37,6 +38,7 @@ #define PON_PS_HOLD_TYPE_HARD_RESET 7 #define PON_PULL_CTL 0x70 +#define PON_RESIN_PULL_UP BIT(0) #define PON_KPDPWR_PULL_UP BIT(1) #define PON_DBC_CTL 0x71 @@ -52,6 +54,7 @@ struct pm8941_pwrkey { unsigned int revision; struct notifier_block reboot_notifier; + unsigned int resin_code; }; static int pm8941_reboot_notify(struct notifier_block *nb, @@ -130,6 +133,25 @@ static irqreturn_t pm8941_pwrkey_irq(int irq, void *_data) return IRQ_HANDLED; } +static irqreturn_t pm8941_resin_irq(int irq, void *_data) +{ + struct pm8941_pwrkey *pwrkey = _data; + unsigned int sts; + int error; + + error = regmap_read(pwrkey->regmap, + pwrkey->baseaddr + PON_RT_STS, &sts); + if (error) + return IRQ_HANDLED; + + input_report_key(pwrkey->input, pwrkey->resin_code, + !!(sts & PON_RESIN_N_SET)); + + input_sync(pwrkey->input); + + return IRQ_HANDLED; +} + static int __maybe_unused pm8941_pwrkey_suspend(struct device *dev) { struct pm8941_pwrkey *pwrkey = dev_get_drvdata(dev); @@ -153,6 +175,46 @@ static int __maybe_unused pm8941_pwrkey_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(pm8941_pwr_key_pm_ops, pm8941_pwrkey_suspend, pm8941_pwrkey_resume); +static void pm8941_resin_setup(struct platform_device *pdev, + struct pm8941_pwrkey *pwrkey) +{ + int irq, error; + bool pull_up; + u32 code; + + irq = platform_get_irq(pdev, 1); + if (irq < 0) + return; + + pull_up = of_property_read_bool(pdev->dev.of_node, "resin-pull-up"); + + error = regmap_update_bits(pwrkey->regmap, + pwrkey->baseaddr + PON_PULL_CTL, + PON_RESIN_PULL_UP, + pull_up ? PON_RESIN_PULL_UP : 0); + if (error) { + dev_err(&pdev->dev, "failed to set pull: %d\n", error); + return; + } + + error = of_property_read_u32(pdev->dev.of_node, "linux,code", &code); + if (error) { + dev_err(&pdev->dev, "resin no linux,code %d\n", error); + return; + } + + pwrkey->resin_code = code; + + input_set_capability(pwrkey->input, EV_KEY, code); + + error = devm_request_threaded_irq(&pdev->dev, irq, + NULL, pm8941_resin_irq, + IRQF_ONESHOT, + "pm8941_resin", pwrkey); + if (error) + dev_err(&pdev->dev, "failed requesting IRQ: %d\n", error); +} + static int pm8941_pwrkey_probe(struct platform_device *pdev) { struct pm8941_pwrkey *pwrkey; @@ -241,6 +303,8 @@ static int pm8941_pwrkey_probe(struct platform_device *pdev) return error; } + pm8941_resin_setup(pdev, pwrkey); + error = input_register_device(pwrkey->input); if (error) { dev_err(&pdev->dev, "failed to register input device: %d\n", -- cgit v1.2.3 From 20d40e94d03e0c51e3a9a1994a11f6aaba49a278 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 4 Nov 2016 12:36:08 +0000 Subject: PCI: qcom: add runtime pm support to pcie_port This patch is required when the pcie controller sits on a bus with its own power domain and clocks which are controlled via a bus driver like simple pm bus. As these bus driver have runtime pm enabled, it makes sense to update the usage counter so that the runtime pm does not suspend the clks or power domain associated with the bus driver. Signed-off-by: Srinivas Kandagatla --- drivers/pci/dwc/pcie-qcom.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c index 5897af7d3355..58988b482939 100644 --- a/drivers/pci/dwc/pcie-qcom.c +++ b/drivers/pci/dwc/pcie-qcom.c @@ -1088,6 +1088,9 @@ static int qcom_pcie_host_init(struct pcie_port *pp) struct qcom_pcie *pcie = to_qcom_pcie(pci); int ret; + + pm_runtime_get_sync(pci->dev); + qcom_ep_reset_assert(pcie); ret = pcie->ops->init(pcie); @@ -1124,6 +1127,7 @@ err_disable_phy: phy_power_off(pcie->phy); err_deinit: pcie->ops->deinit(pcie); + pm_runtime_put_sync(pci->dev); return ret; } @@ -1212,6 +1216,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) if (!pci) return -ENOMEM; + pm_runtime_enable(dev); pci->dev = dev; pci->ops = &dw_pcie_ops; pp = &pci->pp; @@ -1265,6 +1270,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "cannot initialize host\n"); + pm_runtime_disable(&pdev->dev); return ret; } -- cgit v1.2.3 From 3a62b65795a807f62bc4559001ebc8f8500f98c3 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 12 Oct 2017 12:28:47 +0530 Subject: clk: qcom: gdsc: Add support for ALWAYS_ON gdscs Some GDSCs might have software control to turn them off, but we might want to keep them enabled always, in some cases because of lack of support in kernel to handle a graceful turning off/on of such GDSCs. Most common instances would be the GDCSs which power up the noc/bus fabrics, which need bus drivers to handle them and atleast support for which is missing on all qcom SoCs. Signed-off-by: Rajendra Nayak --- drivers/clk/qcom/gdsc.c | 8 ++++++++ drivers/clk/qcom/gdsc.h | 1 + 2 files changed, 9 insertions(+) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index a4f3580587b7..15f4bb5efd68 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -291,6 +291,14 @@ static int gdsc_init(struct gdsc *sc) if ((sc->flags & VOTABLE) && on) gdsc_enable(&sc->pd); + /* If ALWAYS_ON GDSCs are not ON, turn them ON */ + if (sc->flags & ALWAYS_ON) { + if (!on) + gdsc_enable(&sc->pd); + on = true; + sc->pd.flags |= GENPD_FLAG_ALWAYS_ON; + } + if (on || (sc->pwrsts & PWRSTS_RET)) gdsc_force_mem_on(sc); else diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 39648348e5ec..7fd78cec7e5b 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -53,6 +53,7 @@ struct gdsc { #define VOTABLE BIT(0) #define CLAMP_IO BIT(1) #define HW_CTRL BIT(2) +#define ALWAYS_ON BIT(3) struct reset_controller_dev *rcdev; unsigned int *resets; unsigned int reset_count; -- cgit v1.2.3 From 1efa39a6df019e352e773913ee637353cef97ae9 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 12 Oct 2017 12:28:48 +0530 Subject: clk: qcom: Register the gdscs before the clocks We have atleast some instances of ALWAYS_ON gdscs, which need to be turned ON *before* some clocks within the gdsc domain marked with a CLK_IS_CRITICAL can be turned ON. To facilitate this sequence, register the GDCSs (and hence handle the ALWAYS_ON gdscs) before we register clocks (and handle the clocks marked as CLK_IS_CRITICAL) [Archit] Move the reset registration at the top since both gdsc and clk require it. Signed-off-by: Rajendra Nayak --- drivers/clk/qcom/common.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index b8064a336d46..f8d141f06c8c 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -228,22 +228,6 @@ int qcom_cc_really_probe(struct platform_device *pdev, if (!cc) return -ENOMEM; - cc->rclks = rclks; - cc->num_rclks = num_clks; - - for (i = 0; i < num_clks; i++) { - if (!rclks[i]) - continue; - - ret = devm_clk_register_regmap(dev, rclks[i]); - if (ret) - return ret; - } - - ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc); - if (ret) - return ret; - reset = &cc->reset; reset->rcdev.of_node = dev->of_node; reset->rcdev.ops = &qcom_reset_ops; @@ -272,6 +256,22 @@ int qcom_cc_really_probe(struct platform_device *pdev, return ret; } + cc->rclks = rclks; + cc->num_rclks = num_clks; + + for (i = 0; i < num_clks; i++) { + if (!rclks[i]) + continue; + + ret = devm_clk_register_regmap(dev, rclks[i]); + if (ret) + return ret; + } + + ret = of_clk_add_hw_provider(dev->of_node, qcom_cc_clk_hw_get, cc); + if (ret) + return ret; + return 0; } EXPORT_SYMBOL_GPL(qcom_cc_really_probe); -- cgit v1.2.3 From 9bd71716535ed396ce2ccf3fa8f16bf6870cf168 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 12 Oct 2017 12:28:49 +0530 Subject: clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabled There's no bus infrastructure today to handle all the mmagic bus clocks and GDSCs needed by all the multimedia blocks in msm8996, like mdss, video, camera and gpu. Mark all these clocks with a CLK_IS_CRITICAL and GDSCs with a ALWAYS_ON flag for now so they are left always enabled. This patch should be reverted at some point when we do have a bus driver to manage these clocks and GDSCs. [Archit] Add ALWAYS_ON for mmagic_bimc_gdsc too Signed-off-by: Rajendra Nayak --- drivers/clk/qcom/mmcc-msm8996.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c index 66a2fa4ec93c..25120ab6836c 100644 --- a/drivers/clk/qcom/mmcc-msm8996.c +++ b/drivers/clk/qcom/mmcc-msm8996.c @@ -1245,7 +1245,7 @@ static struct clk_branch mmss_mmagic_ahb_clk = { .name = "mmss_mmagic_ahb_clk", .parent_names = (const char *[]){ "ahb_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, @@ -1260,7 +1260,7 @@ static struct clk_branch mmss_mmagic_cfg_ahb_clk = { .name = "mmss_mmagic_cfg_ahb_clk", .parent_names = (const char *[]){ "ahb_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, @@ -1319,7 +1319,7 @@ static struct clk_branch mmagic_camss_axi_clk = { .name = "mmagic_camss_axi_clk", .parent_names = (const char *[]){ "axi_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, @@ -1334,7 +1334,7 @@ static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = { .name = "mmagic_camss_noc_cfg_ahb_clk", .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, @@ -1439,7 +1439,7 @@ static struct clk_branch mmagic_mdss_axi_clk = { .name = "mmagic_mdss_axi_clk", .parent_names = (const char *[]){ "axi_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, @@ -1454,7 +1454,7 @@ static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = { .name = "mmagic_mdss_noc_cfg_ahb_clk", .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, @@ -1529,7 +1529,7 @@ static struct clk_branch mmagic_video_axi_clk = { .name = "mmagic_video_axi_clk", .parent_names = (const char *[]){ "axi_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, @@ -1544,7 +1544,7 @@ static struct clk_branch mmagic_video_noc_cfg_ahb_clk = { .name = "mmagic_video_noc_cfg_ahb_clk", .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, @@ -2910,6 +2910,7 @@ static struct gdsc mmagic_bimc_gdsc = { .name = "mmagic_bimc", }, .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE | ALWAYS_ON, }; static struct gdsc mmagic_video_gdsc = { @@ -2919,7 +2920,7 @@ static struct gdsc mmagic_video_gdsc = { .name = "mmagic_video", }, .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, + .flags = VOTABLE | ALWAYS_ON, }; static struct gdsc mmagic_mdss_gdsc = { @@ -2929,7 +2930,7 @@ static struct gdsc mmagic_mdss_gdsc = { .name = "mmagic_mdss", }, .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, + .flags = VOTABLE | ALWAYS_ON, }; static struct gdsc mmagic_camss_gdsc = { @@ -2939,7 +2940,7 @@ static struct gdsc mmagic_camss_gdsc = { .name = "mmagic_camss", }, .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, + .flags = VOTABLE | ALWAYS_ON, }; static struct gdsc venus_gdsc = { -- cgit v1.2.3 From 0c1394cb0f9afe67e852bf34c6c906dc218b2c70 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 7 Dec 2017 14:08:45 +0000 Subject: clk: qcom: gcc-msm8996: always enable aggre0_noc gdsc bus clks which depend on this gdsc are marked as critical, so this patch flags this gdsc ALWAYS_ON so that bus clks status does not get stuck at on or off. Signed-off-by: Srinivas Kandagatla --- drivers/clk/qcom/gcc-msm8996.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index 3d6452932797..90ac99389075 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -3105,7 +3105,7 @@ static struct gdsc aggre0_noc_gdsc = { .name = "aggre0_noc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, + .flags = VOTABLE | ALWAYS_ON, }; static struct gdsc hlos1_vote_aggre0_noc_gdsc = { -- cgit v1.2.3 From 37c2300c9aaa73d758b116fe0b8ae766d2a209aa Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Mon, 27 Nov 2017 02:24:08 -0800 Subject: irqchip/gic-v3: Support MSIs via aliases and distributor Some GIC configurations don't have an accessible ITS, but they want to support MSIs through the distributor's SETSPI registers or through the IMPLEMENTATION DEFINED message-based interrupt request register region. This mode of operation is similar to the v2m support on gic-400, but we don't necessarily know what particular SPIs are supported as MSIs so we need some help from firmware to know what to do. Introduce an "arm,spi-ranges" property for this, similar to the "marvell,spi-ranges" property, that indicates the base and size of each MSI range. This property applies equally to the distributor and alias registers. In either case, we detect this mode of operation by looking for a node with the "msi-controller" property and then probe the v2m frame code on top of it. Assume these nodes will have the "arm,spi-ranges" property in them so that the v2m code works mostly unmodified. Cc: Cc: Srinivas Kandagatla Cc: Marc Zyngier Signed-off-by: Stephen Boyd --- .../bindings/interrupt-controller/arm,gic-v3.txt | 48 ++++++++++ drivers/irqchip/irq-gic-v2m.c | 102 ++++++++++++++++----- drivers/irqchip/irq-gic-v3.c | 4 + include/linux/irqchip/arm-gic-common.h | 3 + 4 files changed, 133 insertions(+), 24 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt index 0a57f2f4167d..54a942c217e4 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt @@ -57,6 +57,11 @@ Optional occupied by the redistributors. Required if more than one such region is present. +- msi-controller : Boolean property. Identifies the node as an MSI controller + +- arm,spi-ranges : Tuples of GIC SPI interrupt ranges (base, size) indicating + SPIs available for use as MSIs. + Sub-nodes: PPI affinity can be expressed as a single "ppi-partitions" node, @@ -83,6 +88,28 @@ The main GIC node must contain the appropriate #address-cells, #size-cells and ranges properties for the reg property of all ITS nodes. +GICv3 has an IMPLEMENTATION DEFINED set of aliases for message-based interrupt +requests. + +These nodes must have the following properties: +- compatible : Should at least contain one of + "qcom,gic-msi-aliases". +- msi-controller : Boolean property. Identifies the node as an MSI controller +- #msi-cells: Must be <1>. The single msi-cell is the DeviceID of the device + which will generate the MSI. +- reg: Specifies the base physical address and size of the message-based + interrupt request registers. +- arm,spi-ranges: Tuples of GIC SPI interrupt ranges (base, size) indicating + SPIs available for use as MSIs. + +Note: The main GIC node must contain the appropriate #address-cells, +#size-cells and ranges properties for the reg property of all ITS and +alias message-based interrupt nodes. + +Optional: +- socionext,synquacer-pre-its: (u32, u32) tuple describing the untranslated + address and size of the pre-ITS window. + Examples: gic: interrupt-controller@2cf00000 { @@ -149,6 +176,27 @@ Examples: }; }; + intc: interrupt-controller@9bc0000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + reg = <0x09bc0000 0x10000>, + <0x09c00000 0x100000>; + interrupts = <1 9 4>; + + msi_alias0: interrupt-controller@9bd0000 { + compatible = "qcom,gic-msi-aliases"; + reg = <0x9bd0000 0x1000>; + msi-controller; + #msi-cells = <1>; + arm,spi-ranges = <544 96>; + }; + }; device@0 { reg = <0 0 0 4>; diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c index 1ff38aff9f29..2efac604f774 100644 --- a/drivers/irqchip/irq-gic-v2m.c +++ b/drivers/irqchip/irq-gic-v2m.c @@ -26,6 +26,7 @@ #include #include #include +#include /* * MSI_TYPER: @@ -381,13 +382,57 @@ err_free_v2m: return ret; } -static struct of_device_id gicv2m_device_id[] = { - { .compatible = "arm,gic-v2m-frame", }, - {}, +static const struct of_device_id gicv2m_device_id[] = { + { .compatible = "arm,gic-v2m-frame", }, + { .compatible = "qcom,gic-msi-aliases", }, + {} }; -static int __init gicv2m_of_init(struct fwnode_handle *parent_handle, - struct irq_domain *parent) +static int __init gicv2m_of_init_one(struct device_node *child) +{ + u32 spi_start = 0, nr_spis = 0; + struct resource res; + int ret, i, cnt; + struct fwnode_handle *fwnode = &child->fwnode; + + if (!of_find_property(child, "msi-controller", NULL)) + return 0; + + ret = of_address_to_resource(child, 0, &res); + if (ret) { + pr_err("Failed to allocate v2m resource\n"); + return ret; + } + + if (!of_property_read_u32(child, "arm,msi-base-spi", + &spi_start) && + !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis)) + pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n", + spi_start, nr_spis); + + cnt = of_property_count_u32_elems(child, "arm,spi-ranges"); + if (cnt < 0) + cnt = 0; + cnt /= 2; + + if (!cnt) + return gicv2m_init_one(fwnode, spi_start, nr_spis, &res); + + /* Populate v2m for each SPI range */ + for (i = 0; i < cnt; i++) { + of_property_read_u32_index(child, "arm,spi-ranges", + i * 2, &spi_start); + of_property_read_u32_index(child, "arm,spi-ranges", + i * 2 + 1, &nr_spis); + ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res); + if (ret) + return ret; + } + + return 0; +} + +static int __init gicv2m_of_init_children(struct fwnode_handle *parent_handle) { int ret = 0; struct device_node *node = to_of_node(parent_handle); @@ -395,35 +440,27 @@ static int __init gicv2m_of_init(struct fwnode_handle *parent_handle, for (child = of_find_matching_node(node, gicv2m_device_id); child; child = of_find_matching_node(child, gicv2m_device_id)) { - u32 spi_start = 0, nr_spis = 0; - struct resource res; - - if (!of_find_property(child, "msi-controller", NULL)) - continue; - - ret = of_address_to_resource(child, 0, &res); - if (ret) { - pr_err("Failed to allocate v2m resource.\n"); - break; - } - - if (!of_property_read_u32(child, "arm,msi-base-spi", - &spi_start) && - !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis)) - pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n", - spi_start, nr_spis); - - ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis, &res); + ret = gicv2m_of_init_one(child); if (ret) { of_node_put(child); break; } } + return ret; +} + +static int __init gicv2m_of_init(struct fwnode_handle *parent_handle, + struct irq_domain *parent) +{ + int ret; + + ret = gicv2m_of_init_children(parent_handle); if (!ret) ret = gicv2m_allocate_domains(parent); if (ret) gicv2m_teardown(); + return ret; } @@ -516,6 +553,23 @@ static int __init gicv2m_acpi_init(struct irq_domain *parent) } #endif /* CONFIG_ACPI */ +int __init gicv2m_init_gicv3(struct fwnode_handle *handle, + struct irq_domain *parent) +{ + int ret; + struct device_node *node = to_of_node(handle); + + ret = gicv2m_of_init_children(handle); + if (!ret) + ret = gicv2m_of_init_one(node); + if (!ret) + ret = gicv2m_allocate_domains(parent); + if (ret) + gicv2m_teardown(); + + return ret; +} + int __init gicv2m_init(struct fwnode_handle *parent_handle, struct irq_domain *parent) { diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 8c32e679eca0..f799bcd0085a 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -1316,6 +1316,10 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare if (static_branch_likely(&supports_deactivate_key)) gic_of_setup_kvm_info(node); + + if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) + gicv2m_init_gicv3(&node->fwnode, gic_data.domain); + return 0; out_unmap_rdist: diff --git a/include/linux/irqchip/arm-gic-common.h b/include/linux/irqchip/arm-gic-common.h index 0a83b4379f34..d2eea9539d37 100644 --- a/include/linux/irqchip/arm-gic-common.h +++ b/include/linux/irqchip/arm-gic-common.h @@ -33,4 +33,7 @@ struct gic_kvm_info { const struct gic_kvm_info *gic_get_kvm_info(void); +int gicv2m_init_gicv3(struct fwnode_handle *parent_handle, + struct irq_domain *parent); + #endif /* __LINUX_IRQCHIP_ARM_GIC_COMMON_H */ -- cgit v1.2.3 From 4adf944ddfa26c53425519178faa5fca936d516a Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 29 Nov 2017 20:19:07 -0800 Subject: scsi: ufs: ufshcd: Enable no_write_same for scsi host Occasionally the following error message can be seen in the logs of Qualcomm devices using UFS: EXT4-fs (sda9): Delayed block allocation failed for inode 685600 at logical offset 1086 with max blocks 3 with error 121 EXT4-fs (sda9): This should not happen!! Data will be lost This is caused by a failing WRITE_SAME command, which per the JEDEC UFS specification is not a supported. Set the no_write_same flag on the ufshcd SCSI host to let the SCSI layer know this. Fixes: 7a3e97b0dc4b ("[SCSI] ufshcd: UFS Host controller driver") Cc: stable@vger.kernel.org Signed-off-by: Bjorn Andersson --- drivers/scsi/ufs/ufshcd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index c5b1bf1cadcb..8f22a980b1a7 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -6509,6 +6509,7 @@ static struct scsi_host_template ufshcd_driver_template = { .max_host_blocked = 1, .track_queue_depth = 1, .sdev_groups = ufshcd_driver_groups, + .no_write_same = 1, }; static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg, -- cgit v1.2.3 From 4b05960ae1f0d80e9db4b77e2b14344722427586 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 14 Dec 2017 16:01:45 +0000 Subject: clk: qcom: gcc-msm8996: always enable lpass gdsc Signed-off-by: Srinivas Kandagatla --- drivers/clk/qcom/gcc-msm8996.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index 90ac99389075..9ad768a41ca1 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -3123,7 +3123,7 @@ static struct gdsc hlos1_vote_lpass_adsp_gdsc = { .name = "hlos1_vote_lpass_adsp", }, .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, + .flags = VOTABLE | ALWAYS_ON, }; static struct gdsc hlos1_vote_lpass_core_gdsc = { @@ -3132,7 +3132,7 @@ static struct gdsc hlos1_vote_lpass_core_gdsc = { .name = "hlos1_vote_lpass_core", }, .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, + .flags = VOTABLE | ALWAYS_ON, }; static struct gdsc usb30_gdsc = { -- cgit v1.2.3 From 910a253598cb90f041d1d019ec7a7491dec16062 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 8 Dec 2017 09:14:20 +0000 Subject: PCI: qcom: add missing supplies required for msm8996 This patch adds supplies that are required for msm8996. Two of them vdda and vdda-1p8 are analog supplies that go in to controller, and the rest of the two vddpe's are supplies to PCIe endpoints. Without these supplies PCIe endpoints which require power supplies are not enumerated at all, as there is no one to power it up. Signed-off-by: Srinivas Kandagatla --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 18 ++++++++++++++++++ drivers/pci/dwc/pcie-qcom.c | 3 +++ 2 files changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 1fd703bd73e0..09e166d15532 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -179,6 +179,11 @@ Value type: Definition: A phandle to the core analog power supply +- vdda-1p8-supply: + Usage: required for msm8996 + Value type: + Definition: A phandle to the 1.8v analog power supply + - vdda_phy-supply: Usage: required for ipq/apq8064 Value type: @@ -189,11 +194,22 @@ Value type: Definition: A phandle to the analog power supply for IC which generates reference clock + - vddpe-3v3-supply: Usage: optional Value type: Definition: A phandle to the PCIe endpoint power supply +- vddpe-supply: + Usage: optional + Value type: + Definition: A phandle to the PCIe endpoint power supply + +- vddpe1-supply: + Usage: optional + Value type: + Definition: A phandle to the PCIe endpoint power supply 1 + - phys: Usage: required for apq8084 Value type: @@ -209,6 +225,8 @@ Value type: Definition: List of phandle and GPIO specifier pairs. Should contain - "perst-gpios" PCIe endpoint reset signal line + - "pe_en-gpios" PCIe endpoint enable signal line + - "pe_en1-gpios" PCIe endpoint enable1 signal line - "wake-gpios" PCIe endpoint wake signal line * Example for ipq/apq8064 diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c index 58988b482939..da05eae3b2f0 100644 --- a/drivers/pci/dwc/pcie-qcom.c +++ b/drivers/pci/dwc/pcie-qcom.c @@ -497,6 +497,9 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) int ret; res->supplies[0].supply = "vdda"; + res->supplies[1].supply = "vdda-1p8"; + res->supplies[2].supply = "vddpe"; + res->supplies[3].supply = "vddpe1"; res->supplies[1].supply = "vddpe-3v3"; ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), res->supplies); -- cgit v1.2.3 From ea74ef396fba8097d15dc7dcf61ceddc55425fb2 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 13 Mar 2017 18:19:33 +0000 Subject: pcie: qcom: Add support to enable pcie refclk This patch adds support to enable 100MHz pcie refclk, On some boards like DB600c this clock is not enabled by default. Signed-off-by: Srinivas Kandagatla --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 1 + drivers/pci/dwc/pcie-qcom.c | 21 ++++++++++++++++++++- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 09e166d15532..ca40d4318d87 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -88,6 +88,7 @@ Definition: Should contain the following entries - "core" Clocks the pcie hw block - "phy" Clocks the pcie PHY block + - "ref" Clocks the pcie refclk - clock-names: Usage: required for apq8084/ipq4019 Value type: diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c index da05eae3b2f0..4937478c4d10 100644 --- a/drivers/pci/dwc/pcie-qcom.c +++ b/drivers/pci/dwc/pcie-qcom.c @@ -83,6 +83,7 @@ struct qcom_pcie_resources_2_1_0 { struct clk *iface_clk; struct clk *core_clk; + struct clk *ref_clk; struct clk *phy_clk; struct reset_control *pci_reset; struct reset_control *axi_reset; @@ -224,6 +225,15 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->iface_clk)) return PTR_ERR(res->iface_clk); + res->ref_clk = devm_clk_get(dev, "ref"); + + if (IS_ERR(res->ref_clk)) { + if (PTR_ERR(res->ref_clk) == -EPROBE_DEFER) + return PTR_ERR(res->ref_clk); + + res->ref_clk = NULL; + } + res->core_clk = devm_clk_get(dev, "core"); if (IS_ERR(res->core_clk)) return PTR_ERR(res->core_clk); @@ -262,6 +272,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->por_reset); reset_control_assert(res->pci_reset); clk_disable_unprepare(res->iface_clk); + clk_disable_unprepare(res->ref_clk); clk_disable_unprepare(res->core_clk); clk_disable_unprepare(res->phy_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -287,10 +298,16 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_assert_ahb; } + ret = clk_prepare_enable(res->ref_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable ref clock\n"); + goto err_assert_ahb; + } + ret = clk_prepare_enable(res->iface_clk); if (ret) { dev_err(dev, "cannot prepare/enable iface clock\n"); - goto err_assert_ahb; + goto err_clk_iface; } ret = clk_prepare_enable(res->phy_clk); @@ -363,6 +380,8 @@ err_clk_core: clk_disable_unprepare(res->phy_clk); err_clk_phy: clk_disable_unprepare(res->iface_clk); +err_clk_iface: + clk_disable_unprepare(res->ref_clk); err_assert_ahb: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); -- cgit v1.2.3 From 5ea93cb3fc111973ff888dc1b0f1bc712164e4db Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 6 Dec 2016 14:52:19 +0530 Subject: [HACK] clk: qcom: Hook up gpu_gx gdsc as a parent of gpu_gdsc the GPU device on msm8996 requires 2 gdscs to be powered on. With powerdomains we have a limitation wherein only one powerdomain can be associated with a given device in DT. So hook the 2 gdscs together so both are powered on/off when the gpu driver needs them to. [Amit] We use this hack until genpd allows multiple powerdomains to be associated with a device. Signed-off-by: Rajendra Nayak Signed-off-by: Amit Kucheria --- drivers/clk/qcom/mmcc-msm8996.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c index 25120ab6836c..4ca95ff6f94e 100644 --- a/drivers/clk/qcom/mmcc-msm8996.c +++ b/drivers/clk/qcom/mmcc-msm8996.c @@ -3055,16 +3055,6 @@ static struct gdsc mdss_gdsc = { .pwrsts = PWRSTS_OFF_ON, }; -static struct gdsc gpu_gdsc = { - .gdscr = 0x4034, - .gds_hw_ctrl = 0x4038, - .pd = { - .name = "gpu", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, -}; - static struct gdsc gpu_gx_gdsc = { .gdscr = 0x4024, .clamp_io_ctrl = 0x4300, @@ -3077,6 +3067,17 @@ static struct gdsc gpu_gx_gdsc = { .flags = CLAMP_IO, }; +static struct gdsc gpu_gdsc = { + .gdscr = 0x4034, + .gds_hw_ctrl = 0x4038, + .pd = { + .name = "gpu", + }, + .parent = &gpu_gx_gdsc.pd, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + static struct clk_regmap *mmcc_msm8996_clocks[] = { [MMPLL0_EARLY] = &mmpll0_early.clkr, [MMPLL0_PLL] = &mmpll0.clkr, -- cgit v1.2.3 From 3414899e874a7c5bb89c9c0606a9c30373c833d3 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 25 Apr 2018 13:10:40 +0200 Subject: arm64: msm8916: fix gic_irq_domain_translate warnings Remove the usage of IRQ_TYPE_NONE to fix loud warnings from patch (83a86fbb5b56b "irqchip/gic: Loudly complain about the use of IRQ_TYPE_NONE"). Signed-off-by: Srinivas Kandagatla Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 66b318e1de80..650f356f69ca 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -179,7 +179,7 @@ pmu { compatible = "arm,cortex-a53-pmu"; - interrupts = ; + interrupts = ; }; thermal-zones { @@ -512,7 +512,7 @@ blsp_i2c2: i2c@78b6000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b6000 0x500>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; clock-names = "iface", "core"; @@ -527,7 +527,7 @@ blsp_i2c4: i2c@78b8000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b8000 0x500>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; clock-names = "iface", "core"; @@ -542,7 +542,7 @@ blsp_i2c6: i2c@78ba000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078ba000 0x500>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; clock-names = "iface", "core"; @@ -574,7 +574,7 @@ "mi2s-bit-clk3"; #sound-dai-cells = <1>; - interrupts = <0 160 0>; + interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "lpass-irq-lpaif"; reg = <0x07708000 0x10000>; reg-names = "lpass-lpaif"; @@ -594,7 +594,7 @@ reg = <0x07824900 0x11c>, <0x07824000 0x800>; reg-names = "hc_mem", "core_mem"; - interrupts = <0 123 0>, <0 138 0>; + interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, @@ -611,7 +611,7 @@ reg = <0x07864900 0x11c>, <0x07864000 0x800>; reg-names = "hc_mem", "core_mem"; - interrupts = <0 125 0>, <0 221 0>; + interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>, @@ -818,7 +818,7 @@ iommu-ctx@2000 { compatible = "qcom,msm-iommu-v1-ns"; reg = <0x2000 0x1000>; - interrupts = ; + interrupts = ; }; }; @@ -862,7 +862,7 @@ "bus_clk", "vsync_clk"; - interrupts = <0 72 0>; + interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; -- cgit v1.2.3