From 10a39681fe6196a4ace96ac8bcf36fd1d7ef80c1 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Mon, 15 Oct 2018 17:55:15 +0530 Subject: drivers: thermal: tsens: Add generic support for TSENS v1 IP qcs404 has a single TSENS IP block with 10 sensors. It uses version 1.4 of the TSENS IP, functionality for which is encapsulated inside qcom,tsens-v1 compatible. Signed-off-by: Amit Kucheria Reviewed-by: Vinod Koul Tested-by: Vinod Koul --- drivers/thermal/qcom/Makefile | 2 +- drivers/thermal/qcom/tsens-common.c | 2 +- drivers/thermal/qcom/tsens-v1.c | 196 ++++++++++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.c | 3 + drivers/thermal/qcom/tsens.h | 3 +- 5 files changed, 203 insertions(+), 3 deletions(-) create mode 100644 drivers/thermal/qcom/tsens-v1.c diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile index a821929ede0b..60269ee90c43 100644 --- a/drivers/thermal/qcom/Makefile +++ b/drivers/thermal/qcom/Makefile @@ -1,2 +1,2 @@ obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o -qcom_tsens-y += tsens.o tsens-common.o tsens-8916.o tsens-8974.o tsens-8960.o tsens-v2.o +qcom_tsens-y += tsens.o tsens-common.o tsens-8916.o tsens-8974.o tsens-8960.o tsens-v2.o tsens-v1.o diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 3be4be2e0465..98f77401bc12 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -76,7 +76,7 @@ void compute_intercept_slope(struct tsens_device *tmdev, u32 *p1, } } -static inline int code_to_degc(u32 adc_code, const struct tsens_sensor *s) +int code_to_degc(u32 adc_code, const struct tsens_sensor *s) { int degc, num, den; diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c new file mode 100644 index 000000000000..1dbf4fde6da8 --- /dev/null +++ b/drivers/thermal/qcom/tsens-v1.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, Linaro Limited + */ + +#include +#include +#include "tsens.h" + +/* eeprom layout data for qcs404 (v1) */ +#define BASE0_MASK 0x000007f8 +#define BASE1_MASK 0x0007f800 +#define BASE0_SHIFT 3 +#define BASE1_SHIFT 11 + +#define S0_P1_MASK 0x0000003f +#define S1_P1_MASK 0x0003f000 +#define S2_P1_MASK 0x3f000000 +#define S3_P1_MASK 0x000003f0 +#define S4_P1_MASK 0x003f0000 +#define S5_P1_MASK 0x0000003f +#define S6_P1_MASK 0x0003f000 +#define S7_P1_MASK 0x3f000000 +#define S8_P1_MASK 0x000003f0 +#define S9_P1_MASK 0x003f0000 + +#define S0_P2_MASK 0x00000fc0 +#define S1_P2_MASK 0x00fc0000 +#define S2_P2_MASK_1_0 0xc0000000 +#define S2_P2_MASK_5_2 0x0000000f +#define S3_P2_MASK 0x0000fc00 +#define S4_P2_MASK 0x0fc00000 +#define S5_P2_MASK 0x00000fc0 +#define S6_P2_MASK 0x00fc0000 +#define S7_P2_MASK_1_0 0xc0000000 +#define S7_P2_MASK_5_2 0x0000000f +#define S8_P2_MASK 0x0000fc00 +#define S9_P2_MASK 0x0fc00000 + +#define S0_P1_SHIFT 0 +#define S0_P2_SHIFT 6 +#define S1_P1_SHIFT 12 +#define S1_P2_SHIFT 18 +#define S2_P1_SHIFT 24 +#define S2_P2_SHIFT_1_0 30 + +#define S2_P2_SHIFT_5_2 0 +#define S3_P1_SHIFT 4 +#define S3_P2_SHIFT 10 +#define S4_P1_SHIFT 16 +#define S4_P2_SHIFT 22 + +#define S5_P1_SHIFT 0 +#define S5_P2_SHIFT 6 +#define S6_P1_SHIFT 12 +#define S6_P2_SHIFT 18 +#define S7_P1_SHIFT 24 +#define S7_P2_SHIFT_1_0 30 + +#define S7_P2_SHIFT_5_2 0 +#define S8_P1_SHIFT 4 +#define S8_P2_SHIFT 10 +#define S9_P1_SHIFT 16 +#define S9_P2_SHIFT 22 + +#define CAL_SEL_MASK 7 +#define CAL_SEL_SHIFT 0 + +static int calibrate_v1(struct tsens_device *tmdev) +{ + u32 base0 = 0, base1 = 0; + u32 p1[10], p2[10]; + u32 mode = 0, lsb = 0, msb = 0; + u32 *qfprom_cdata; + int i; + + qfprom_cdata = (u32 *)qfprom_read(tmdev->dev, "calib"); + if (IS_ERR(qfprom_cdata)) + return PTR_ERR(qfprom_cdata); + + mode = (qfprom_cdata[4] & CAL_SEL_MASK) >> CAL_SEL_SHIFT; + dev_dbg(tmdev->dev, "calibration mode is %d\n", mode); + + switch (mode) { + case TWO_PT_CALIB: + base1 = (qfprom_cdata[4] & BASE1_MASK) >> BASE1_SHIFT; + p2[0] = (qfprom_cdata[0] & S0_P2_MASK) >> S0_P2_SHIFT; + p2[1] = (qfprom_cdata[0] & S1_P2_MASK) >> S1_P2_SHIFT; + /* This value is split over two registers, 2 bits and 4 bits */ + lsb = (qfprom_cdata[0] & S2_P2_MASK_1_0) >> S2_P2_SHIFT_1_0; + msb = (qfprom_cdata[1] & S2_P2_MASK_5_2) >> S2_P2_SHIFT_5_2; + p2[2] = msb << 2 | lsb; + p2[3] = (qfprom_cdata[1] & S3_P2_MASK) >> S3_P2_SHIFT; + p2[4] = (qfprom_cdata[1] & S4_P2_MASK) >> S4_P2_SHIFT; + p2[5] = (qfprom_cdata[2] & S5_P2_MASK) >> S5_P2_SHIFT; + p2[6] = (qfprom_cdata[2] & S6_P2_MASK) >> S6_P2_SHIFT; + /* This value is split over two registers, 2 bits and 4 bits */ + lsb = (qfprom_cdata[2] & S7_P2_MASK_1_0) >> S7_P2_SHIFT_1_0; + msb = (qfprom_cdata[3] & S7_P2_MASK_5_2) >> S7_P2_SHIFT_5_2; + p2[7] = msb << 2 | lsb; + p2[8] = (qfprom_cdata[3] & S8_P2_MASK) >> S8_P2_SHIFT; + p2[9] = (qfprom_cdata[3] & S9_P2_MASK) >> S9_P2_SHIFT; + for (i = 0; i < tmdev->num_sensors; i++) + p2[i] = ((base1 + p2[i]) << 2); + /* Fall through */ + case ONE_PT_CALIB2: + base0 = (qfprom_cdata[4] & BASE0_MASK) >> BASE0_SHIFT; + p1[0] = (qfprom_cdata[0] & S0_P1_MASK) >> S0_P1_SHIFT; + p1[1] = (qfprom_cdata[0] & S1_P1_MASK) >> S1_P1_SHIFT; + p1[2] = (qfprom_cdata[0] & S2_P1_MASK) >> S2_P1_SHIFT; + p1[3] = (qfprom_cdata[1] & S3_P1_MASK) >> S3_P1_SHIFT; + p1[4] = (qfprom_cdata[1] & S4_P1_MASK) >> S4_P1_SHIFT; + p1[5] = (qfprom_cdata[2] & S5_P1_MASK) >> S5_P1_SHIFT; + p1[6] = (qfprom_cdata[2] & S6_P1_MASK) >> S6_P1_SHIFT; + p1[7] = (qfprom_cdata[2] & S7_P1_MASK) >> S7_P1_SHIFT; + p1[8] = (qfprom_cdata[3] & S8_P1_MASK) >> S8_P1_SHIFT; + p1[9] = (qfprom_cdata[3] & S9_P1_MASK) >> S9_P1_SHIFT; + for (i = 0; i < tmdev->num_sensors; i++) + p1[i] = (((base0) + p1[i]) << 2); + break; + default: + for (i = 0; i < tmdev->num_sensors; i++) { + p1[i] = 500; + p2[i] = 780; + } + break; + } + + compute_intercept_slope(tmdev, p1, p2, mode); + + return 0; +} + +#define STATUS_OFFSET 0x44 +#define LAST_TEMP_MASK 0x3ff +#define STATUS_VALID_BIT BIT(14) + +static int get_temp_tsens_v1(struct tsens_device *tmdev, int id, int *temp) +{ + struct tsens_sensor *s = &tmdev->sensor[id]; + u32 code; + unsigned int status_reg; + u32 last_temp = 0, last_temp2 = 0, last_temp3 = 0; + int ret; + + status_reg = tmdev->tm_offset + STATUS_OFFSET + s->hw_id * 4; + ret = regmap_read(tmdev->tm_map, status_reg, &code); + if (ret) + return ret; + last_temp = code & LAST_TEMP_MASK; + if (code & STATUS_VALID_BIT) + goto done; + + /* Try a second time */ + ret = regmap_read(tmdev->tm_map, status_reg, &code); + if (ret) + return ret; + if (code & STATUS_VALID_BIT) { + last_temp = code & LAST_TEMP_MASK; + goto done; + } else { + last_temp2 = code & LAST_TEMP_MASK; + } + + /* Try a third/last time */ + ret = regmap_read(tmdev->tm_map, status_reg, &code); + if (ret) + return ret; + if (code & STATUS_VALID_BIT) { + last_temp = code & LAST_TEMP_MASK; + goto done; + } else { + last_temp3 = code & LAST_TEMP_MASK; + } + + if (last_temp == last_temp2) + last_temp = last_temp2; + else if (last_temp2 == last_temp3) + last_temp = last_temp3; +done: + /* Convert temperature from ADC code to milliCelsius */ + *temp = code_to_degc(last_temp, s) * 1000; + + return 0; +} + +static const struct tsens_ops ops_generic_v1 = { + .init = init_common, + .calibrate = calibrate_v1, + .get_temp = get_temp_tsens_v1, +}; + +const struct tsens_data data_tsens_v1 = { + .ops = &ops_generic_v1, + .reg_offsets = { [SROT_CTRL_OFFSET] = 0x4 }, +}; diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index f1ec9bbe4717..d0cc0c09894a 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -63,6 +63,9 @@ static const struct of_device_id tsens_table[] = { }, { .compatible = "qcom,msm8996-tsens", .data = &data_8996, + }, { + .compatible = "qcom,tsens-v1", + .data = &data_tsens_v1, }, { .compatible = "qcom,tsens-v2", .data = &data_tsens_v2, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 7b7feee5dc46..f8dc96c42b94 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -90,9 +90,10 @@ char *qfprom_read(struct device *, const char *); void compute_intercept_slope(struct tsens_device *, u32 *, u32 *, u32); int init_common(struct tsens_device *); int get_temp_common(struct tsens_device *, int, int *); +int code_to_degc(u32 adc_code, const struct tsens_sensor *s); /* TSENS v1 targets */ -extern const struct tsens_data data_8916, data_8974, data_8960; +extern const struct tsens_data data_8916, data_8974, data_8960, data_tsens_v1; /* TSENS v2 targets */ extern const struct tsens_data data_8996, data_tsens_v2; -- cgit v1.2.3 From 5fe04f94a00a29c149e9452c92607d8a22c4816a Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 14 Sep 2018 12:18:54 -0700 Subject: clk: qcom: smd: Add support for QCS404 rpm clocks Add rpm smd clocks, PMIC and bus clocks which are required on QCS404 for clients to vote on. Signed-off-by: Taniya Das Signed-off-by: Anu Ramanathan [bjorn: Dropped voter clocks and static initialization] Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/clock/qcom,rpmcc.txt | 1 + .../devicetree/bindings/soc/qcom/qcom,smd-rpm.txt | 1 + drivers/clk/qcom/clk-smd-rpm.c | 48 ++++++++++++++++++++++ drivers/soc/qcom/smd-rpm.c | 1 + drivers/thermal/qcom/tsens-common.c | 2 +- drivers/thermal/qcom/tsens-v1.c | 6 +-- drivers/thermal/qcom/tsens.h | 1 - include/dt-bindings/clock/qcom,rpmcc.h | 4 ++ 8 files changed, 59 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt index 4491d1c104aa..87b4949e9bc8 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt @@ -16,6 +16,7 @@ Required properties : "qcom,rpmcc-msm8974", "qcom,rpmcc" "qcom,rpmcc-apq8064", "qcom,rpmcc" "qcom,rpmcc-msm8996", "qcom,rpmcc" + "qcom,rpmcc-qcs404", "qcom,rpmcc" - #clock-cells : shall contain 1 diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt index 89e1cb9212f6..ec95705ba692 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt @@ -23,6 +23,7 @@ resources. "qcom,rpm-msm8916" "qcom,rpm-msm8974" "qcom,rpm-msm8998" + "qcom,rpm-qcs404" - qcom,smd-channels: Usage: required diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 850c02a52248..16fe4b119c38 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -611,10 +611,58 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { .num_clks = ARRAY_SIZE(msm8996_clks), }; +/* QCS404 */ +DEFINE_CLK_SMD_RPM_BRANCH(qcs404, cxo, cxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000); +DEFINE_CLK_SMD_RPM_QDSS(qcs404, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); + +DEFINE_CLK_SMD_RPM(qcs404, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); +DEFINE_CLK_SMD_RPM(qcs404, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); + +DEFINE_CLK_SMD_RPM(qcs404, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); +DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); + +DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0); +DEFINE_CLK_SMD_RPM(qcs404, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); + +DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, rf_clk1, rf_clk1_a, 4); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, rf_clk1_pin, rf_clk1_a_pin, 4); + +DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, ln_bb_clk, ln_bb_a_clk, 8); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8); + +static struct clk_smd_rpm *qcs404_clks[] = { +// [RPM_SMD_XO_CLK_SRC] = &qcs404_cxo, +// [RPM_SMD_XO_A_CLK_SRC] = &qcs404_cxo_a, + [RPM_SMD_QDSS_CLK] = &qcs404_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &qcs404_qdss_a_clk, + [RPM_SMD_PNOC_CLK] = &qcs404_pnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &qcs404_pnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &qcs404_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &qcs404_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &qcs404_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &qcs404_bimc_a_clk, + [RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk, + [RPM_SMD_BIMC_GPU_A_CLK] = &qcs404_bimc_gpu_a_clk, + [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk, + [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk, + [RPM_SMD_CE1_CLK] = &qcs404_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &qcs404_ce1_a_clk, + [RPM_SMD_RF_CLK1] = &qcs404_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &qcs404_rf_clk1_a, + [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk, + [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_a_clk, +}; + +static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { + .clks = qcs404_clks, + .num_clks = ARRAY_SIZE(qcs404_clks), +}; + static const struct of_device_id rpm_smd_clk_match_table[] = { { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 }, { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 }, { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 }, + { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 }, { } }; MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c index 93517ed83355..b8e63724a49d 100644 --- a/drivers/soc/qcom/smd-rpm.c +++ b/drivers/soc/qcom/smd-rpm.c @@ -227,6 +227,7 @@ static const struct of_device_id qcom_smd_rpm_of_match[] = { { .compatible = "qcom,rpm-msm8974" }, { .compatible = "qcom,rpm-msm8996" }, { .compatible = "qcom,rpm-msm8998" }, + { .compatible = "qcom,rpm-qcs404" }, {} }; MODULE_DEVICE_TABLE(of, qcom_smd_rpm_of_match); diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 98f77401bc12..3be4be2e0465 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -76,7 +76,7 @@ void compute_intercept_slope(struct tsens_device *tmdev, u32 *p1, } } -int code_to_degc(u32 adc_code, const struct tsens_sensor *s) +static inline int code_to_degc(u32 adc_code, const struct tsens_sensor *s) { int degc, num, den; diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 1dbf4fde6da8..297bcac3b94e 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -69,7 +69,7 @@ static int calibrate_v1(struct tsens_device *tmdev) { u32 base0 = 0, base1 = 0; - u32 p1[10], p2[10]; + u32 p1[tmdev->num_sensors], p2[tmdev->num_sensors]; u32 mode = 0, lsb = 0, msb = 0; u32 *qfprom_cdata; int i; @@ -178,8 +178,8 @@ static int get_temp_tsens_v1(struct tsens_device *tmdev, int id, int *temp) else if (last_temp2 == last_temp3) last_temp = last_temp3; done: - /* Convert temperature from ADC code to milliCelsius */ - *temp = code_to_degc(last_temp, s) * 1000; + /* Convert temperature from deciCelsius to milliCelsius */ + *temp = sign_extend32(last_temp, fls(LAST_TEMP_MASK) - 1) * 100; return 0; } diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index f8dc96c42b94..7060c22ea611 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -90,7 +90,6 @@ char *qfprom_read(struct device *, const char *); void compute_intercept_slope(struct tsens_device *, u32 *, u32 *, u32); int init_common(struct tsens_device *); int get_temp_common(struct tsens_device *, int, int *); -int code_to_degc(u32 adc_code, const struct tsens_sensor *s); /* TSENS v1 targets */ extern const struct tsens_data data_8916, data_8974, data_8960, data_tsens_v1; diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index c585b82b9c05..3658b0c14966 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -123,5 +123,9 @@ #define RPM_SMD_DIV_A_CLK3 73 #define RPM_SMD_LN_BB_CLK 74 #define RPM_SMD_LN_BB_A_CLK 75 +#define RPM_SMD_BIMC_GPU_CLK 76 +#define RPM_SMD_BIMC_GPU_A_CLK 77 +#define RPM_SMD_QPIC_CLK 78 +#define RPM_SMD_QPIC_CLK_A 79 #endif -- cgit v1.2.3 From ecb5d46cbc362c1f0a6469b14eb8b7a06c583923 Mon Sep 17 00:00:00 2001 From: Sriharsha Allenki Date: Thu, 1 Nov 2018 09:18:25 -0700 Subject: dt-bindings: phy: Add Qualcomm Synopsys High-Speed USB PHY binding It adds bindings for Synopsys 28nm femto phy controller that supports LS/FS/HS usb connectivity on Qualcomm chipsets. Changes for v4: - Kill device tree property 'qcom,init-seq' by moving the settings into phy driver as device match data. Changes for v3: - Use SoC specific compatible "qcom,qcs404-usb-hsphy". - Use OF graph instead of extcon bindings to model the link to USB connector. Changes for v2: - Add a pointer to phy/phy-bindings.txt for property #phy-cells. Signed-off-by: Sriharsha Allenki Signed-off-by: Anu Ramanathan Signed-off-by: Bjorn Andersson Signed-off-by: Shawn Guo --- .../bindings/phy/qcom,snps-28nm-usb-hs-phy.txt | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt b/Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt new file mode 100644 index 000000000000..301987e716fd --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt @@ -0,0 +1,87 @@ +Qualcomm Synopsys 28nm Femto phy controller +=========================================== + +Synopsys 28nm femto phy controller supports LS/FS/HS usb connectivity on +Qualcomm chipsets. + +Required properties: + +- compatible: + Value type: + Definition: Should contain "qcom,qcs404-usb-hsphy". + +- reg: + Value type: + Definition: USB PHY base address and length of the register map. + +- #phy-cells: + Value type: + Definition: Should be 0. See phy/phy-bindings.txt for details. + +- clocks: + Value type: + Definition: See clock-bindings.txt section "consumers". List of + three clock specifiers for reference, phy core and + sleep clocks. + +- clock-names: + Value type: + Definition: Names of the clocks in 1-1 correspondence with the "clocks" + property. Must contain "ref", "phy" and "sleep". + +- resets: + Value type: + Definition: See reset.txt section "consumers". PHY reset specifiers + for phy core and POR resets. + +- reset-names: + Value type: + Definition: Names of the resets in 1-1 correspondence with the "resets" + property. Must contain "phy" and "por". + +- vdd-supply: + Value type: + Definition: phandle to the regulator VDD supply node. + +- vdda1p8-supply: + Value type: + Definition: phandle to the regulator 1.8V supply node. + +- vdda3p3-supply: + Value type: + Definition: phandle to the regulator 3.3V supply node. + +- qcom,vdd-voltage-level: + Value type: + Definition: This is a list of three integer values where + each value corresponding to voltage corner in uV. + +Optional child nodes: + +- The link to the USB connector should be modeled using the OF graph bindings + specified in bindings/graph.txt. + +Example: + + phy@7a000 { + compatible = "qcom,qcs404-usb-hsphy"; + reg = <0x7a000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "phy", "sleep"; + resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&gcc GCC_USB2A_PHY_BCR>; + reset-names = "phy", "por"; + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + qcom,vdd-voltage-level = <0 1144000 1200000>; + + port { + ep_usb_phy: endpoint { + remote-endpoint = <&ep_usb_con>; + }; + }; + }; -- cgit v1.2.3 From 66cb0ace0b7aff33bbc32fe98013ca1b9d029042 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 5 Nov 2018 14:29:21 +0800 Subject: phy: qualcomm: Add Synopsys High-Speed USB PHY driver It adds Synopsys 28nm Femto High-Speed USB PHY driver support, which is usually paired with Synopsys DWC3 USB controllers on Qualcomm SoCs. Changes for v2: - Roll back voltage settings in case function qcom_snps_hsphy_config_regulators() fails in the middle. - Add a comment for init-seq tuple which consists of 3 numbers. - Sort include headers alphabetically. - Sort register definitions in order of offset. Signed-off-by: Shawn Guo --- drivers/phy/qualcomm/Kconfig | 10 + drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-usb-hs-snsp-28nm.c | 535 +++++++++++++++++++++++ 3 files changed, 546 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-usb-hs-snsp-28nm.c diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index 32f7d34eb784..c7b5ee82895d 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -82,3 +82,13 @@ config PHY_QCOM_USB_HSIC select GENERIC_PHY help Support for the USB HSIC ULPI compliant PHY on QCOM chipsets. + +config PHY_QCOM_USB_HS_SNPS_28NM + tristate "Qualcomm Synopsys 28nm USB HS PHY driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in + select GENERIC_PHY + help + Enable this to support the Synopsys 28nm Femto USB PHY on Qualcomm + chips. This driver supports the high-speed PHY which is usually + paired with either the ChipIdea or Synopsys DWC3 USB IPs on MSM SOCs. diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index c56efd3af205..dc238d95b18c 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-qcom-ufs-qmp-14nm.o obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o +obj-$(CONFIG_PHY_QCOM_USB_HS_SNPS_28NM) += phy-qcom-usb-hs-snsp-28nm.o diff --git a/drivers/phy/qualcomm/phy-qcom-usb-hs-snsp-28nm.c b/drivers/phy/qualcomm/phy-qcom-usb-hs-snsp-28nm.c new file mode 100644 index 000000000000..ee52bb6df6da --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-usb-hs-snsp-28nm.c @@ -0,0 +1,535 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2009-2018, Linux Foundation. All rights reserved. + * Copyright (c) 2018, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PHY register and bit definitions */ +#define PHY_CTRL_COMMON0 0x078 +#define SIDDQ BIT(2) +#define PHY_IRQ_CMD 0x0d0 +#define PHY_INTR_MASK0 0x0d4 +#define PHY_INTR_CLEAR0 0x0dc +#define DPDM_MASK 0x1e +#define DP_1_0 BIT(4) +#define DP_0_1 BIT(3) +#define DM_1_0 BIT(2) +#define DM_0_1 BIT(1) + +enum hsphy_voltage { + VOL_NONE, + VOL_MIN, + VOL_MAX, + VOL_NUM, +}; + +enum hsphy_vreg { + VDD, + VDDA_1P8, + VDDA_3P3, + VREG_NUM, +}; + +struct hsphy_init_seq { + int offset; + int val; + int delay; +}; + +struct hsphy_data { + const struct hsphy_init_seq *init_seq; + unsigned int init_seq_num; +}; + +struct hsphy_priv { + void __iomem *base; + struct clk_bulk_data *clks; + int num_clks; + struct reset_control *phy_reset; + struct reset_control *por_reset; + struct regulator_bulk_data vregs[VREG_NUM]; + unsigned int voltages[VREG_NUM][VOL_NUM]; + const struct hsphy_data *data; + bool cable_connected; + struct extcon_dev *vbus_edev; + struct notifier_block vbus_notify; + enum phy_mode mode; +}; + +static int qcom_snps_hsphy_config_regulators(struct hsphy_priv *priv, int high) +{ + int old_uV[VREG_NUM]; + int min, ret, i; + + min = high ? 1 : 0; /* low or none? */ + + for (i = 0; i < VREG_NUM; i++) { + old_uV[i] = regulator_get_voltage(priv->vregs[i].consumer); + ret = regulator_set_voltage(priv->vregs[i].consumer, + priv->voltages[i][min], + priv->voltages[i][VOL_MAX]); + if (ret) + goto roll_back; + } + + return 0; + +roll_back: + for (; i >= 0; i--) + regulator_set_voltage(priv->vregs[i].consumer, + old_uV[i], old_uV[i]); + return ret; +} + +static int qcom_snps_hsphy_enable_regulators(struct hsphy_priv *priv) +{ + int ret; + + ret = qcom_snps_hsphy_config_regulators(priv, 1); + if (ret) + return ret; + + ret = regulator_set_load(priv->vregs[VDDA_1P8].consumer, 19000); + if (ret < 0) + goto unconfig_regulators; + + ret = regulator_set_load(priv->vregs[VDDA_3P3].consumer, 16000); + if (ret < 0) + goto unset_1p8_load; + + ret = regulator_bulk_enable(VREG_NUM, priv->vregs); + if (ret) + goto unset_3p3_load; + + return 0; + +unset_3p3_load: + regulator_set_load(priv->vregs[VDDA_3P3].consumer, 0); +unset_1p8_load: + regulator_set_load(priv->vregs[VDDA_1P8].consumer, 0); +unconfig_regulators: + qcom_snps_hsphy_config_regulators(priv, 0); + return ret; +} + +static void qcom_snps_hsphy_disable_regulators(struct hsphy_priv *priv) +{ + regulator_bulk_disable(VREG_NUM, priv->vregs); + regulator_set_load(priv->vregs[VDDA_1P8].consumer, 0); + regulator_set_load(priv->vregs[VDDA_3P3].consumer, 0); + qcom_snps_hsphy_config_regulators(priv, 0); +} + +static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + + priv->mode = mode; + + return 0; +} + +static void qcom_snps_hsphy_enable_hv_interrupts(struct hsphy_priv *priv) +{ + u32 val; + + /* Clear any existing interrupts before enabling the interrupts */ + val = readb(priv->base + PHY_INTR_CLEAR0); + val |= DPDM_MASK; + writeb(val, priv->base + PHY_INTR_CLEAR0); + + writeb(0x0, priv->base + PHY_IRQ_CMD); + usleep_range(200, 220); + writeb(0x1, priv->base + PHY_IRQ_CMD); + + /* Make sure the interrupts are cleared */ + usleep_range(200, 220); + + val = readb(priv->base + PHY_INTR_MASK0); + switch (priv->mode) { + case PHY_MODE_USB_HOST_HS: + case PHY_MODE_USB_HOST_FS: + case PHY_MODE_USB_DEVICE_HS: + case PHY_MODE_USB_DEVICE_FS: + val |= DP_1_0 | DM_0_1; + break; + case PHY_MODE_USB_HOST_LS: + case PHY_MODE_USB_DEVICE_LS: + val |= DP_0_1 | DM_1_0; + break; + default: + /* No device connected */ + val |= DP_0_1 | DM_0_1; + break; + } + writeb(val, priv->base + PHY_INTR_MASK0); +} + +static void qcom_snps_hsphy_disable_hv_interrupts(struct hsphy_priv *priv) +{ + u32 val; + + val = readb(priv->base + PHY_INTR_MASK0); + val &= ~DPDM_MASK; + writeb(val, priv->base + PHY_INTR_MASK0); + + /* Clear any pending interrupts */ + val = readb(priv->base + PHY_INTR_CLEAR0); + val |= DPDM_MASK; + writeb(val, priv->base + PHY_INTR_CLEAR0); + + writeb(0x0, priv->base + PHY_IRQ_CMD); + usleep_range(200, 220); + + writeb(0x1, priv->base + PHY_IRQ_CMD); + usleep_range(200, 220); +} + +static void qcom_snps_hsphy_enter_retention(struct hsphy_priv *priv) +{ + u32 val; + + val = readb(priv->base + PHY_CTRL_COMMON0); + val |= SIDDQ; + writeb(val, priv->base + PHY_CTRL_COMMON0); +} + +static void qcom_snps_hsphy_exit_retention(struct hsphy_priv *priv) +{ + u32 val; + + val = readb(priv->base + PHY_CTRL_COMMON0); + val &= ~SIDDQ; + writeb(val, priv->base + PHY_CTRL_COMMON0); +} + +static int qcom_snps_hsphy_vbus_notifier(struct notifier_block *nb, + unsigned long event, void *ptr) +{ + struct hsphy_priv *priv = container_of(nb, struct hsphy_priv, + vbus_notify); + priv->cable_connected = !!event; + return 0; +} + +static int qcom_snps_hsphy_power_on(struct phy *phy) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + int ret; + + if (priv->cable_connected) { + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) + return ret; + qcom_snps_hsphy_disable_hv_interrupts(priv); + } else { + ret = qcom_snps_hsphy_enable_regulators(priv); + if (ret) + return ret; + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) + return ret; + qcom_snps_hsphy_exit_retention(priv); + } + + return 0; +} + +static int qcom_snps_hsphy_power_off(struct phy *phy) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + + if (priv->cable_connected) { + qcom_snps_hsphy_enable_hv_interrupts(priv); + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + } else { + qcom_snps_hsphy_enter_retention(priv); + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + qcom_snps_hsphy_disable_regulators(priv); + } + + return 0; +} + +static int qcom_snps_hsphy_reset(struct hsphy_priv *priv) +{ + int ret; + + ret = reset_control_assert(priv->phy_reset); + if (ret) + return ret; + + usleep_range(10, 15); + + ret = reset_control_deassert(priv->phy_reset); + if (ret) + return ret; + + usleep_range(80, 100); + + return 0; +} + +static void qcom_snps_hsphy_init_sequence(struct hsphy_priv *priv) +{ + const struct hsphy_data *data = priv->data; + const struct hsphy_init_seq *seq; + int i; + + /* Device match data is optional. */ + if (!data) + return; + + seq = data->init_seq; + + for (i = 0; i < data->init_seq_num; i++, seq++) { + writeb(seq->val, priv->base + seq->offset); + if (seq->delay) + usleep_range(seq->delay, seq->delay + 10); + } + + /* Ensure that the above parameter overrides is successful. */ + mb(); +} + +static int qcom_snps_hsphy_por_reset(struct hsphy_priv *priv) +{ + int ret; + + ret = reset_control_assert(priv->por_reset); + if (ret) + return ret; + + /* + * The Femto PHY is POR reset in the following scenarios. + * + * 1. After overriding the parameter registers. + * 2. Low power mode exit from PHY retention. + * + * Ensure that SIDDQ is cleared before bringing the PHY + * out of reset. + */ + qcom_snps_hsphy_exit_retention(priv); + + /* + * As per databook, 10 usec delay is required between + * PHY POR assert and de-assert. + */ + usleep_range(10, 20); + ret = reset_control_deassert(priv->por_reset); + if (ret) + return ret; + + /* + * As per databook, it takes 75 usec for PHY to stabilize + * after the reset. + */ + usleep_range(80, 100); + + /* Ensure that RESET operation is completed. */ + mb(); + + return 0; +} + +static int qcom_snps_hsphy_init(struct phy *phy) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + int state; + int ret; + + ret = qcom_snps_hsphy_reset(priv); + if (ret) + return ret; + + qcom_snps_hsphy_init_sequence(priv); + + ret = qcom_snps_hsphy_por_reset(priv); + if (ret) + return ret; + + /* Setup initial state */ + if (priv->vbus_edev) { + state = extcon_get_state(priv->vbus_edev, EXTCON_USB); + ret = qcom_snps_hsphy_vbus_notifier(&priv->vbus_notify, state, + priv->vbus_edev); + if (ret) + return ret; + } + + return 0; +} + +static const struct phy_ops qcom_snps_hsphy_ops = { + .init = qcom_snps_hsphy_init, + .power_on = qcom_snps_hsphy_power_on, + .power_off = qcom_snps_hsphy_power_off, + .set_mode = qcom_snps_hsphy_set_mode, + .owner = THIS_MODULE, +}; + +static const char * const qcom_snps_hsphy_clks[] = { + "ref", + "phy", + "sleep", +}; + +static int qcom_snps_hsphy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *extcon_node; + struct phy_provider *provider; + struct hsphy_priv *priv; + struct resource *res; + struct phy *phy; + int ret; + int i; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->base = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->num_clks = ARRAY_SIZE(qcom_snps_hsphy_clks); + priv->clks = devm_kcalloc(dev, priv->num_clks, sizeof(*priv->clks), + GFP_KERNEL); + if (!priv->clks) + return -ENOMEM; + + for (i = 0; i < priv->num_clks; i++) + priv->clks[i].id = qcom_snps_hsphy_clks[i]; + + ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks); + if (ret) + return ret; + + priv->phy_reset = devm_reset_control_get(dev, "phy"); + if (IS_ERR(priv->phy_reset)) + return PTR_ERR(priv->phy_reset); + + priv->por_reset = devm_reset_control_get(dev, "por"); + if (IS_ERR(priv->por_reset)) + return PTR_ERR(priv->por_reset); + + priv->vregs[VDD].supply = "vdd"; + priv->vregs[VDDA_1P8].supply = "vdda1p8"; + priv->vregs[VDDA_3P3].supply = "vdda3p3"; + + ret = devm_regulator_bulk_get(dev, VREG_NUM, priv->vregs); + if (ret) + return ret; + + priv->voltages[VDDA_1P8][VOL_NONE] = 0; + priv->voltages[VDDA_1P8][VOL_MIN] = 1800000; + priv->voltages[VDDA_1P8][VOL_MAX] = 1800000; + + priv->voltages[VDDA_3P3][VOL_NONE] = 0; + priv->voltages[VDDA_3P3][VOL_MIN] = 3050000; + priv->voltages[VDDA_3P3][VOL_MAX] = 3300000; + + ret = of_property_read_u32_array(dev->of_node, "qcom,vdd-voltage-level", + priv->voltages[VDD], VOL_NUM); + if (ret) { + dev_err(dev, "failed to read qcom,vdd-voltage-level\n"); + return ret; + } + + extcon_node = of_graph_get_remote_node(dev->of_node, -1, -1); + if (extcon_node) { + priv->vbus_edev = extcon_find_edev_by_node(extcon_node); + if (IS_ERR(priv->vbus_edev)) { + if (PTR_ERR(priv->vbus_edev) != -ENODEV) { + of_node_put(extcon_node); + return PTR_ERR(priv->vbus_edev); + } + priv->vbus_edev = NULL; + } + } + of_node_put(extcon_node); + + if (priv->vbus_edev) { + priv->vbus_notify.notifier_call = qcom_snps_hsphy_vbus_notifier; + ret = devm_extcon_register_notifier(dev, priv->vbus_edev, + EXTCON_USB, + &priv->vbus_notify); + if (ret) + return ret; + } + + /* Get device match data */ + priv->data = device_get_match_data(dev); + + phy = devm_phy_create(dev, dev->of_node, &qcom_snps_hsphy_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + phy_set_drvdata(phy, priv); + + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + return PTR_ERR_OR_ZERO(provider); +} + +/* + * The macro is used to define an initialization sequence. Each tuple + * is meant to program 'value' into phy register at 'offset' with 'delay' + * in us followed. + */ +#define HSPHY_INIT_CFG(o, v, d) { .offset = o, .val = v, .delay = d, } + +static const struct hsphy_init_seq init_seq_qcs404[] = { + HSPHY_INIT_CFG(0xc0, 0x01, 0), + HSPHY_INIT_CFG(0xe8, 0x0d, 0), + HSPHY_INIT_CFG(0x74, 0x12, 0), + HSPHY_INIT_CFG(0x98, 0x63, 0), + HSPHY_INIT_CFG(0x9c, 0x03, 0), + HSPHY_INIT_CFG(0xa0, 0x1d, 0), + HSPHY_INIT_CFG(0xa4, 0x03, 0), + HSPHY_INIT_CFG(0x8c, 0x23, 0), + HSPHY_INIT_CFG(0x78, 0x08, 0), + HSPHY_INIT_CFG(0x7c, 0xdc, 0), + HSPHY_INIT_CFG(0x90, 0xe0, 20), + HSPHY_INIT_CFG(0x74, 0x10, 0), + HSPHY_INIT_CFG(0x90, 0x60, 0), +}; + +static const struct hsphy_data hsphy_data_qcs404 = { + .init_seq = init_seq_qcs404, + .init_seq_num = ARRAY_SIZE(init_seq_qcs404), +}; + +static const struct of_device_id qcom_snps_hsphy_match[] = { + { .compatible = "qcom,qcs404-usb-hsphy", .data = &hsphy_data_qcs404, }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_match); + +static struct platform_driver qcom_snps_hsphy_driver = { + .probe = qcom_snps_hsphy_probe, + .driver = { + .name = "qcom-usb-snps-hsphy", + .of_match_table = qcom_snps_hsphy_match, + }, +}; +module_platform_driver(qcom_snps_hsphy_driver); + +MODULE_DESCRIPTION("Qualcomm Synopsys 28nm USB High-Speed PHY driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From c698c466a4c94397b560f162f57b9e7af5d3f8c9 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 1 Nov 2018 09:18:23 -0700 Subject: dt-bindings: Add Qualcomm USB Super-Speed PHY bindings Signed-off-by: Shawn Guo --- .../devicetree/bindings/usb/qcom,usb-ssphy.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt diff --git a/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt new file mode 100644 index 000000000000..ecf21dadf187 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt @@ -0,0 +1,39 @@ +Qualcomm Technologies, Inc. MSM PHY Transceivers + +Required properties: + +- compatible: Should be "qcom,usb-ssphy" +- reg: Address and length of the register set for the device +- clocks: a list of handles to the PHY clocks. Use as per + Documentation/devicetree/bindings/clock/clock-bindings.txt +- clock-names: Names of the clocks in 1-1 correspondence with the "clocks" + property. "ref_clk", "cfg_ahb_clk" and "pipe_clk" are mandatory. + +- -supply: phandle to the regulator device tree node + Required "supply-name" examples are: + "vdd" : vdd supply for SSPHY digital circuit operation + "vdda18" : 1.8v high-voltage analog supply for SSPHY + +- qcom,vdd-voltage-level: This property must be a list of three integer +values (no, min, max) where each value represents either a voltage in +microvolts or a value corresponding to voltage corner + +Optional properties: + +- qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to +the USB PHY and the controller must rely on external VBUS notification in +order to manually relay the notification to the SSPHY. + +Example: + +ssphy@f9200000 { + compatible = "qcom,usb-ssphy"; + reg = <0xf9200000 0xfc000>; + vdd-supply = <&pm8841_s2_corner>; + vdda18-supply = <&pm8941_l6>; + qcom,vdd-voltage-level = <1 5 7>; + clocks = <&clock_gcc USB_PHY_REF_CLK>, + <&clock_gcc USB_PHY_CFG_AHB_CLK>, + <&clock_gcc USB_PHY_PIPE_CLK>; + clock-names = "ref_clk", "cfg_ahb_clk", "pipe_clk"; +}; -- cgit v1.2.3 From 4f7c033b7ea1ac4fbc37b4a5aaf651d271759a31 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 1 Nov 2018 09:18:23 -0700 Subject: phy: qualcomm: Add USB Super-Speed PHY driver Signed-off-by: Shawn Guo --- drivers/phy/qualcomm/Kconfig | 11 ++ drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-usb-ss.c | 277 +++++++++++++++++++++++++++++++++ 3 files changed, 289 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-usb-ss.c diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index c7b5ee82895d..35a5a67eb468 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -92,3 +92,14 @@ config PHY_QCOM_USB_HS_SNPS_28NM Enable this to support the Synopsys 28nm Femto USB PHY on Qualcomm chips. This driver supports the high-speed PHY which is usually paired with either the ChipIdea or Synopsys DWC3 USB IPs on MSM SOCs. + +config PHY_QCOM_USB_SS + tristate "Qualcomm USB SS PHY driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in + select GENERIC_PHY + help + Enable this to support the Super-Speed USB transceiver on Qualcomm + chips. This driver supports the PHY which uses the QSCRATCH-based + register set for its control sequences, normally paired with newer + DWC3-based Super-Speed controllers on Qualcomm SoCs. diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index dc238d95b18c..71492612854b 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o obj-$(CONFIG_PHY_QCOM_USB_HS_SNPS_28NM) += phy-qcom-usb-hs-snsp-28nm.o +obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qualcomm/phy-qcom-usb-ss.c b/drivers/phy/qualcomm/phy-qcom-usb-ss.c new file mode 100644 index 000000000000..1cee5300ff71 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-usb-ss.c @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2012-2014,2017 The Linux Foundation. All rights reserved. + * Copyright (c) 2018, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* SSPHY control registers */ +#define SS_PHY_CTRL0 0x6C +#define SS_PHY_CTRL1 0x70 +#define SS_PHY_CTRL2 0x74 +#define SS_PHY_CTRL4 0x7C + +/* SS_PHY_CTRL_REG bits */ +#define REF_SS_PHY_EN BIT(0) +#define LANE0_PWR_PRESENT BIT(2) +#define SWI_PCS_CLK_SEL BIT(4) +#define TEST_POWERDOWN BIT(4) +#define SS_PHY_RESET BIT(7) + +enum ssphy_vdd_level { + LEVEL_NONE, + LEVEL_MIN, + LEVEL_MAX, + LEVEL_NUM, +}; + +struct ssphy_priv { + void __iomem *base; + struct clk_bulk_data *clks; + int num_clks; + struct reset_control *com_reset; + struct reset_control *phy_reset; + struct regulator *vdd; + struct regulator *vdda1p8; + unsigned int vdd_levels[LEVEL_NUM]; + struct regulator *vbus; +}; + +static void qcom_ssphy_write(void *base, u32 offset, u32 mask, u32 val) +{ + u32 tmp; + + tmp = readl(base + offset); + tmp &= ~mask; + tmp |= val; + writel(tmp, base + offset); +} + +static int qcom_ssphy_config_vdd(struct ssphy_priv *priv, int high) +{ + int min, ret; + + min = high ? 1 : 0; /* low or none? */ + ret = regulator_set_voltage(priv->vdd, priv->vdd_levels[min], + priv->vdd_levels[LEVEL_MAX]); + if (ret) + return ret; + + return 0; +} + +static int qcom_ssphy_ldo_enable(struct ssphy_priv *priv, int on) +{ + int ret = 0; + + if (!on) + goto disable_regulators; + + ret = regulator_set_load(priv->vdda1p8, 23000); + if (ret < 0) + return ret; + + ret = regulator_set_voltage(priv->vdda1p8, 1800000, 1800000); + if (ret) + goto put_vdda1p8_lpm; + + ret = regulator_enable(priv->vdda1p8); + if (ret) + goto unset_vdda1p8; + + return 0; + +disable_regulators: + regulator_disable(priv->vdda1p8); +unset_vdda1p8: + regulator_set_voltage(priv->vdda1p8, 0, 1800000); +put_vdda1p8_lpm: + regulator_set_load(priv->vdda1p8, 0); + return ret; +} + +static int qcom_ssphy_power_on(struct phy *phy) +{ + struct ssphy_priv *priv = phy_get_drvdata(phy); + int ret; + + /* Enable VBUS supply */ + if (priv->vbus) { + ret = regulator_enable(priv->vbus); + if (ret) + return ret; + } + + ret = qcom_ssphy_config_vdd(priv, 1); + if (ret) + return ret; + + ret = qcom_ssphy_ldo_enable(priv, 1); + if (ret) + return ret; + + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) + return ret; + + /* Use clk reset, if available; otherwise use SS_PHY_RESET bit */ + if (priv->com_reset) { + reset_control_assert(priv->com_reset); + reset_control_assert(priv->phy_reset); + udelay(10); + reset_control_deassert(priv->com_reset); + reset_control_deassert(priv->phy_reset); + } else { + qcom_ssphy_write(priv->base, SS_PHY_CTRL1, SS_PHY_RESET, + SS_PHY_RESET); + udelay(10); /* 10us required before de-asserting */ + qcom_ssphy_write(priv->base, SS_PHY_CTRL1, SS_PHY_RESET, 0); + } + + writeb_relaxed(SWI_PCS_CLK_SEL, priv->base + SS_PHY_CTRL0); + + qcom_ssphy_write(priv->base, SS_PHY_CTRL4, LANE0_PWR_PRESENT, + LANE0_PWR_PRESENT); + + writeb_relaxed(REF_SS_PHY_EN, priv->base + SS_PHY_CTRL2); + + qcom_ssphy_write(priv->base, SS_PHY_CTRL2, REF_SS_PHY_EN, REF_SS_PHY_EN); + qcom_ssphy_write(priv->base, SS_PHY_CTRL4, TEST_POWERDOWN, 0); + + return 0; +} + +static int qcom_ssphy_power_off(struct phy *phy) +{ + struct ssphy_priv *priv = phy_get_drvdata(phy); + + qcom_ssphy_write(priv->base, SS_PHY_CTRL2, REF_SS_PHY_EN, 0); + qcom_ssphy_write(priv->base, SS_PHY_CTRL4, TEST_POWERDOWN, + TEST_POWERDOWN); + + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + + qcom_ssphy_ldo_enable(priv, 0); + qcom_ssphy_config_vdd(priv, 0); + + /* Disable VBUS supply */ + if (priv->vbus) + regulator_disable(priv->vbus); + + return 0; +} + +static const struct phy_ops qcom_ssphy_ops = { + .power_on = qcom_ssphy_power_on, + .power_off = qcom_ssphy_power_off, + .owner = THIS_MODULE, +}; + +static const char * const qcom_ssphy_clks[] = { + "ref", + "phy", + "pipe", +}; + +static int qcom_ssphy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy_provider *provider; + struct ssphy_priv *priv; + struct resource *res; + struct phy *phy; + int ret; + int i; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->base = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->num_clks = ARRAY_SIZE(qcom_ssphy_clks); + priv->clks = devm_kcalloc(dev, priv->num_clks, sizeof(*priv->clks), + GFP_KERNEL); + if (!priv->clks) + return -ENOMEM; + + for (i = 0; i < priv->num_clks; i++) + priv->clks[i].id = qcom_ssphy_clks[i]; + + ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks); + if (ret) + return ret; + + priv->com_reset = devm_reset_control_get_optional(dev, "com"); + if (IS_ERR(priv->com_reset)) + return PTR_ERR(priv->com_reset); + + priv->phy_reset = devm_reset_control_get_optional(dev, "phy"); + if (IS_ERR(priv->phy_reset)) + return PTR_ERR(priv->phy_reset); + + priv->vdd = devm_regulator_get(dev, "vdd"); + if (IS_ERR(priv->vdd)) + return PTR_ERR(priv->vdd); + + priv->vdda1p8 = devm_regulator_get(dev, "vdda1p8"); + if (IS_ERR(priv->vdda1p8)) + return PTR_ERR(priv->vdda1p8); + + ret = of_property_read_u32_array(dev->of_node, "qcom,vdd-voltage-level", + priv->vdd_levels, + ARRAY_SIZE(priv->vdd_levels)); + if (ret) { + dev_err(dev, "failed to read qcom,vdd-voltage-level\n"); + return ret; + } + + priv->vbus = devm_regulator_get_optional(dev, "vbus"); + if (IS_ERR(priv->vbus)) { + if (PTR_ERR(priv->vbus) == -EPROBE_DEFER) + return PTR_ERR(priv->vbus); + priv->vbus = NULL; + } + + phy = devm_phy_create(dev, dev->of_node, &qcom_ssphy_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + phy_set_drvdata(phy, priv); + + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + return PTR_ERR_OR_ZERO(provider); +} + +static const struct of_device_id qcom_ssphy_match[] = { + { .compatible = "qcom,usb-ssphy", }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_ssphy_match); + +static struct platform_driver qcom_ssphy_driver = { + .probe = qcom_ssphy_probe, + .driver = { + .name = "qcom_usb_ssphy", + .of_match_table = qcom_ssphy_match, + }, +}; +module_platform_driver(qcom_ssphy_driver); + +MODULE_DESCRIPTION("Qualcomm Super-Speed USB PHY driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 0da848903323c31a1e3af80fa411a7da1c4516af Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 20 Nov 2018 13:31:32 +0800 Subject: dt-bindings: pinctrl: fix qcom-pmic-gpio for pms405 Rather than gpio1-gpio11 for pms405, there are 12 GPIOs for pms405. But gpio1, gpio9 and gpio10 are not available. Fix the bindings doc to make it correct for pms405. Fixes: ed80f6eb799a ("dt-bindings: pinctrl: qcom-pmic-gpio: Add pms405 support") Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt index ab4000eab07d..759aa1732e48 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt @@ -92,7 +92,7 @@ to specify in a pin configuration subnode: gpio1-gpio26 for pm8998 gpio1-gpio22 for pma8084 gpio1-gpio10 for pmi8994 - gpio1-gpio11 for pms405 + gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10) - function: Usage: required -- cgit v1.2.3 From 1b72e1027912edf291f78533a12689457deb34c5 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 20 Nov 2018 13:36:40 +0800 Subject: pinctrl: qcom: spmi-gpio: add compatible for pms405 GPIO Let's add "qcom,pms405-gpio" to match table, as commit ed80f6eb799a ("dt-bindings: pinctrl: qcom-pmic-gpio: Add pms405 support") already adds the compatible. Signed-off-by: Shawn Guo --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index a29efbe08f48..21ccf94b22ea 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1055,6 +1055,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ { .compatible = "qcom,pmi8994-gpio" }, /* 10 GPIO's */ { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */ + { .compatible = "qcom,pms405-gpio" }, /* 12 GPIO's, holes on 1 9 10 */ { .compatible = "qcom,spmi-gpio" }, /* Generic */ { }, }; -- cgit v1.2.3