From 40edc4cf5e6a2ab77c1658df4b277b01a2ba8916 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 25 Nov 2020 10:42:11 +0530 Subject: ARM: dts: qcom: Add SDX55 platform and MTP board support Add basic devicetree support for SDX55 platform and MTP board from Qualcomm. The SDX55 platform features an ARM Cortex A7 CPU which forms the Application Processor Sub System (APSS) along with standard Qualcomm peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem etc.. Currently, this basic devicetree support includes GCC, RPMh clock, INTC and Debug UART. Co-developed-by: Vinod Koul Signed-off-by: Vinod Koul Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/qcom-sdx55-mtp.dts | 27 +++++ arch/arm/boot/dts/qcom-sdx55.dtsi | 202 +++++++++++++++++++++++++++++++++++ 3 files changed, 231 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/qcom-sdx55-mtp.dts create mode 100644 arch/arm/boot/dts/qcom-sdx55.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 3d1ea0b25168..13a7cee00daf 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -927,7 +927,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8974-sony-xperia-amami.dtb \ qcom-msm8974-sony-xperia-castor.dtb \ qcom-msm8974-sony-xperia-honami.dtb \ - qcom-mdm9615-wp8548-mangoh-green.dtb + qcom-mdm9615-wp8548-mangoh-green.dtb \ + qcom-sdx55-mtp.dtb dtb-$(CONFIG_ARCH_RDA) += \ rda8810pl-orangepi-2g-iot.dtb \ rda8810pl-orangepi-i96.dtb diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts b/arch/arm/boot/dts/qcom-sdx55-mtp.dts new file mode 100644 index 000000000000..262660e6dd11 --- /dev/null +++ b/arch/arm/boot/dts/qcom-sdx55-mtp.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, Linaro Ltd. + */ + +/dts-v1/; + +#include "qcom-sdx55.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX55 MTP"; + compatible = "qcom,sdx55-mtp", "qcom,sdx55"; + qcom,board-id = <0x5010008 0x0>; + + aliases { + serial0 = &blsp1_uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_uart3 { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi new file mode 100644 index 000000000000..ca7d4e4f5d11 --- /dev/null +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SDX55 SoC device tree source + * + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, Linaro Ltd. + */ + +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>; + interrupt-parent = <&intc>; + + memory { + device_type = "memory"; + reg = <0 0>; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; + + pll_test_clk: pll-test-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sdx55"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "bi_tcxo", "sleep_clk", "core_bi_pll_test_se"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, <&pll_test_clk>; + }; + + blsp1_uart3: serial@831000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x00831000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + pdc: interrupt-controller@b210000 { + compatible = "qcom,sdx55-pdc", "qcom,pdc"; + reg = <0x0b210000 0x30000>; + qcom,pdc-ranges = <0 179 52>; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + intc: interrupt-controller@17800000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + reg = <0x17800000 0x1000>, + <0x17802000 0x1000>; + }; + + timer@17820000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17820000 0x1000>; + clock-frequency = <19200000>; + + frame@17821000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17821000 0x1000>, + <0x17822000 0x1000>; + }; + + frame@17823000 { + frame-number = <1>; + interrupts = ; + reg = <0x17823000 0x1000>; + status = "disabled"; + }; + + frame@17824000 { + frame-number = <2>; + interrupts = ; + reg = <0x17824000 0x1000>; + status = "disabled"; + }; + + frame@17825000 { + frame-number = <3>; + interrupts = ; + reg = <0x17825000 0x1000>; + status = "disabled"; + }; + + frame@17826000 { + frame-number = <4>; + interrupts = ; + reg = <0x17826000 0x1000>; + status = "disabled"; + }; + + frame@17827000 { + frame-number = <5>; + interrupts = ; + reg = <0x17827000 0x1000>; + status = "disabled"; + }; + + frame@17828000 { + frame-number = <6>; + interrupts = ; + reg = <0x17828000 0x1000>; + status = "disabled"; + }; + + frame@17829000 { + frame-number = <7>; + interrupts = ; + reg = <0x17829000 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17830000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x17830000 0x10000>, <0x17840000 0x10000>; + reg-names = "drv-0", "drv-1"; + interrupts = , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <1>; + qcom,tcs-config = , , + , ; + + rpmhcc: clock-controller { + compatible = "qcom,sdx55-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; +}; -- cgit v1.2.3 From cc1cd39990eb716650a31fba9e10462ce1d1b17a Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 22 Oct 2020 09:42:45 +0530 Subject: ARM: dts: qcom: sdx55: Add pincontrol node This adds pincontrol node to SDX55 dts. Signed-off-by: Vinod Koul --- arch/arm/boot/dts/qcom-sdx55.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index ca7d4e4f5d11..08b4a40338fa 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -96,6 +96,16 @@ interrupt-controller; }; + tlmm: pinctrl@f100000 { + compatible = "qcom,sdx55-pinctrl"; + reg = <0xf100000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + intc: interrupt-controller@17800000 { compatible = "qcom,msm-qgic2"; interrupt-controller; -- cgit v1.2.3 From e82490e3956f7e175e622c7d04a1afdce11dc019 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 22 Oct 2020 09:42:45 +0530 Subject: ARM: dts: qcom: sdx55: Add reserved memory nodes This adds reserved memory nodes to the SDX55 dtsi as defined by v8 of the memory map Signed-off-by: Vinod Koul --- arch/arm/boot/dts/qcom-sdx55.dtsi | 68 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 08b4a40338fa..1d6bc50f7d3d 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -60,6 +60,74 @@ method = "smc"; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + + mpss_debug_mem: memory@8ef00000 { + no-map; + reg = <0x8ef00000 0x800000>; + }; + + hyp_mem: memory@8fc00000 { + no-map; + reg = <0x8fc00000 0x80000>; + }; + + ac_db_mem: memory@8fc80000 { + no-map; + reg = <0x8fc80000 0x40000>; + }; + + secdata_mem: memory@8fcfd000 { + no-map; + reg = <0x8fcfd000 0x1000>; + }; + + ipa_fw_mem: memory@8fced000 { + no-map; + reg = <0x8fced000 0x10000>; + }; + + sbl_mem: memory@8fd00000 { + no-map; + reg = <0x8fd00000 0x100000>; + }; + + aop_image: memory@8fe00000 { + no-map; + reg = <0x8fe00000 0x20000>; + }; + + aop_cmd_db: memory@8fe20000 { + compatible = "qcom,cmd-db"; + reg = <0x8fe20000 0x20000>; + no-map; + }; + + smem_mem: memory@8fe40000 { + no-map; + reg = <0x8fe40000 0xc0000>; + }; + + tz_mem: memory@8ff00000 { + no-map; + reg = <0x8ff00000 0x100000>; + }; + + tz_apps_mem: memory@0x90000000 { + no-map; + reg = <0x90000000 0x500000>; + }; + + mpss_adsp_mem: memory@90800000 { + no-map; + reg = <0x90800000 0xf800000>; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 529a74ce1876d94b3816419fc8a8c3e8a557eb82 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 29 Oct 2020 14:18:14 +0530 Subject: dt-bindings: mmc: sdhci-msm: Document the SDX55 compatible The SDHCI controller on SDX55 is based on MSM SDHCI v5 IP. Hence, document the compatible with "qcom,sdhci-msm-v5" as the fallback. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt index 3b602fd6180b..31f4a5628595 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt @@ -21,6 +21,7 @@ Required properties: "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5" "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5" "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; + "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; NOTE that some old device tree files may be floating around that only have the string "qcom,sdhci-msm-v4" without the SoC compatible string but doing that should be considered a deprecated practice. -- cgit v1.2.3 From 2f45299f9d3f821c58ec9e901287ec5e42eaebaf Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 29 Oct 2020 14:26:42 +0530 Subject: ARM: dts: qcom: sdx55: Add support for SDHCI controller Add devicetree support for SDHCI controller found in Qualcomm SDX55 SoC. The SDHCI controller used in this SoC is based on the MSM SDHCI v5 IP. Hence, the support is added by reusing the existing sdhci driver with "qcom,sdhci-msm-v5" as the fallback. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 1d6bc50f7d3d..1f9a0d9b4190 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -155,6 +155,18 @@ status = "disabled"; }; + sdhc_1: sdhci@8804000 { + compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>; + clock-names = "iface", "core"; + status = "disabled"; + }; + pdc: interrupt-controller@b210000 { compatible = "qcom,sdx55-pdc", "qcom,pdc"; reg = <0x0b210000 0x30000>; -- cgit v1.2.3 From e54b8b489b6fd6b44a0118779743ca76d5b7b7cd Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 29 Oct 2020 14:28:58 +0530 Subject: ARM: dts: qcom: sdx55-mtp: Enable SDHCI controller Enable SDHCI controller on the Qualcomm SDX55 MTP board. TODO: Remove fixed regulators and source the actual regulators. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55-mtp.dts | 53 ++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts b/arch/arm/boot/dts/qcom-sdx55-mtp.dts index 262660e6dd11..3ed31f76c116 100644 --- a/arch/arm/boot/dts/qcom-sdx55-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx55-mtp.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include #include "qcom-sdx55.dtsi" / { @@ -20,8 +21,60 @@ chosen { stdout-path = "serial0:115200n8"; }; + + vreg_sd_vdd: sd-vdd { + compatible = "regulator-fixed"; + regulator-name = "vreg_sd_vdd"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + vreg_vddpx_2: vddpx-2 { + compatible = "regulator-fixed"; + regulator-name = "vreg_vddpx_2"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; }; &blsp1_uart3 { status = "ok"; }; + +&sdhc_1 { + pinctrl-names = "default"; + pinctrl-0 = <&sdc1_default_state &sdc1_card_det_n>; + vmmc-supply = <&vreg_sd_vdd>; + vqmmc-supply = <&vreg_vddpx_2>; + bus-width = <4>; + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; + status = "ok"; +}; + +&tlmm { + sdc1_default_state: sdc1-default { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc1_card_det_n: sd-card-det-n { + pins = "gpio99"; + function = "gpio"; + bias-pull-up; + }; +}; -- cgit v1.2.3 From 7e901016876a52bfab590cf1e3a0deec6e433c42 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 5 Nov 2020 11:10:03 -0800 Subject: ARM: dts: qcom: sdx55: Enable ARM SMMU Add a node for the ARM SMMU found in the SDX55. Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-sdx55.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 1f9a0d9b4190..5b7bf4b0bb4e 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -186,6 +186,30 @@ #interrupt-cells = <2>; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,sdx55-smmu-500", "arm,mmu-500"; + reg = <0x15000000 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + intc: interrupt-controller@17800000 { compatible = "qcom,msm-qgic2"; interrupt-controller; -- cgit v1.2.3 From 60ff26bed021e21f0643f70e2dfaa98c3b2f55c8 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 12 Nov 2020 13:59:39 +0530 Subject: ARM: dts: qcom: sdx55: Add support for TCSR Mutex Add TCSR Mutex node to support Qualcomm Hardware Mutex block on SDX55 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 5b7bf4b0bb4e..1a87d6282e02 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -167,6 +167,17 @@ status = "disabled"; }; + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + pdc: interrupt-controller@b210000 { compatible = "qcom,sdx55-pdc", "qcom,pdc"; reg = <0x0b210000 0x30000>; -- cgit v1.2.3 From ca13b443d30d903d20103fa2fd3167557d08f3eb Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 12 Nov 2020 14:03:31 +0530 Subject: ARM: dts: qcom: sdx55: Add Shared memory manager support Add smem node to support shared memory manager on SDX55 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 1a87d6282e02..0aa30bebc7c7 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -178,6 +178,12 @@ #hwlock-cells = <1>; }; + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + pdc: interrupt-controller@b210000 { compatible = "qcom,sdx55-pdc", "qcom,pdc"; reg = <0x0b210000 0x30000>; -- cgit v1.2.3 From c0b87a7fe9eb87a0a1f74b7cf040f54a88b6510f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 12 Nov 2020 14:11:16 +0530 Subject: ARM: dts: qcom: sdx55: Add QPIC BAM support Add qpic_bam node to support QPIC BAM DMA controller on SDX55 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 0aa30bebc7c7..7947788c5bd3 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -167,6 +167,18 @@ status = "disabled"; }; + qpic_bam: dma@1b04000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x01b04000 0x1c000>; + interrupts = ; + clocks = <&rpmhcc RPMH_QPIC_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + status = "disabled"; + }; + tcsr_mutex_block: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x20000>; -- cgit v1.2.3 From 15d6aa24f8cb32fc0b1df5670a80c8472c8781c0 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 12 Nov 2020 14:27:44 +0530 Subject: ARM: dts: qcom: sdx55: Add QPIC NAND support Add qpic_nand node to support QPIC NAND controller on SDX55 SoC. FIXME: Remove the fixed clock and source real clock. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 7947788c5bd3..c15277d2d73c 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -41,6 +41,12 @@ #clock-cells = <0>; clock-frequency = <400000000>; }; + + nand_clk_dummy: nand-clk-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; }; cpus { @@ -179,6 +185,22 @@ status = "disabled"; }; + qpic_nand: nand@1b30000 { + compatible = "qcom,sdx55-nand"; + reg = <0x01b30000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rpmhcc RPMH_QPIC_CLK>, + <&nand_clk_dummy>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + status = "disabled"; + }; + tcsr_mutex_block: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x20000>; -- cgit v1.2.3 From ee1b1e24be6af08965f81655759495dec4523feb Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 12 Nov 2020 14:36:09 +0530 Subject: ARM: dts: qcom: sdx55-mtp: Enable BAM DMA Enable BAM DMA on SDX55-MTP board. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55-mtp.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts b/arch/arm/boot/dts/qcom-sdx55-mtp.dts index 3ed31f76c116..3be3e1cad2cf 100644 --- a/arch/arm/boot/dts/qcom-sdx55-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx55-mtp.dts @@ -41,6 +41,10 @@ status = "ok"; }; +&qpic_bam { + status = "ok"; +}; + &sdhc_1 { pinctrl-names = "default"; pinctrl-0 = <&sdc1_default_state &sdc1_card_det_n>; -- cgit v1.2.3 From 2c5a5e140dba21318407e6943cd3e172b8fd282a Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 12 Nov 2020 14:37:25 +0530 Subject: ARM: dts: qcom: sdx55-mtp: Enable QPIC NAND Enable QPIC NAND on SDX55-MTP board. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55-mtp.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts b/arch/arm/boot/dts/qcom-sdx55-mtp.dts index 3be3e1cad2cf..436707b8e259 100644 --- a/arch/arm/boot/dts/qcom-sdx55-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx55-mtp.dts @@ -45,6 +45,18 @@ status = "ok"; }; +&qpic_nand { + status = "ok"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + }; +}; + &sdhc_1 { pinctrl-names = "default"; pinctrl-0 = <&sdc1_default_state &sdc1_card_det_n>; -- cgit v1.2.3 From 4a99c9f537c52eddd343941e95a54e27c79be299 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 22 Oct 2020 09:42:45 +0530 Subject: ARM: dts: qcom: sdx55: Add spmi node This adds SPMI node to SDX55 dts. Signed-off-by: Vinod Koul --- arch/arm/boot/dts/qcom-sdx55.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index c15277d2d73c..9d06b7f78c37 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -227,6 +227,25 @@ interrupt-controller; }; + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0c440000 0x0000d00>, + <0x0c600000 0x2000000>, + <0x0e600000 0x0100000>, + <0x0e700000 0x00a0000>, + <0x0c40a000 0x0000700>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,sdx55-pinctrl"; reg = <0xf100000 0x300000>; -- cgit v1.2.3 From d711c602b9e44e4dc5e14103aacfa5bdbfc44b30 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 23 Nov 2020 12:47:31 +0530 Subject: ARM: dts: qcom: sdx55-mtp: Add pm8150b pmic SDX55-mtp features PM8150B pmic, so include the dts as well Signed-off-by: Vinod Koul --- arch/arm/boot/dts/qcom-sdx55-mtp.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts b/arch/arm/boot/dts/qcom-sdx55-mtp.dts index 436707b8e259..90d587225ce8 100644 --- a/arch/arm/boot/dts/qcom-sdx55-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx55-mtp.dts @@ -8,6 +8,7 @@ #include #include "qcom-sdx55.dtsi" +#include / { model = "Qualcomm Technologies, Inc. SDX55 MTP"; -- cgit v1.2.3 From de2fb039a4776896feeeeb2bc4c19e1ddebee5c4 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 23 Nov 2020 12:47:31 +0530 Subject: ARM: dts: qcom: sdx55-mtp: Add pmx55 pmic SDX55-mtp features PMX55 pmic, so include the dts as well Signed-off-by: Vinod Koul --- arch/arm/boot/dts/qcom-sdx55-mtp.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts b/arch/arm/boot/dts/qcom-sdx55-mtp.dts index 90d587225ce8..b1fd239b66c4 100644 --- a/arch/arm/boot/dts/qcom-sdx55-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx55-mtp.dts @@ -9,6 +9,7 @@ #include #include "qcom-sdx55.dtsi" #include +#include "qcom-pmx55.dtsi" / { model = "Qualcomm Technologies, Inc. SDX55 MTP"; -- cgit v1.2.3 From 38ffb85225cc4ce7712154e089ef94e0b05526bc Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 22 Oct 2020 09:42:45 +0530 Subject: ARM: dts: qcom: sdx55: Add rpmpd node This adds rpmpd node and opps for this node to the SDX55 dts. Signed-off-by: Vinod Koul --- arch/arm/boot/dts/qcom-sdx55.dtsi | 51 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 9d06b7f78c37..4e27a458ec0b 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include / { @@ -372,6 +373,56 @@ clock-names = "xo"; clocks = <&xo_board>; }; + + rpmhpd: power-controller { + compatible = "qcom,sdx55-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; }; }; -- cgit v1.2.3 From c3a5f3b4710034c9826a6741faf06586c83f0822 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 23 Nov 2020 12:44:59 +0530 Subject: ARM: dts: qcom: Add PMIC pmx55 dts This adds DTS for PMIC PMX55 found in Qualcomm platforms. Signed-off-by: Vinod Koul --- arch/arm/boot/dts/qcom-pmx55.dtsi | 92 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-pmx55.dtsi diff --git a/arch/arm/boot/dts/qcom-pmx55.dtsi b/arch/arm/boot/dts/qcom-pmx55.dtsi new file mode 100644 index 000000000000..aa063cc6379f --- /dev/null +++ b/arch/arm/boot/dts/qcom-pmx55.dtsi @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, Linaro Limited + */ + +#include +#include +#include + +&spmi_bus { + pmic@8 { + compatible = "qcom,pmx55", "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + power-on@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x0800>; + + status = "disabled"; + }; + + pmx55_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmx55_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pmx55_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + die-temp@6 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "die_temp"; + }; + + chg-temp@9 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "chg_temp"; + }; + }; + + pmx55_gpios: gpio@c000 { + compatible = "qcom,pmx55-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0x8 0xc0 0x0 IRQ_TYPE_NONE>, + <0x8 0xc1 0x0 IRQ_TYPE_NONE>, + <0x8 0xc3 0x0 IRQ_TYPE_NONE>, + <0x8 0xc4 0x0 IRQ_TYPE_NONE>, + <0x8 0xc5 0x0 IRQ_TYPE_NONE>, + <0x8 0xc7 0x0 IRQ_TYPE_NONE>, + <0x8 0xc8 0x0 IRQ_TYPE_NONE>; + }; + }; + + + pmic@9 { + compatible = "qcom,pmx55", "qcom,spmi-pmic"; + reg = <0x9 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; -- cgit v1.2.3 From 49a3da37b9100d4956bcff0bd0bf88c9339d7c30 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 26 Nov 2020 14:38:50 +0530 Subject: ARM: dts: qcom: sdx55-mtp: Add regulator nodes This adds the regulators found on SDX55 MTP. Signed-off-by: Vinod Koul --- arch/arm/boot/dts/qcom-sdx55-mtp.dts | 178 ++++++++++++++++++++++++++++++++++- 1 file changed, 176 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts b/arch/arm/boot/dts/qcom-sdx55-mtp.dts index b1fd239b66c4..b3f4932a9ef3 100644 --- a/arch/arm/boot/dts/qcom-sdx55-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx55-mtp.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include "qcom-sdx55.dtsi" #include #include "qcom-pmx55.dtsi" @@ -24,18 +25,191 @@ stdout-path = "serial0:115200n8"; }; + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_bob_3p3: pmx55-bob { + compatible = "regulator-fixed"; + regulator-name = "vreg_bob_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + vreg_s7e_mx_0p752: pmx55-s7e { + compatible = "regulator-fixed"; + regulator-name = "vreg_s7e_mx_0p752"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + + vin-supply = <&vph_pwr>; + }; + vreg_sd_vdd: sd-vdd { compatible = "regulator-fixed"; regulator-name = "vreg_sd_vdd"; regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; + + vin-supply = <&vreg_vddpx_2>; }; vreg_vddpx_2: vddpx-2 { - compatible = "regulator-fixed"; + compatible = "regulator-gpio"; regulator-name = "vreg_vddpx_2"; - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2850000>; + enable-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + states = <1800000 0>, <2850000 1>; + startup-delay-us = <200000>; + enable-active-high; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; +}; + +&apps_rsc { + pmx55-rpmh-regulators { + compatible = "qcom,pmx55-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-l1-l2-supply = <&vreg_s2e_1p224>; + vdd-l3-l9-supply = <&vreg_s3e_0p824>; + vdd-l4-l12-supply = <&vreg_s4e_1p904>; + vdd-l5-l6-supply = <&vreg_s4e_1p904>; + vdd-l7-l8-supply = <&vreg_s3e_0p824>; + vdd-l10-l11-l13-supply = <&vreg_bob_3p3>; + vdd-l14-supply = <&vreg_s7e_mx_0p752>; + vdd-l15-supply = <&vreg_s2e_1p224>; + vdd-l16-supply = <&vreg_s4e_1p904>; + + vreg_s2e_1p224: smps2 { + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <1400000>; + }; + + vreg_s3e_0p824: smps3 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_s4e_1p904: smps4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1960000>; + }; + + ldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo2 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = ; + }; + + ldo3 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + ldo4 { + regulator-min-microvolt = <872000>; + regulator-max-microvolt = <872000>; + regulator-initial-mode = ; + }; + + ldo5 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + ldo7 { + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <900000>; + regulator-initial-mode = ; + }; + + ldo8 { + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <900000>; + regulator-initial-mode = ; + }; + + ldo9 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + ldo10 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + ldo11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + ldo12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo13 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + ldo14 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + ldo15 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + ldo16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = ; + }; }; }; -- cgit v1.2.3 From fe53d246d489b58a0eb26ff9650d51b8432d5b3c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 3 Dec 2020 18:14:18 +0530 Subject: ARM: dts: qcom: sdx55: Add USB3 and PHY support Add devicetree nodes for enabling USB3 controller, Qcom QMP PHY and SNPS HS PHY on SDX55. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 86 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 4e27a458ec0b..5fc4dfb951c5 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -162,6 +162,47 @@ status = "disabled"; }; + usb_hsphy: phy@ff4000 { + compatible = "qcom,usb-snps-hs-7nm-phy"; + reg = <0xff4000 0x114>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_BCR>; + }; + + usb_qmpphy: phy@ff6000 { + compatible = "qcom,sdx55-qmp-usb3-uni-phy"; + reg = <0xff6000 0x1c0>; + status = "disabled"; + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "aux", "cfg_ahb", "ref"; + + resets = <&gcc GCC_USB3PHY_PHY_BCR>, + <&gcc GCC_USB3_PHY_BCR>; + reset-names = "phy", "common"; + + usb_ssphy: lane@ff6200 { + reg = <0x00ff6200 0x170>, + <0x00ff6400 0x200>, + <0x00ff6800 0x800>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + }; + }; + sdhc_1: sdhci@8804000 { compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>; @@ -219,6 +260,51 @@ hwlocks = <&tcsr_mutex 3>; }; + usb: usb@a6f8800 { + compatible = "qcom,sdx55-dwc3", "qcom,dwc3"; + reg = <0xa6f8800 0x400>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, + <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_USB30_MSTR_AXI_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep", "xo"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_GDSC>; + + resets = <&gcc GCC_USB30_BCR>; + + usb_dwc3: dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0x0a600000 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x1a0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_hsphy>, <&usb_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + pdc: interrupt-controller@b210000 { compatible = "qcom,sdx55-pdc", "qcom,pdc"; reg = <0x0b210000 0x30000>; -- cgit v1.2.3 From 0a97c46631e8071db8083f98c9d248c05f603e2c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 3 Dec 2020 18:15:40 +0530 Subject: ARM: dts: qcom: sdx55-mtp: Enable USB3 and PHY support Enable the support for USB3 controller, QMP PHY and HS PHY on SDX55 MTP. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55-mtp.dts | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts b/arch/arm/boot/dts/qcom-sdx55-mtp.dts index b3f4932a9ef3..33f9c3f11bb4 100644 --- a/arch/arm/boot/dts/qcom-sdx55-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx55-mtp.dts @@ -115,7 +115,7 @@ regulator-max-microvolt = <1960000>; }; - ldo1 { + vreg_l1e_bb_1p2: ldo1 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = ; @@ -133,13 +133,13 @@ regulator-initial-mode = ; }; - ldo4 { + vreg_l4e_bb_0p875: ldo4 { regulator-min-microvolt = <872000>; regulator-max-microvolt = <872000>; regulator-initial-mode = ; }; - ldo5 { + vreg_l5e_bb_1p7: ldo5 { regulator-min-microvolt = <1704000>; regulator-max-microvolt = <1900000>; regulator-initial-mode = ; @@ -169,7 +169,7 @@ regulator-initial-mode = ; }; - ldo10 { + vreg_l10e_3p1: ldo10 { regulator-min-microvolt = <3088000>; regulator-max-microvolt = <3088000>; regulator-initial-mode = ; @@ -270,3 +270,24 @@ bias-pull-up; }; }; + +&usb_hsphy { + status = "okay"; + vdda-pll-supply = <&vreg_l4e_bb_0p875>; + vdda33-supply = <&vreg_l10e_3p1>; + vdda18-supply = <&vreg_l5e_bb_1p7>; +}; + +&usb_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l4e_bb_0p875>; + vdda-pll-supply = <&vreg_l1e_bb_1p2>; +}; + +&usb { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "peripheral"; +}; -- cgit v1.2.3 From 5ae8cfa93624a80da28770875ac146d4ce01974f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 4 Dec 2020 13:56:12 +0530 Subject: ARM: dts: qcom: sdx55: Add Watchdog support Enable Watchdog support for Application Processor Subsystem (APSS) block on SDX55 platform. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 5fc4dfb951c5..22e341227e53 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -376,6 +376,12 @@ <0x17802000 0x1000>; }; + watchdog@17817000 { + compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt"; + reg = <0x17817000 0x1000>; + clocks = <&sleep_clk>; + }; + timer@17820000 { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From c1efc7912855eec09dfb76b5a92d311666b68042 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 7 Dec 2020 10:38:51 +0530 Subject: ARM: dts: qcom: sdx55: Add pshold support Add support for pshold block to drive pshold towards the PMIC, which is used to trigger a configurable event such as reboot or poweroff of the SDX55 platform. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 22e341227e53..404595a742d9 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -314,6 +314,11 @@ interrupt-controller; }; + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0x0c264000 0x1000>; + }; + spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0c440000 0x0000d00>, -- cgit v1.2.3 From 36fedd832d4171997cda1783fcef1c79a3692ecc Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 18 Dec 2020 19:14:31 +0530 Subject: ARM: dts: qcom: sdx55: Add support for A7 PLL clock On SDX55 there is a separate A7 PLL which is used to provide high frequency clock to the Cortex A7 CPU via a MUX. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 404595a742d9..d11ca6cbf635 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -381,6 +381,14 @@ <0x17802000 0x1000>; }; + a7pll: clock@17808000 { + compatible = "qcom,sdx55-a7pll"; + reg = <0x17808000 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <0>; + }; + watchdog@17817000 { compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt"; reg = <0x17817000 0x1000>; -- cgit v1.2.3 From 65a72a4c356ddfc74594b61c5463d7b6a6cf7cf6 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 18 Dec 2020 19:56:06 +0530 Subject: ARM: dts: qcom: sdx55: Add support for APCS block The APCS block on SDX55 acts as a mailbox controller and also provides clock output for the Cortex A7 CPU. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index d11ca6cbf635..c94a18739182 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -389,6 +389,15 @@ #clock-cells = <0>; }; + apcs: mailbox@17810000 { + compatible = "qcom,sdx55-apcs-gcc", "syscon"; + reg = <0x17810000 0x2000>; + #mbox-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; + clock-names = "ref", "pll", "aux"; + #clock-cells = <0>; + }; + watchdog@17817000 { compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt"; reg = <0x17817000 0x1000>; -- cgit v1.2.3 From 0f53c7367dc52fff77c915da41dee0ca6a52c8aa Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 18 Dec 2020 19:59:49 +0530 Subject: ARM: dts: qcom: sdx55: Add CPUFreq support Add CPUFreq support to SDX55 platform using the cpufreq-dt driver. There is no dedicated hardware block available on this platform to carry on the CPUFreq duties. Hence, it is accomplished using the CPU clock and regulators tied together by the operating points table. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index c94a18739182..a1ae23d8cc05 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -59,6 +59,35 @@ compatible = "arm,cortex-a7"; reg = <0x0>; enable-method = "psci"; + clocks = <&apcs>; + power-domains = <&rpmhpd SDX55_CX>; + power-domain-names = "rpmhpd"; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + cpu_opp_table: cpu-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-345600000 { + opp-hz = /bits/ 64 <345600000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + required-opps = <&rpmhpd_opp_turbo>; }; }; -- cgit v1.2.3 From 250a0538f33d4e10995396624c4a462c585d97d6 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 30 Dec 2020 12:26:36 +0530 Subject: ARM: dts: qcom: sdx55: Add modem SMP2P node Add SMP2P nodes for the SDX55 platform to communicate with the modem. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index a1ae23d8cc05..6035478220a8 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -164,6 +164,37 @@ }; }; + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + mboxes = <&apcs 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From a714ac43da761a890b8b93566939365c040c2442 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 30 Dec 2020 12:33:23 +0530 Subject: ARM: dts: qcom: sdx55: Add Modem remoteproc node Add modem support to SDX55 using the PAS remoteproc driver. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 6035478220a8..65845ce92483 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -320,6 +320,39 @@ hwlocks = <&tcsr_mutex 3>; }; + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sdx55-mpss-pas"; + reg = <0x04080000 0x4040>; + + interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SDX55_CX>, + <&rpmhpd SDX55_MSS>; + power-domain-names = "cx", "mss"; + + memory-region = <&mpss_adsp_mem>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = ; + label = "mpss"; + qcom,remote-pid = <1>; + mboxes = <&apcs 15>; + }; + }; + usb: usb@a6f8800 { compatible = "qcom,sdx55-dwc3", "qcom,dwc3"; reg = <0xa6f8800 0x400>; -- cgit v1.2.3 From c71627a62e10989d99fe179373dee4c3b1501bab Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 30 Dec 2020 12:39:59 +0530 Subject: ARM: dts: qcom: sdx55: Add IMEM and PIL info region Add a simple-mfd representing IMEM on SDX55 and define the PIL relocation info region, so that post mortem tools will be able to locate the loaded remoteproc. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 65845ce92483..415aeb0f6294 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -441,6 +441,21 @@ #interrupt-cells = <2>; }; + imem@1468f000 { + compatible = "simple-mfd"; + reg = <0x1468f000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x1468f000 0x1000>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0x200>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sdx55-smmu-500", "arm,mmu-500"; reg = <0x15000000 0x20000>; -- cgit v1.2.3 From 05d5b2e17f79624edcc0edfb785d6920bcb4e97f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 30 Dec 2020 11:20:05 +0530 Subject: TEMP: Modify Modem memory based on the trustzone version used in the MTP Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 415aeb0f6294..ca98615966e8 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -158,9 +158,9 @@ reg = <0x90000000 0x500000>; }; - mpss_adsp_mem: memory@90800000 { + mpss_adsp_mem: memory@90c00000 { no-map; - reg = <0x90800000 0xf800000>; + reg = <0x90c00000 0xd400000>; }; }; -- cgit v1.2.3 From d8cf29a9f2867bd7a89558e2c9ce7a22eec4ac29 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 30 Dec 2020 13:03:19 +0530 Subject: ARM: dts: qcom: sdx55: Add SCM node Add SCM node to enable SCM functionality on SDX55 platform. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index ca98615966e8..149c25159cbe 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -91,6 +91,12 @@ }; }; + firmware { + scm { + compatible = "qcom,scm-sdx55", "qcom,scm"; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; -- cgit v1.2.3