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Diffstat (limited to 'arch/arm64/boot/dts/qcom/qcs404.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/qcs404.dtsi233
1 files changed, 233 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index f5f0c4c9cb16..c835cc6a8d77 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -42,6 +42,9 @@
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&pms405_s3>;
};
CPU1: cpu@101 {
@@ -52,6 +55,9 @@
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&pms405_s3>;
};
CPU2: cpu@102 {
@@ -62,6 +68,9 @@
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&pms405_s3>;
};
CPU3: cpu@103 {
@@ -72,6 +81,9 @@
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
+ clocks = <&apcs_glb>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&pms405_s3>;
};
L2_0: l2-cache {
@@ -94,6 +106,24 @@
};
};
+ cpu_opp_table: cpu_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ opp-microvolt = <1224000 1224000 1224000>;
+ };
+ opp-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <1288000 1288000 1288000>;
+ };
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ opp-microvolt = <1352000 1352000 1352000>;
+ };
+ };
+
firmware {
scm: scm {
compatible = "qcom,scm-qcs404", "qcom,scm";
@@ -376,6 +406,169 @@
mboxes = <&apcs_glb 12>;
label = "cdsp";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "cdsp";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,msm_fastrpc_compute_cb_1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+ };
+
+ qcom,msm_fastrpc_compute_cb_2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+ };
+
+ qcom,msm_fastrpc_compute_cb_3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ };
+
+ qcom,msm_fastrpc_compute_cb_4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ };
+
+ qcom,msm_fastrpc_compute_cb_5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ };
+ };
+ };
+ };
+
+ usb3_phy: phy@78000 {
+ compatible = "qcom,usb-ssphy";
+ reg = <0x78000 0x400>;
+ #phy-cells = <0>;
+ clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+ <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "ref", "phy", "pipe";
+ resets = <&gcc GCC_USB3_PHY_BCR>,
+ <&gcc GCC_USB3PHY_PHY_BCR>;
+ reset-names = "com", "phy";
+ status = "disabled";
+ };
+
+ usb2_phy_prim: phy@7a000 {
+ compatible = "qcom,qcs404-usb-hsphy";
+ reg = <0x7a000 0x200>;
+ #phy-cells = <0>;
+ clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+ <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+ clock-names = "ref", "phy", "sleep";
+ resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
+ <&gcc GCC_USB2A_PHY_BCR>;
+ reset-names = "phy", "por";
+ qcom,init-seq = <0xc0 0x01 0>,
+ <0xe8 0x0d 0>,
+ <0x74 0x12 0>,
+ <0x98 0x63 0>,
+ <0x9c 0x03 0>,
+ <0xa0 0x1d 0>,
+ <0xa4 0x03 0>,
+ <0x8c 0x23 0>,
+ <0x78 0x08 0>,
+ <0x7c 0xdc 0>,
+ <0x90 0xe0 20>,
+ <0x74 0x10 0>,
+ <0x90 0x60 0>;
+ status = "disabled";
+ };
+
+ usb2_phy_sec: phy@7c000 {
+ compatible = "qcom,qcs404-usb-hsphy";
+ reg = <0x7c000 0x200>;
+ #phy-cells = <0>;
+ clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+ <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+ clock-names = "ref", "phy", "sleep";
+ resets = <&gcc GCC_QUSB2_PHY_BCR>,
+ <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
+ reset-names = "phy", "por";
+ qcom,init-seq = <0xc0 0x01 0>,
+ <0xe8 0x0d 0>,
+ <0x74 0x12 0>,
+ <0x98 0x63 0>,
+ <0x9c 0x03 0>,
+ <0xa0 0x1d 0>,
+ <0xa4 0x03 0>,
+ <0x8c 0x23 0>,
+ <0x78 0x08 0>,
+ <0x7c 0xdc 0>,
+ <0x90 0xe0 20>,
+ <0x74 0x10 0>,
+ <0x90 0x60 0>;
+ status = "disabled";
+ };
+
+ usb3: usb@7678800 {
+ compatible = "qcom,dwc3";
+ reg = <0x07678800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&gcc GCC_USB30_MASTER_CLK>,
+ <&gcc GCC_SYS_NOC_USB3_CLK>,
+ <&gcc GCC_USB30_SLEEP_CLK>,
+ <&gcc GCC_USB30_MOCK_UTMI_CLK>;
+ clock-names = "core", "iface", "sleep", "mock_utmi";
+ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+ status = "disabled";
+
+ dwc3@7580000 {
+ compatible = "snps,dwc3";
+ reg = <0x07580000 0xcd00>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_phy_sec>, <&usb3_phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,usb3_lpm_capable;
+ dr_mode = "otg";
+ };
+ };
+
+ usb2: usb@79b8800 {
+ compatible = "qcom,dwc3";
+ reg = <0x079b8800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
+ <&gcc GCC_PCNOC_USB2_CLK>,
+ <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
+ <&gcc GCC_USB20_MOCK_UTMI_CLK>;
+ clock-names = "core", "iface", "sleep", "mock_utmi";
+ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB_HS_SYSTEM_CLK>;
+ assigned-clock-rates = <19200000>, <133333333>;
+ status = "disabled";
+
+ dwc3@78c0000 {
+ compatible = "snps,dwc3";
+ reg = <0x078c0000 0xcc00>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_phy_prim>;
+ phy-names = "usb2-phy";
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,usb3_lpm_capable;
+ dr_mode = "peripheral";
};
};
@@ -902,6 +1095,18 @@
compatible = "qcom,qcs404-apcs-apps-global", "syscon";
reg = <0x0b011000 0x1000>;
#mbox-cells = <1>;
+ clocks = <&gcc GCC_GPLL0_AO_OUT_MAIN>, <&apcs_hfpll>;
+ clock-names = "aux", "pll";
+ #clock-cells = <0>;
+ };
+
+ apcs_hfpll: clock-controller@0b016000 {
+ compatible = "qcom,hfpll";
+ reg = <0x0b016000 0x30>;
+ #clock-cells = <0>;
+ clock-output-names = "apcs_hfpll";
+ clocks = <&xo_board>;
+ clock-names = "xo";
};
watchdog@b017000 {
@@ -998,6 +1203,34 @@
mboxes = <&apcs_glb 8>;
label = "adsp";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "adsp";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,msm_fastrpc_compute_cb_1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ };
+
+ qcom,msm_fastrpc_compute_cb_2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ };
+
+ qcom,msm_fastrpc_compute_cb_3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ shared-cb = <5>;
+ };
+ };
};
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-18 23:06:27 +0000