diff options
| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-03-08 18:34:21 +0100 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-03-08 19:36:30 +0100 |
| commit | 028c6e749fd890e68e710ca1d6d941dc5a77b8c5 (patch) | |
| tree | f85d0f9ce84b960db3be920e4697579aca82e689 | |
| parent | da3962ed3debe5b652ccb77b47674fbb56613169 (diff) | |
arm64: dts: qcom: sm8450-hdk: align WCD9385 reset pin with downstream config
Downstream DTS uses 16 mA drive strength for the WCD9385 audio codec
RESET_N reset pin. It also pulls the pin down in shutdown mode, thus it
is more like a shutdown pin, not a reset. Use the same settings here
for HDK8450 and keep the WCD9385 by default in powered off (so pin as
low). Align the name of pin configuration node with other pins in the
DTS.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index d6b0974ed85b..d86712bd96e5 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -870,9 +870,11 @@ output-low; }; - wcd_default: wcd-default-state { + wcd_default: wcd-reset-n-active-state { pins = "gpio43"; function = "gpio"; + drive-strength = <16>; bias-disable; + output-low; }; }; |