diff options
author | Linaro CI <ci_notify@linaro.org> | 2022-09-22 11:25:25 +0000 |
---|---|---|
committer | Linaro CI <ci_notify@linaro.org> | 2022-09-22 11:25:25 +0000 |
commit | 7c7514482c4a718e38cb9657f2b56eeee92f3e70 (patch) | |
tree | e7a991ddaeb352cbda4b3e45f9d1e4db5053a257 | |
parent | 04d26096aaaea786215dcc682fe7ffac88e01729 (diff) | |
parent | c7f77af79d4f6ebb5a75339c990a37818c7b1690 (diff) |
Merge remote-tracking branch 'sm8250/tracking-qcomlt-sm8250' into integration-linux-qcomlt
-rw-r--r-- | arch/arm64/boot/dts/qcom/Makefile | 2 | ||||
-rw-r--r-- | arch/arm64/boot/dts/qcom/qrb5165-rb5-dual-dsi.dts | 46 | ||||
-rw-r--r-- | arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 5 | ||||
-rw-r--r-- | arch/arm64/boot/dts/qcom/sm8250-rb5-dvt.dts | 18 | ||||
-rw-r--r-- | arch/arm64/boot/dts/qcom/sm8250.dtsi | 52 | ||||
-rw-r--r-- | drivers/gpu/drm/bridge/lontium-lt9611uxc.c | 80 | ||||
-rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 15 | ||||
-rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 14 | ||||
-rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 16 | ||||
-rw-r--r-- | drivers/of/property.c | 76 |
17 files changed, 260 insertions, 85 deletions
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 1d86a33de528..568697873201 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -49,6 +49,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb +dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-dual-dsi.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb @@ -143,6 +144,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-bahamut.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-griffin.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8250-rb5-dvt.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5-dual-dsi.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5-dual-dsi.dts new file mode 100644 index 000000000000..1178bb85f7f4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5-dual-dsi.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Linaro Ltd. + */ + +/dts-v1/; + +#include "qrb5165-rb5.dts" + +&dsi0 { + qcom,dual-dsi-mode; + qcom,master-dsi; +}; + +&dsi1 { + status = "okay"; + vdda-supply = <&vreg_l9a_1p2>; + + qcom,dual-dsi-mode; + + ports { + port@1 { + endpoint { + remote-endpoint = <<9611_b>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dsi1_phy { + status = "okay"; + vdds-supply = <&vreg_l5a_0p88>; +}; + +<9611_codec { + ports { + port@1 { + reg = <1>; + + lt9611_b: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 15b2d33090c1..d6abee488b2e 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -931,6 +931,11 @@ no-emmc; }; +&slpi { + /* status = "okay"; */ + firmware-name = "qcom/sm8250/slpi.mbn"; +}; + &sound { compatible = "qcom,qrb5165-rb5-sndcard"; pinctrl-0 = <&tert_mi2s_active>; diff --git a/arch/arm64/boot/dts/qcom/sm8250-rb5-dvt.dts b/arch/arm64/boot/dts/qcom/sm8250-rb5-dvt.dts new file mode 100644 index 000000000000..47e14bb0f288 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-rb5-dvt.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Linaro Ltd. + */ + +/dts-v1/; + +#include "qrb5165-rb5.dts" + +&left_spkr { + compatible = "sdw10217201000"; + reg = <0 1>; +}; + +&right_spkr { + compatible = "sdw10217201000"; + reg = <0 2>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index bc773e210023..41c3c01bd7cb 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1792,7 +1792,7 @@ }; pcie0: pci@1c00000 { - compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; + compatible = "qcom,pcie-sm8250"; reg = <0 0x01c00000 0 0x3000>, <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, @@ -1810,8 +1810,15 @@ ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "msi8"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1893,7 +1900,7 @@ }; pcie1: pci@1c08000 { - compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; + compatible = "qcom,pcie-sm8250"; reg = <0 0x01c08000 0 0x3000>, <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, @@ -2001,7 +2008,7 @@ }; pcie2: pci@1c10000 { - compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; + compatible = "qcom,pcie-sm8250"; reg = <0 0x01c10000 0 0x3000>, <0 0x64000000 0 0xf1d>, <0 0x64000f20 0 0xa8>, @@ -2514,6 +2521,41 @@ }; }; + slimbam: dma@3a84000 { + compatible = "qcom,bam-v1.7.0"; + qcom,controlled-remotely; + reg = <0 0x3a84000 0 0x2a000>; + num-channels = <31>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <1>; + qcom,num-ees = <2>; + iommus = <&apps_smmu 0x1826 0x0>; + }; + + slim: slim@3ac0000 { + compatible = "qcom,slim-ngd-v2.2.0"; + reg = <0 0x3ac0000 0 0x2c000>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + + qcom,apps-ch-pipes = <0x780000>; + qcom,ea-pc = <0x270>; + status = "okay"; + dmas = <&slimbam 3>, <&slimbam 4>, + <&slimbam 5>, <&slimbam 6>; + dma-names = "rx", "tx", "tx2", "rx2"; + + iommus = <&apps_smmu 0x1826 0x0>; + #address-cells = <1>; + #size-cells = <0>; + + ngd@1 { + reg = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + }; + gpu: gpu@3d00000 { compatible = "qcom,adreno-650.2", "qcom,adreno"; diff --git a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c index fdf12d4c6416..33a928dc1f06 100644 --- a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c +++ b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c @@ -87,6 +87,7 @@ struct lt9611uxc_mode { u16 hdisplay; u16 vdisplay; u8 vrefresh; + bool dual_dsi; }; /* @@ -94,22 +95,24 @@ struct lt9611uxc_mode { * Enumerate them here to check whether the mode is supported. */ static struct lt9611uxc_mode lt9611uxc_modes[] = { - { 1920, 1080, 60 }, - { 1920, 1080, 30 }, - { 1920, 1080, 25 }, - { 1366, 768, 60 }, - { 1360, 768, 60 }, - { 1280, 1024, 60 }, - { 1280, 800, 60 }, - { 1280, 720, 60 }, - { 1280, 720, 50 }, - { 1280, 720, 30 }, - { 1152, 864, 60 }, - { 1024, 768, 60 }, - { 800, 600, 60 }, - { 720, 576, 50 }, - { 720, 480, 60 }, - { 640, 480, 60 }, + { 3840, 2160, 60, true }, + { 3840, 2160, 30, true }, + { 1920, 1080, 60, false }, + { 1920, 1080, 30, false }, + { 1920, 1080, 25, false }, + { 1366, 768, 60, false }, + { 1360, 768, 60, false }, + { 1280, 1024, 60, false }, + { 1280, 800, 60, false }, + { 1280, 720, 60, false }, + { 1280, 720, 50, false }, + { 1280, 720, 30, false }, + { 1152, 864, 60, false }, + { 1024, 768, 60, false }, + { 800, 600, 60, false }, + { 720, 576, 50, false }, + { 720, 480, 60, false }, + { 640, 480, 60, false }, }; static struct lt9611uxc *bridge_to_lt9611uxc(struct drm_bridge *bridge) @@ -314,8 +317,15 @@ static enum drm_mode_status lt9611uxc_connector_mode_valid(struct drm_connector struct drm_display_mode *mode) { struct lt9611uxc_mode *lt9611uxc_mode = lt9611uxc_find_mode(mode); + struct lt9611uxc *lt9611uxc = connector_to_lt9611uxc(connector); + + if (!lt9611uxc_mode) + return MODE_BAD; - return lt9611uxc_mode ? MODE_OK : MODE_BAD; + if (lt9611uxc_mode->dual_dsi && (!lt9611uxc->dsi0 || !lt9611uxc->dsi1)) + return MODE_BAD; + + return MODE_OK; } static const struct drm_connector_helper_funcs lt9611uxc_bridge_connector_helper_funcs = { @@ -376,11 +386,16 @@ lt9611uxc_bridge_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info, const struct drm_display_mode *mode) { - struct lt9611uxc_mode *lt9611uxc_mode; + struct lt9611uxc *lt9611uxc = bridge_to_lt9611uxc(bridge); + struct lt9611uxc_mode *lt9611uxc_mode = lt9611uxc_find_mode(mode); + + if (!lt9611uxc_mode) + return MODE_BAD; - lt9611uxc_mode = lt9611uxc_find_mode(mode); + if (lt9611uxc_mode->dual_dsi && (!lt9611uxc->dsi0 || !lt9611uxc->dsi1)) + return MODE_BAD; - return lt9611uxc_mode ? MODE_OK : MODE_BAD; + return MODE_OK; } static void lt9611uxc_video_setup(struct lt9611uxc *lt9611uxc, @@ -400,6 +415,13 @@ static void lt9611uxc_video_setup(struct lt9611uxc *lt9611uxc, vsync_len = mode->vsync_end - mode->vsync_start; vfront_porch = mode->vsync_start - mode->vdisplay; + if (lt9611uxc->dsi0 && lt9611uxc->dsi1) + regmap_write(lt9611uxc->regmap, 0xb025, 0x03); + else if (lt9611uxc->dsi0) + regmap_write(lt9611uxc->regmap, 0xb025, 0x01); + else + regmap_write(lt9611uxc->regmap, 0xb025, 0x02); + regmap_write(lt9611uxc->regmap, 0xd00d, (u8)(v_total / 256)); regmap_write(lt9611uxc->regmap, 0xd00e, (u8)(v_total % 256)); @@ -522,13 +544,13 @@ static int lt9611uxc_parse_dt(struct device *dev, struct lt9611uxc *lt9611uxc) { lt9611uxc->dsi0_node = of_graph_get_remote_node(dev->of_node, 0, -1); - if (!lt9611uxc->dsi0_node) { + lt9611uxc->dsi1_node = of_graph_get_remote_node(dev->of_node, 1, -1); + + if (!lt9611uxc->dsi0_node && !lt9611uxc->dsi1_node) { dev_err(lt9611uxc->dev, "failed to get remote node for primary dsi\n"); return -ENODEV; } - lt9611uxc->dsi1_node = of_graph_get_remote_node(dev->of_node, 1, -1); - return 0; } @@ -947,11 +969,13 @@ retry: drm_bridge_add(<9611uxc->bridge); - /* Attach primary DSI */ - lt9611uxc->dsi0 = lt9611uxc_attach_dsi(lt9611uxc, lt9611uxc->dsi0_node); - if (IS_ERR(lt9611uxc->dsi0)) { - ret = PTR_ERR(lt9611uxc->dsi0); - goto err_remove_bridge; + /* Attach primary DSI, if specified */ + if (lt9611uxc->dsi0_node) { + lt9611uxc->dsi0 = lt9611uxc_attach_dsi(lt9611uxc, lt9611uxc->dsi0_node); + if (IS_ERR(lt9611uxc->dsi0)) { + ret = PTR_ERR(lt9611uxc->dsi0); + goto err_remove_bridge; + } } /* Attach secondary DSI, if specified */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 52a626117f70..fff8f015c88c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1102,14 +1102,18 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, return; } - if (!hw_ctl[i]) { + /* Use first (and only) CTL if active CTLs are supported */ + if (dpu_kms->catalog->caps->has_active_ctls) + phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[0]); + else + phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); + if (!phys->hw_ctl) { DPU_ERROR_ENC(dpu_enc, "no ctl block assigned at idx: %d\n", i); return; } phys->hw_pp = dpu_enc->hw_pp[i]; - phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); phys->cached_mode = crtc_state->adjusted_mode; if (phys->ops.atomic_mode_set) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index ae28b2b93e69..ed89011e36a7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -58,6 +58,8 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( return; intf_cfg.intf = phys_enc->intf_idx; + if (phys_enc->split_role == ENC_ROLE_MASTER) + intf_cfg.intf_master = phys_enc->hw_intf->idx; intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; intf_cfg.stream_sel = cmd_enc->stream_sel; intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 2c14646661b7..2c1dbfce20b5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -270,6 +270,8 @@ static void dpu_encoder_phys_vid_setup_timing_engine( DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc); intf_cfg.intf = phys_enc->hw_intf->idx; + if (phys_enc->split_role == ENC_ROLE_MASTER) + intf_cfg.intf_master = phys_enc->hw_intf->idx; intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID; intf_cfg.stream_sel = 0; /* Don't care value for video mode */ intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); @@ -347,7 +349,8 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx) static bool dpu_encoder_phys_vid_needs_single_flush( struct dpu_encoder_phys *phys_enc) { - return phys_enc->split_role != ENC_ROLE_SOLO; + return !(phys_enc->hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) && + phys_enc->split_role != ENC_ROLE_SOLO; } static void dpu_encoder_phys_vid_atomic_mode_set( diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 0239a811d5ec..e875afa1e30e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -328,6 +328,7 @@ static const struct dpu_caps sm8150_dpu_caps = { .has_dim_layer = true, .has_idle_pc = true, .has_3d_merge = true, + .has_active_ctls = true, .max_linewidth = 4096, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, .max_hdeci_exp = MAX_HORZ_DECIMATION, @@ -360,6 +361,7 @@ static const struct dpu_caps sm8250_dpu_caps = { .has_dim_layer = true, .has_idle_pc = true, .has_3d_merge = true, + .has_active_ctls = true, .max_linewidth = 4096, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 71fe4c505f5b..2422c09275cb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -395,6 +395,7 @@ struct dpu_caps { bool has_dim_layer; bool has_idle_pc; bool has_3d_merge; + bool has_active_ctls; /* SSPP limits */ u32 max_linewidth; u32 pixel_ram_size; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index e12b7fa48a7b..ee97577b1d14 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -531,6 +531,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, u32 intf_active = 0; u32 wb_active = 0; u32 mode_sel = 0; + u32 merge_3d_active = 0; /* CTL_TOP[31:28] carries group_id to collate CTL paths * per VM. Explicitly disable it until VM support is @@ -554,10 +555,17 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if (cfg->wb) wb_active |= BIT(cfg->wb - WB_0); + merge_3d_active = DPU_REG_READ(c, CTL_MERGE_3D_ACTIVE); + if (cfg->merge_3d) + merge_3d_active |= BIT(cfg->merge_3d - MERGE_3D_0); + DPU_REG_WRITE(c, CTL_TOP, mode_sel); DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active); DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active); + if (cfg->intf_master) + DPU_REG_WRITE(c, CTL_INTF_MASTER, BIT(cfg->intf_master - INTF_0)); + if (cfg->merge_3d) DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, BIT(cfg->merge_3d - MERGE_3D_0)); @@ -565,6 +573,13 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, DSC_IDX); DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc); } + if (cfg->merge_3d) + DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active); + + if (cfg->intf_master) + DPU_DEBUG_DRIVER("ACTIVE: %x %x %lx\n", intf_active, merge_3d_active, BIT(cfg->intf_master - INTF_0)); + else + DPU_DEBUG_DRIVER("ACTIVE: %x %x\n", intf_active, merge_3d_active); } static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index 7d9ad6a3f9f6..79cc5fc039f1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -36,6 +36,7 @@ struct dpu_hw_stage_cfg { /** * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface * @intf : Interface id + * @intf_master: Master interface id in the dual pipe topology * @mode_3d: 3d mux configuration * @merge_3d: 3d merge block used * @intf_mode_sel: Interface mode, cmd / vid @@ -44,6 +45,7 @@ struct dpu_hw_stage_cfg { */ struct dpu_hw_intf_cfg { enum dpu_intf intf; + enum dpu_intf intf_master; enum dpu_wb wb; enum dpu_3d_blend_mode mode_3d; enum dpu_merge_3d merge_3d; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 73b3442e7467..8a3411edacd3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -224,6 +224,7 @@ int dpu_rm_init(struct dpu_rm *rm, } rm->ctl_blks[ctl->id - CTL_0] = &hw->base; } + rm->has_active_ctls = cat->caps->has_active_ctls; for (i = 0; i < cat->dspp_count; i++) { struct dpu_hw_dspp *hw; @@ -443,10 +444,15 @@ static int _dpu_rm_reserve_ctls( int i = 0, j, num_ctls; bool needs_split_display; - /* each hw_intf needs its own hw_ctrl to program its control path */ - num_ctls = top->num_intf; + if (rm->has_active_ctls) { + num_ctls = 1; + needs_split_display = false; + } else { + /* each hw_intf needs its own hw_ctrl to program its control path */ + num_ctls = top->num_intf; - needs_split_display = _dpu_rm_needs_split_display(top); + needs_split_display = _dpu_rm_needs_split_display(top); + } for (j = 0; j < ARRAY_SIZE(rm->ctl_blks); j++) { const struct dpu_hw_ctl *ctl; @@ -464,7 +470,7 @@ static int _dpu_rm_reserve_ctls( DPU_DEBUG("ctl %d caps 0x%lX\n", j + CTL_0, features); - if (needs_split_display != has_split_display) + if (!rm->has_active_ctls && needs_split_display != has_split_display) continue; ctl_idx[i] = j; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index 59de72b381f9..2b9f7557dd70 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -31,6 +31,7 @@ struct dpu_rm { struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0]; struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0]; struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0]; + bool has_active_ctls; }; /** diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 56dfa2d24be1..ca15d2409d08 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -782,6 +782,22 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) goto fail; } + /* + * As explained in msm_dsi_phy_enable, resetting the DSI PHY (as done + * in dsi_mgr_phy_enable) silently changes its PLL registers to power-on + * defaults, but the generic clock framework manages and caches several + * of the PLL registers. It initializes these caches at registration + * time via register read. + * + * As a result, we need to save DSI PLL registers once at probe in order + * for the first call to msm_dsi_phy_enable to successfully bring PLL + * registers back in line with what the generic clock framework expects. + * + * Subsequent PLL restores during msm_dsi_phy_enable will always be + * paired with PLL saves in msm_dsi_phy_disable. + */ + msm_dsi_phy_pll_save_state(phy); + dsi_phy_disable_resource(phy); platform_set_drvdata(pdev, phy); diff --git a/drivers/of/property.c b/drivers/of/property.c index 967f79b59016..5f1606a95676 100644 --- a/drivers/of/property.c +++ b/drivers/of/property.c @@ -1074,36 +1074,6 @@ static bool of_is_ancestor_of(struct device_node *test_ancestor, return false; } -static struct device_node *of_get_compat_node(struct device_node *np) -{ - of_node_get(np); - - while (np) { - if (!of_device_is_available(np)) { - of_node_put(np); - np = NULL; - } - - if (of_find_property(np, "compatible", NULL)) - break; - - np = of_get_next_parent(np); - } - - return np; -} - -static struct device_node *of_get_compat_node_parent(struct device_node *np) -{ - struct device_node *parent, *node; - - parent = of_get_parent(np); - node = of_get_compat_node(parent); - of_node_put(parent); - - return node; -} - /** * of_link_to_phandle - Add fwnode link to supplier from supplier phandle * @con_np: consumer device tree node @@ -1127,11 +1097,25 @@ static int of_link_to_phandle(struct device_node *con_np, struct device *sup_dev; struct device_node *tmp_np = sup_np; + of_node_get(sup_np); /* * Find the device node that contains the supplier phandle. It may be * @sup_np or it may be an ancestor of @sup_np. */ - sup_np = of_get_compat_node(sup_np); + while (sup_np) { + + /* Don't allow linking to a disabled supplier */ + if (!of_device_is_available(sup_np)) { + of_node_put(sup_np); + sup_np = NULL; + } + + if (of_find_property(sup_np, "compatible", NULL)) + break; + + sup_np = of_get_next_parent(sup_np); + } + if (!sup_np) { pr_debug("Not linking %pOFP to %pOFP - No device\n", con_np, tmp_np); @@ -1277,10 +1261,6 @@ static struct device_node *parse_##fname(struct device_node *np, \ * @parse_prop.prop_name: Name of property holding a phandle value * @parse_prop.index: For properties holding a list of phandles, this is the * index into the list - * @optional: Describes whether a supplier is mandatory or not - * @node_not_dev: The consumer node containing the property is never converted - * to a struct device. Instead, parse ancestor nodes for the - * compatible property to find a node corresponding to a device. * * Returns: * parse_prop() return values are @@ -1292,10 +1272,8 @@ struct supplier_bindings { struct device_node *(*parse_prop)(struct device_node *np, const char *prop_name, int index); bool optional; - bool node_not_dev; }; -DEFINE_SIMPLE_PROP(clocks, "clocks", "#clock-cells") DEFINE_SIMPLE_PROP(interconnects, "interconnects", "#interconnect-cells") DEFINE_SIMPLE_PROP(iommus, "iommus", "#iommu-cells") DEFINE_SIMPLE_PROP(mboxes, "mboxes", "#mbox-cells") @@ -1325,6 +1303,21 @@ DEFINE_SIMPLE_PROP(backlight, "backlight", NULL) DEFINE_SUFFIX_PROP(regulators, "-supply", NULL) DEFINE_SUFFIX_PROP(gpio, "-gpio", "#gpio-cells") +static struct device_node *parse_clocks(struct device_node *np, + const char *prop_name, int index) +{ + /* + * Do not create clock-related device links for clocks controllers, + * clock orphans will handle missing clock parents automatically. + */ + if (!strcmp(prop_name, "clocks") && + of_find_property(np, "#clock-cells", NULL)) + return NULL; + + return parse_prop_cells(np, prop_name, index, "clocks", + "#clock-cells"); +} + static struct device_node *parse_gpios(struct device_node *np, const char *prop_name, int index) { @@ -1405,7 +1398,6 @@ static const struct supplier_bindings of_supplier_bindings[] = { { .parse_prop = parse_pinctrl6, }, { .parse_prop = parse_pinctrl7, }, { .parse_prop = parse_pinctrl8, }, - { .parse_prop = parse_remote_endpoint, .node_not_dev = true, }, { .parse_prop = parse_pwms, }, { .parse_prop = parse_resets, }, { .parse_prop = parse_leds, }, @@ -1452,16 +1444,10 @@ static int of_link_property(struct device_node *con_np, const char *prop_name) } while ((phandle = s->parse_prop(con_np, prop_name, i))) { - struct device_node *con_dev_np; - - con_dev_np = s->node_not_dev - ? of_get_compat_node_parent(con_np) - : of_node_get(con_np); matched = true; i++; - of_link_to_phandle(con_dev_np, phandle); + of_link_to_phandle(con_np, phandle); of_node_put(phandle); - of_node_put(con_dev_np); } s++; } |