diff options
author | Linaro CI <ci_notify@linaro.org> | 2021-06-07 09:29:23 +0000 |
---|---|---|
committer | Linaro CI <ci_notify@linaro.org> | 2021-06-07 09:29:23 +0000 |
commit | ff0ab4ca28a224b49b89f90984377676543c3e81 (patch) | |
tree | e3800314caccc7d89ed284ea72347ed5ffb0f05b | |
parent | 49f31429b566f43efcdb78554cd4a97e9dbdd514 (diff) | |
parent | 3018e97f8f4a82a4b363c04b1f3bc869783dc55e (diff) |
Merge remote-tracking branch 'sdx55-dts/tracking-qcomlt-sdx55-dts' into integration-linux-qcomlt
-rw-r--r-- | arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 53 | ||||
-rw-r--r-- | arch/arm/boot/dts/qcom-sdx55.dtsi | 88 |
2 files changed, 141 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index 3065f84634b8..6932fd58ab5c 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -236,6 +236,21 @@ status = "ok"; }; +&pcie0_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1e_bb_1p2>; + vdda-pll-supply = <&vreg_l4e_bb_0p875>; +}; + +&pcie_ep { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; +}; + &qpic_bam { status = "ok"; }; @@ -260,6 +275,44 @@ memory-region = <&mpss_adsp_mem>; }; +&tlmm { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio56"; + function = "pcie_clkreq"; + }; + config { + pins = "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio57"; + function = "gpio"; + }; + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + config { + pins = "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; +}; + &usb_hsphy { status = "okay"; vdda-pll-supply = <&vreg_l4e_bb_0p875>; diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 0057c7c04d31..563216a93ab3 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/qcom,gcc-sdx55.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interconnect/qcom,sdx55.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> @@ -310,6 +311,41 @@ status = "disabled"; }; + pcie0_phy: phy@1c07000 { + compatible = "qcom,sdx55-qmp-pcie-phy"; + reg = <0x01c07000 0x1c4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie0_lane: lanes@1c06000 { + reg = <0x01c06000 0x104>, /* tx0 */ + <0x01c06200 0x328>, /* rx0 */ + <0x01c07200 0x1e8>, /* pcs */ + <0x01c06800 0x104>, /* tx1 */ + <0x01c06a00 0x328>, /* rx1 */ + <0x01c07600 0x800>; /* pcs_misc */ + clocks = <&gcc GCC_PCIE_PIPE_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + clock-output-names = "pcie_pipe_clk"; + }; + }; + ipa: ipa@1e40000 { compatible = "qcom,sdx55-ipa"; @@ -369,6 +405,58 @@ status = "disabled"; }; + pcie_ep: qcom,pcie@40000000 { + compatible = "qcom,pcie-ep"; + + reg = <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40002000 0x1000>, + <0x01c00000 0x3000>, + <0x01fcb000 0x1000>; + reg-names = "dbi", "elbi", "atu", "addr_space", "parf", "tcsr"; + + #address-cells = <0>; + interrupt-parent = <&pcie_ep>; + interrupts = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int_global"; + + clkreq-gpio = <&tlmm 56 GPIO_ACTIVE_LOW>; + perst-gpio = <&tlmm 57 GPIO_ACTIVE_HIGH>; + wake-gpio = <&tlmm 53 GPIO_ACTIVE_LOW>; + + vdda-supply = <&vreg_l1e_bb_1p2>; + vdda_phy-supply = <&vreg_l4e_bb_0p875>; + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>; + + clock-names = "pipe_clk", "ahb_clk", + "master_axi_clk", "slave_axi_clk", + "aux_clk", "ldo", + "sleep_clk", + "slave_q2a_axi_clk"; + + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core_reset"; + + power-domains = <&gcc PCIE_GDSC>; + + phys = <&pcie0_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sdx55-mpss-pas"; reg = <0x04080000 0x4040>; |