diff options
| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2021-03-24 09:30:52 +0530 |
|---|---|---|
| committer | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2021-05-11 11:02:50 +0530 |
| commit | 3018e97f8f4a82a4b363c04b1f3bc869783dc55e (patch) | |
| tree | 5f2b22ddeb197112b161432515742f697e8b364d | |
| parent | f5a32e14b27faaa0702101a3451d76d2bb840a5d (diff) | |
[TEMP]: ARM: dts: qcom: sdx55: Add support for PCIe EP
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 46 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom-sdx55.dtsi | 53 |
2 files changed, 99 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index db1975359f1a..6932fd58ab5c 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -243,6 +243,14 @@ vdda-pll-supply = <&vreg_l4e_bb_0p875>; }; +&pcie_ep { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; +}; + &qpic_bam { status = "ok"; }; @@ -267,6 +275,44 @@ memory-region = <&mpss_adsp_mem>; }; +&tlmm { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio56"; + function = "pcie_clkreq"; + }; + config { + pins = "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio57"; + function = "gpio"; + }; + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + config { + pins = "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; +}; + &usb_hsphy { status = "okay"; vdda-pll-supply = <&vreg_l4e_bb_0p875>; diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 56432caf4577..563216a93ab3 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/qcom,gcc-sdx55.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interconnect/qcom,sdx55.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> @@ -404,6 +405,58 @@ status = "disabled"; }; + pcie_ep: qcom,pcie@40000000 { + compatible = "qcom,pcie-ep"; + + reg = <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40002000 0x1000>, + <0x01c00000 0x3000>, + <0x01fcb000 0x1000>; + reg-names = "dbi", "elbi", "atu", "addr_space", "parf", "tcsr"; + + #address-cells = <0>; + interrupt-parent = <&pcie_ep>; + interrupts = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int_global"; + + clkreq-gpio = <&tlmm 56 GPIO_ACTIVE_LOW>; + perst-gpio = <&tlmm 57 GPIO_ACTIVE_HIGH>; + wake-gpio = <&tlmm 53 GPIO_ACTIVE_LOW>; + + vdda-supply = <&vreg_l1e_bb_1p2>; + vdda_phy-supply = <&vreg_l4e_bb_0p875>; + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>; + + clock-names = "pipe_clk", "ahb_clk", + "master_axi_clk", "slave_axi_clk", + "aux_clk", "ldo", + "sleep_clk", + "slave_q2a_axi_clk"; + + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core_reset"; + + power-domains = <&gcc PCIE_GDSC>; + + phys = <&pcie0_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sdx55-mpss-pas"; reg = <0x04080000 0x4040>; |