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author | Linaro CI <ci_notify@linaro.org> | 2020-12-29 14:16:10 +0000 |
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committer | Linaro CI <ci_notify@linaro.org> | 2020-12-29 14:16:10 +0000 |
commit | a298bfd5f184d2273036f1147d97af0175b43c7d (patch) | |
tree | 26afd9fd7bee712040df0cc1cc7408d890eaffc8 | |
parent | d0e1fd245dba9a59a458073962f8e14dff821768 (diff) | |
parent | 3bc88d3f6dbd97de7283c54b38a7dcc5a6e59a06 (diff) |
Merge remote-tracking branch 'db820c-fixes/db820c/5.7-rc1' into integration-linux-qcomlt
# Conflicts:
# drivers/clk/qcom/Kconfig
# drivers/clk/qcom/clk-cpu-8996.c
# drivers/soc/qcom/Kconfig
# drivers/soc/qcom/kryo-l2-accessors.c
-rw-r--r-- | drivers/clk/qcom/clk-cpu-8996.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 4a4fde8dd12d..50683db99620 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -32,7 +32,9 @@ * * The primary PLL is what drives the CPU clk, except for times * when we are reprogramming the PLL itself (for rate changes) when - * we temporarily switch to an alternate PLL. + * we temporarily switch to an alternate PLL. A subsequent patch adds + * support to switch between primary and alternate PLL during rate + * changes. * * The primary PLL operates on a single VCO range, between 600MHz * and 3GHz. However the CPUs do support OPPs with frequencies @@ -44,6 +46,7 @@ * Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk * and for frequencies between 300MHz and 600MHz we follow * Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk + * Support for this is added in a subsequent patch as well. * * ACD stands for Adaptive Clock Distribution and is used to * detect voltage droops. @@ -534,5 +537,6 @@ static struct platform_driver qcom_cpu_clk_msm8996_driver = { }; module_platform_driver(qcom_cpu_clk_msm8996_driver); +MODULE_ALIAS("platform:msm8996-apcc"); MODULE_DESCRIPTION("QCOM MSM8996 CPU Clock Driver"); MODULE_LICENSE("GPL v2"); |