diff options
author | Linaro CI <ci_notify@linaro.org> | 2019-04-08 00:45:10 +0000 |
---|---|---|
committer | Linaro CI <ci_notify@linaro.org> | 2019-04-08 00:45:10 +0000 |
commit | b870fa3ce630da012d7491e3c3da9f987034749d (patch) | |
tree | da7358aa81b2b8ed8551e20ea6d4f9f911ab91f1 | |
parent | 812eccc5c3b68572c949ad6fd28751381974d2d4 (diff) | |
parent | 5764a9194423c4c1cee35cd0e000aea9388a5a2c (diff) |
Merge remote-tracking branch 'bus-scaling/bus-scaling' into integration-linux-qcomlt
# Conflicts:
# arch/arm64/boot/dts/qcom/msm8996.dtsi
# arch/arm64/boot/dts/qcom/sdm845.dtsi
# drivers/interconnect/core.c
# drivers/interconnect/qcom/Kconfig
# drivers/interconnect/qcom/Makefile
# drivers/interconnect/qcom/sdm845.c
# include/linux/interconnect-provider.h
# include/linux/interconnect.h
21 files changed, 2252 insertions, 34 deletions
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,interconnect-smd-rpm.txt b/Documentation/devicetree/bindings/interconnect/qcom,interconnect-smd-rpm.txt new file mode 100644 index 000000000000..2325167f6eaf --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,interconnect-smd-rpm.txt @@ -0,0 +1,32 @@ +Qualcomm SMD-RPM interconnect driver binding +------------------------------------------------ +The RPM (Resource Power Manager) is a dedicated hardware engine +for managing the shared SoC resources in order to keep the lowest +power profile. It communicates with other hardware subsystems via +the shared memory driver (SMD) back-end and accepts requests for +various resources. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,interconnect-smd-rpm" + +Example: + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests { + compatible = "qcom,rpm-msm8916"; + qcom,smd-channels = "rpm_requests"; + + interconnect-smd-rpm { + compatible = "qcom,interconnect-smd-rpm"; + }; + + }; + }; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8916.txt b/Documentation/devicetree/bindings/interconnect/qcom,msm8916.txt new file mode 100644 index 000000000000..5763fafee808 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8916.txt @@ -0,0 +1,41 @@ +Qualcomm MSM8916 Network-On-Chip interconnect driver binding +---------------------------------------------------- + +Required properties : +- compatible : shall contain only one of the following: + "qcom,msm8916-bimc" + "qcom,msm8916-pnoc" + "qcom,msm8916-snoc" +- #interconnect-cells : should contain 1 +- reg : shall contain base register location and length + +Optional properties : +clocks : list of phandles and specifiers to all interconnect bus clocks +clock-names : clock names should include both "bus_clk" and "bus_a_clk" + +Examples: + + snoc: interconnect@580000 { + compatible = "qcom,msm8916-snoc"; + #interconnect-cells = <1>; + reg = <0x580000 0x14000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + bimc: interconnect@400000 { + compatible = "qcom,msm8916-bimc"; + #interconnect-cells = <1>; + reg = <0x400000 0x62000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + pnoc: interconnect@500000 { + compatible = "qcom,msm8916-pnoc"; + #interconnect-cells = <1>; + reg = <0x500000 0x11000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8996.txt b/Documentation/devicetree/bindings/interconnect/qcom,msm8996.txt new file mode 100644 index 000000000000..26bbc564cd60 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8996.txt @@ -0,0 +1,95 @@ +Qualcomm MSM8996 Network-On-Chip interconnect driver binding +---------------------------------------------------- + +Required properties : +- compatible : shall contain only one of the following: + "qcom,msm8996-a0noc" + "qcom,msm8996-a1noc" + "qcom,msm8996-a2noc" + "qcom,msm8996-bimc" + "qcom,msm8996-cnoc" + "qcom,msm8996-mmnoc" + "qcom,msm8996-snoc" + "qcom,msm8996-pnoc" +- #interconnect-cells : should contain 1 +- reg : shall contain base register location and length + +Optional properties : +clocks : list of phandles and specifiers to all interconnect bus clocks +clock-names : clock names should include both "bus_clk" and "bus_a_clk" + +Examples: + + bimc: bimc@400000 { + compatible = "qcom,msm8996-bimc"; + #interconnect-cells = <1>; + reg = <0x400000 0x62000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + + cnoc: cnoc@500000 { + compatible = "qcom,msm8996-cnoc"; + #interconnect-cells = <1>; + reg = <0x500000 0x80>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; + }; + + snoc: snoc@520000 { + compatible = "qcom,msm8996-snoc"; + #interconnect-cells = <1>; + reg = <0x520000 0xa100>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + + a0noc: a0noc@540000 { + compatible = "qcom,msm8996-a0noc"; + #interconnect-cells = <1>; + reg = <0x540000 0x5100>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, + <&gcc GCC_AGGRE0_SNOC_AXI_CLK>; + power-domains = <&gcc AGGRE0_NOC_GDSC>; + }; + + a1noc: a1noc@560000 { + compatible = "qcom,msm8996-a1noc"; + #interconnect-cells = <1>; + reg = <0x560000 0x3100>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, + <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; + }; + + a2noc: a2noc@580000 { + compatible = "qcom,msm8996-a2noc"; + #interconnect-cells = <1>; + reg = <0x580000 0x8100>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, + <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>; + }; + + mmnoc: mmnoc@5a0000 { + compatible = "qcom,msm8996-mmnoc"; + #interconnect-cells = <1>; + reg = <0x5a0000 0xb080>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, + <&rpmcc RPM_SMD_MMAXI_A_CLK>; + power-domains = <&mmcc MMAGIC_BIMC_GDSC>; + }; + + pnoc: pnoc@5c0000 { + compatible = "qcom,msm8996-pnoc"; + #interconnect-cells = <1>; + reg = <0x5c0000 0x2480>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 0803ca8c02da..64a0c49a32d4 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include <dt-bindings/interconnect/qcom,msm8916.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8916.h> #include <dt-bindings/reset/qcom,gcc-msm8916.h> @@ -1525,6 +1526,42 @@ #size-cells = <0>; }; }; + + bimc: interconnect@400000 { + compatible = "qcom,msm8916-bimc"; + #interconnect-cells = <1>; + reg = <0x400000 0x62000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + base-offset = <0>; + qos-offset = <0>; + status = "okay"; + }; + + pnoc: interconnect@500000 { + compatible = "qcom,msm8916-pnoc"; + #interconnect-cells = <1>; + reg = <0x500000 0x11000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + base-offset = <0x7000>; + qos-offset = <0x1000>; + status = "okay"; + }; + + snoc: interconnect@580000 { + compatible = "qcom,msm8916-snoc"; + #interconnect-cells = <1>; + reg = <0x580000 0x14000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + base-offset = <0x7000>; + qos-offset = <0x1000>; + status = "okay"; + }; }; smd { @@ -1544,6 +1581,10 @@ #clock-cells = <1>; }; + interconnect-smd-rpm { + compatible = "qcom,interconnect-smd-rpm"; + }; + smd_rpm_regulators: pm8916-regulators { compatible = "qcom,rpm-pm8916-regulators"; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 06162fdf57db..0e61f6adbdd3 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2014-2015, 2018 The Linux Foundation. All rights reserved. */ +#include <dt-bindings/interconnect/qcom,msm8996.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8996.h> #include <dt-bindings/clock/qcom,mmcc-msm8996.h> @@ -821,6 +822,10 @@ }; }; + interconnect-smd-rpm { + compatible = "qcom,interconnect-smd-rpm"; + }; + pm8994-regulators { compatible = "qcom,rpm-pm8994-regulators"; @@ -1790,6 +1795,108 @@ }; }; + bimc: bimc@400000 { + compatible = "qcom,msm8996-bimc"; + #interconnect-cells = <1>; + reg = <0x400000 0x62000>; + type = <2>; + base-offset = <0x8000>; + qos-offset = <0x4000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + status = "okay"; + }; + + cnoc: cnoc@500000 { + compatible = "qcom,msm8996-cnoc"; + #interconnect-cells = <1>; + reg = <0x500000 0x80>; + type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; + status = "okay"; + }; + + snoc: snoc@520000 { + compatible = "qcom,msm8996-snoc"; + #interconnect-cells = <1>; + reg = <0x520000 0xa100>; + type = <1>; + base-offset = <0x4000>; + qos-offset = <0x1000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + status = "okay"; + }; + + a0noc: a0noc@540000 { + compatible = "qcom,msm8996-a0noc"; + #interconnect-cells = <1>; + reg = <0x540000 0x5100>; + type = <1>; + qcom,base-offset = <0x3000>; + qos-offset = <0x1000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, + <&gcc GCC_AGGRE0_SNOC_AXI_CLK>; + power-domains = <&gcc AGGRE0_NOC_GDSC>; + status = "okay"; + }; + + a1noc: a1noc@560000 { + compatible = "qcom,msm8996-a1noc"; + #interconnect-cells = <1>; + reg = <0x560000 0x3100>; + type = <1>; + base-offset = <0x2000>; + qos-offset = <0x1000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, + <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; + status = "okay"; + }; + + a2noc: a2noc@580000 { + compatible = "qcom,msm8996-a2noc"; + #interconnect-cells = <1>; + reg = <0x580000 0x8100>; + base-offset = <0x3000>; + qos-offset = <0x1000>; + type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, + <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>; + status = "okay"; + }; + + mmnoc: mmnoc@5a0000 { + compatible = "qcom,msm8996-mmnoc"; + #interconnect-cells = <1>; + reg = <0x5a0000 0xb080>; + type = <1>; + base-offset = <0x4000>; + qos-offset = <0x1000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, + <&rpmcc RPM_SMD_MMAXI_A_CLK>; + power-domains = <&mmcc MMAGIC_BIMC_GDSC>; + status = "okay"; + }; + + pnoc: pnoc@5c0000 { + compatible = "qcom,msm8996-pnoc"; + #interconnect-cells = <1>; + reg = <0x5c0000 0x2480>; + type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + status = "okay"; + }; + slimbam:dma@9184000 { compatible = "qcom,bam-v1.7.0"; @@ -2085,7 +2192,6 @@ }; sound: sound { - }; adsp-pil { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index dfda6c9c082a..c6689f1bd035 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/clock/qcom,lpass-sdm845.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,videocc-sdm845.h> +#include <dt-bindings/interconnect/qcom,sdm845.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/phy/phy-qcom-qusb2.h> #include <dt-bindings/power/qcom-aoss-qmp.h> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 63af4425a7da..acebeb95d657 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -786,6 +786,11 @@ CONFIG_UNIPHIER_EFUSE=y CONFIG_MESON_EFUSE=m CONFIG_TEE=y CONFIG_OPTEE=y +CONFIG_INTERCONNECT=y +CONFIG_INTERCONNECT_QCOM=y +CONFIG_INTERCONNECT_QCOM_MSM8916=y +CONFIG_INTERCONNECT_QCOM_MSM8996=y +CONFIG_INTERCONNECT_QCOM_SDM845=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS_POSIX_ACL=y diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c index 6005a1c189f6..8d2348bf283e 100644 --- a/drivers/interconnect/core.c +++ b/drivers/interconnect/core.c @@ -42,10 +42,12 @@ struct icc_req { /** * struct icc_path - interconnect path structure + * @tag: path tag * @num_nodes: number of hops (nodes) * @reqs: array of the requests applicable to this path of nodes */ struct icc_path { + u8 tag; size_t num_nodes; struct icc_req reqs[]; }; @@ -206,7 +208,7 @@ out: * implementing its own aggregate() function. */ -static int aggregate_requests(struct icc_node *node) +static int aggregate_requests(struct icc_node *node, u8 tag) { struct icc_provider *p = node->provider; struct icc_req *r; @@ -215,7 +217,7 @@ static int aggregate_requests(struct icc_node *node) node->peak_bw = 0; hlist_for_each_entry(r, &node->req_list, req_node) - p->aggregate(node, r->avg_bw, r->peak_bw, + p->aggregate(node, tag, r->avg_bw, r->peak_bw, &node->avg_bw, &node->peak_bw); return 0; @@ -397,6 +399,23 @@ struct icc_path *of_icc_get(struct device *dev, const char *name) EXPORT_SYMBOL_GPL(of_icc_get); /** + * icc_set_tag() - set tag on a path + * @path: the path we want to tag + * @tag: the tag value + * + * This function allows consumers to append a tag to the path, so that a + * different aggregation could be done based on this tag. + */ +void icc_set_tag(struct icc_path *path, u8 tag) +{ + if (!path) + return; + + path->tag = tag; +} +EXPORT_SYMBOL_GPL(icc_set_tag); + +/** * icc_set_bw() - set bandwidth constraints on an interconnect path * @path: reference to the path returned by icc_get() * @avg_bw: average bandwidth in kilobytes per second @@ -434,7 +453,7 @@ int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw) path->reqs[i].peak_bw = peak_bw; /* aggregate requests for this node */ - aggregate_requests(node); + aggregate_requests(node, path->tag); } ret = apply_constraints(path); @@ -446,7 +465,7 @@ int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw) node = path->reqs[i].node; path->reqs[i].avg_bw = old_avg; path->reqs[i].peak_bw = old_peak; - aggregate_requests(node); + aggregate_requests(node, path->tag); } apply_constraints(path); } diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig index 290d330abe5a..2334da717c4c 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -11,3 +11,29 @@ config INTERCONNECT_QCOM_SDM845 help This is a driver for the Qualcomm Network-on-Chip on sdm845-based platforms. + +config INTERCONNECT_QCOM_SMD_RPM + tristate "Qualcomm SMD RPM interconnect driver" + depends on INTERCONNECT_QCOM + depends on QCOM_SMD_RPM + help + This is a driver for communicating interconnect related configuration + details with a remote processor (RPM) on Qualcomm platforms. + +config INTERCONNECT_QCOM_MSM8916 + tristate "Qualcomm MSM8916 interconnect driver" + depends on INTERCONNECT_QCOM + depends on QCOM_SMD_RPM + select INTERCONNECT_QCOM_SMD_RPM + help + This is a driver for the Qualcomm Network-on-Chip on msm8916-based + platforms. + +config INTERCONNECT_QCOM_MSM8996 + tristate "Qualcomm MSM8996 interconnect driver" + depends on INTERCONNECT_QCOM + depends on QCOM_SMD_RPM + select INTERCONNECT_QCOM_SMD_RPM + help + This is a driver for the Qualcomm Network-on-Chip on msm8996-based + platforms. diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index 1c1cea690f92..dc2f8b99a958 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -1,5 +1,11 @@ # SPDX-License-Identifier: GPL-2.0 qnoc-sdm845-objs := sdm845.o +qnoc-smd-rpm-objs := smd-rpm.o +qnoc-msm8916-objs := msm8916.o +qnoc-msm8996-objs := msm8996.o obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o +obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += qnoc-smd-rpm.o +obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o +obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) += qnoc-msm8996.o diff --git a/drivers/interconnect/qcom/msm8916.c b/drivers/interconnect/qcom/msm8916.c new file mode 100644 index 000000000000..43963e978f5d --- /dev/null +++ b/drivers/interconnect/qcom/msm8916.c @@ -0,0 +1,517 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Linaro Ltd + * Author: Georgi Djakov <georgi.djakov@linaro.org> + */ + +#include <dt-bindings/interconnect/qcom,msm8916.h> +#include <linux/clk.h> +#include <linux/device.h> +#include <linux/interconnect-provider.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include "msm8916_ids.h" +#include "smd-rpm.h" + +#define RPM_BUS_MASTER_REQ 0x73616d62 +#define RPM_BUS_SLAVE_REQ 0x766c7362 + +#define to_qcom_provider(_provider) \ + container_of(_provider, struct qcom_icc_provider, provider) + +enum qcom_qos_mode { + QCOM_QOS_MODE_BYPASS = 0, + QCOM_QOS_MODE_FIXED, + QCOM_QOS_MODE_MAX, +}; + +struct qcom_icc_provider { + struct icc_provider provider; + void __iomem *base; + struct clk *bus_clk; + struct clk *bus_a_clk; +}; + +#define MSM8916_MAX_LINKS 8 + +/** + * struct qcom_icc_node - Qualcomm specific interconnect nodes + * @name: the node name used in debugfs + * @id: a unique node identifier + * @links: an array of nodes where we can go next while traversing + * @num_links: the total number of @links + * @port: the offset index into the masters QoS register space + * @buswidth: width of the interconnect between a node and the bus (bytes) + * @ap_owned: the AP CPU does the writing to QoS registers + * @qos_mode: QoS mode for ap_owned resources + * @mas_rpm_id: RPM id for devices that are bus masters + * @slv_rpm_id: RPM id for devices that are bus slaves + * @rate: current bus clock rate in Hz + */ +struct qcom_icc_node { + unsigned char *name; + u16 id; + u16 links[MSM8916_MAX_LINKS]; + u16 num_links; + u16 port; + u16 buswidth; + bool ap_owned; + enum qcom_qos_mode qos_mode; + int mas_rpm_id; + int slv_rpm_id; + u64 rate; +}; + +struct qcom_icc_desc { + struct qcom_icc_node **nodes; + size_t num_nodes; +}; + +#define DEFINE_QNODE(_name, _id, _port, _buswidth, _ap_owned, \ + _mas_rpm_id, _slv_rpm_id, _qos_mode, \ + _numlinks, ...) \ + static struct qcom_icc_node _name = { \ + .name = #_name, \ + .id = _id, \ + .port = _port, \ + .buswidth = _buswidth, \ + .ap_owned = _ap_owned, \ + .mas_rpm_id = _mas_rpm_id, \ + .slv_rpm_id = _slv_rpm_id, \ + .qos_mode = _qos_mode, \ + .num_links = _numlinks, \ + .links = { __VA_ARGS__ }, \ + } + +DEFINE_QNODE(bimc_snoc_mas, MSM8916_BIMC_SNOC_MAS, 0, 8, 1, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_BIMC_SNOC_SLV); +DEFINE_QNODE(bimc_snoc_slv, MSM8916_BIMC_SNOC_SLV, 0, 8, 1, -1, -1, QCOM_QOS_MODE_FIXED, 2, MSM8916_SNOC_INT_0, MSM8916_SNOC_INT_1); +DEFINE_QNODE(mas_apss, MSM8916_MASTER_AMPSS_M0, 0, 8, 1, -1, -1, QCOM_QOS_MODE_FIXED, 3, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2); +DEFINE_QNODE(mas_audio, MSM8916_MASTER_LPASS, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_PNOC_MAS_0); +DEFINE_QNODE(mas_blsp_1, MSM8916_MASTER_BLSP_1, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_PNOC_MAS_1); +DEFINE_QNODE(mas_dehr, MSM8916_MASTER_DEHR, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_PNOC_MAS_0); +DEFINE_QNODE(mas_gfx, MSM8916_MASTER_GRAPHICS_3D, 2, 8, 1, -1, -1, QCOM_QOS_MODE_FIXED, 3, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2); +DEFINE_QNODE(mas_jpeg, MSM8916_MASTER_JPEG, 6, 16, 1, -1, -1, QCOM_QOS_MODE_BYPASS, 2, MSM8916_SNOC_MM_INT_0, MSM8916_SNOC_MM_INT_2); +DEFINE_QNODE(mas_mdp, MSM8916_MASTER_MDP_PORT0, 7, 16, 1, -1, -1, QCOM_QOS_MODE_BYPASS, 2, MSM8916_SNOC_MM_INT_0, MSM8916_SNOC_MM_INT_2); +DEFINE_QNODE(mas_pnoc_crypto_0, MSM8916_MASTER_CRYPTO_CORE0, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_PNOC_INT_1); +DEFINE_QNODE(mas_pnoc_sdcc_1, MSM8916_MASTER_SDCC_1, 7, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_PNOC_INT_1); +DEFINE_QNODE(mas_pnoc_sdcc_2, MSM8916_MASTER_SDCC_2, 8, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_PNOC_INT_1); +DEFINE_QNODE(mas_qdss_bam, MSM8916_MASTER_QDSS_BAM, 11, 8, 1, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_SNOC_QDSS_INT); +DEFINE_QNODE(mas_qdss_etr, MSM8916_MASTER_QDSS_ETR, 10, 8, 1, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_SNOC_QDSS_INT); +DEFINE_QNODE(mas_snoc_cfg, MSM8916_MASTER_SNOC_CFG, 0, 4, 0, 20, -1, QCOM_QOS_MODE_BYPASS, 1, MSM8916_SNOC_QDSS_INT); +DEFINE_QNODE(mas_spdm, MSM8916_MASTER_SPDM, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_PNOC_MAS_0); +DEFINE_QNODE(mas_tcu0, MSM8916_MASTER_TCU0, 5, 8, 1, -1, -1, QCOM_QOS_MODE_FIXED, 3, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2); +DEFINE_QNODE(mas_tcu1, MSM8916_MASTER_TCU1, 6, 8, 1, -1, -1, QCOM_QOS_MODE_FIXED, 3, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2); +DEFINE_QNODE(mas_usb_hs, MSM8916_MASTER_USB_HS, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_PNOC_MAS_1); +DEFINE_QNODE(mas_vfe, MSM8916_MASTER_VFE, 9, 16, 1, -1, -1, QCOM_QOS_MODE_BYPASS, 2, MSM8916_SNOC_MM_INT_1, MSM8916_SNOC_MM_INT_2); +DEFINE_QNODE(mas_video, MSM8916_MASTER_VIDEO_P0, 8, 16, 1, -1, -1, QCOM_QOS_MODE_BYPASS, 2, MSM8916_SNOC_MM_INT_0, MSM8916_SNOC_MM_INT_2); +DEFINE_QNODE(mm_int_0, MSM8916_SNOC_MM_INT_0, 0, 16, 1, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_SNOC_MM_INT_BIMC); +DEFINE_QNODE(mm_int_1, MSM8916_SNOC_MM_INT_1, 0, 16, 1, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_SNOC_MM_INT_BIMC); +DEFINE_QNODE(mm_int_2, MSM8916_SNOC_MM_INT_2, 0, 16, 1, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_SNOC_INT_0); +DEFINE_QNODE(mm_int_bimc, MSM8916_SNOC_MM_INT_BIMC, 0, 16, 1, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_SNOC_BIMC_1_MAS); +DEFINE_QNODE(pnoc_int_0, MSM8916_PNOC_INT_0, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 8, MSM8916_PNOC_SNOC_MAS, MSM8916_PNOC_SLV_0, MSM8916_PNOC_SLV_1, MSM8916_PNOC_SLV_2, MSM8916_PNOC_SLV_3, MSM8916_PNOC_SLV_4, MSM8916_PNOC_SLV_8, MSM8916_PNOC_SLV_9); +DEFINE_QNODE(pnoc_int_1, MSM8916_PNOC_INT_1, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_PNOC_SNOC_MAS); +DEFINE_QNODE(pnoc_m_0, MSM8916_PNOC_MAS_0, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_PNOC_INT_0); +DEFINE_QNODE(pnoc_m_1, MSM8916_PNOC_MAS_1, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_PNOC_SNOC_MAS); +DEFINE_QNODE(pnoc_s_0, MSM8916_PNOC_SLV_0, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 5, MSM8916_SLAVE_CLK_CTL, MSM8916_SLAVE_TLMM, MSM8916_SLAVE_TCSR, MSM8916_SLAVE_SECURITY, MSM8916_SLAVE_MSS); +DEFINE_QNODE(pnoc_s_1, MSM8916_PNOC_SLV_1, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 5, MSM8916_SLAVE_IMEM_CFG, MSM8916_SLAVE_CRYPTO_0_CFG, MSM8916_SLAVE_MSG_RAM, MSM8916_SLAVE_PDM, MSM8916_SLAVE_PRNG); +DEFINE_QNODE(pnoc_s_2, MSM8916_PNOC_SLV_2, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 5, MSM8916_SLAVE_SPDM, MSM8916_SLAVE_BOOT_ROM, MSM8916_SLAVE_BIMC_CFG, MSM8916_SLAVE_PNOC_CFG, MSM8916_SLAVE_PMIC_ARB); +DEFINE_QNODE(pnoc_s_3, MSM8916_PNOC_SLV_3, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 5, MSM8916_SLAVE_MPM, MSM8916_SLAVE_SNOC_CFG, MSM8916_SLAVE_RBCPR_CFG, MSM8916_SLAVE_QDSS_CFG, MSM8916_SLAVE_DEHR_CFG); +DEFINE_QNODE(pnoc_s_4, MSM8916_PNOC_SLV_4, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 3, MSM8916_SLAVE_VENUS_CFG, MSM8916_SLAVE_CAMERA_CFG, MSM8916_SLAVE_DISPLAY_CFG); +DEFINE_QNODE(pnoc_s_8, MSM8916_PNOC_SLV_8, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 3, MSM8916_SLAVE_USB_HS, MSM8916_SLAVE_SDCC_1, MSM8916_SLAVE_BLSP_1); +DEFINE_QNODE(pnoc_s_9, MSM8916_PNOC_SLV_9, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 3, MSM8916_SLAVE_SDCC_2, MSM8916_SLAVE_LPASS, MSM8916_SLAVE_GRAPHICS_3D_CFG); +DEFINE_QNODE(pnoc_snoc_mas, MSM8916_PNOC_SNOC_MAS, 0, 8, 0, 29, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_PNOC_SNOC_SLV); +DEFINE_QNODE(pnoc_snoc_slv, MSM8916_PNOC_SNOC_SLV, 0, 8, 0, -1, 45, QCOM_QOS_MODE_FIXED, 3, MSM8916_SNOC_INT_0, MSM8916_SNOC_INT_BIMC, MSM8916_SNOC_INT_1); +DEFINE_QNODE(qdss_int, MSM8916_SNOC_QDSS_INT, 0, 8, 1, -1, -1, QCOM_QOS_MODE_FIXED, 2, MSM8916_SNOC_INT_0, MSM8916_SNOC_INT_BIMC); +DEFINE_QNODE(slv_apps_l2, MSM8916_SLAVE_AMPSS_L2, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_apss, MSM8916_SLAVE_APSS, 0, 4, 0, -1, 20, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_audio, MSM8916_SLAVE_LPASS, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_bimc_cfg, MSM8916_SLAVE_BIMC_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_blsp_1, MSM8916_SLAVE_BLSP_1, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_boot_rom, MSM8916_SLAVE_BOOT_ROM, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_camera_cfg, MSM8916_SLAVE_CAMERA_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_cats_0, MSM8916_SLAVE_CATS_128, 0, 16, 0, -1, 106, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_cats_1, MSM8916_SLAVE_OCMEM_64, 0, 8, 0, -1, 107, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_clk_ctl, MSM8916_SLAVE_CLK_CTL, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_crypto_0_cfg, MSM8916_SLAVE_CRYPTO_0_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_dehr_cfg, MSM8916_SLAVE_DEHR_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_display_cfg, MSM8916_SLAVE_DISPLAY_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_ebi_ch0, MSM8916_SLAVE_EBI_CH0, 0, 8, 0, -1, 0, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_gfx_cfg, MSM8916_SLAVE_GRAPHICS_3D_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_imem_cfg, MSM8916_SLAVE_IMEM_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_imem, MSM8916_SLAVE_IMEM, 0, 8, 0, -1, 26, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_mpm, MSM8916_SLAVE_MPM, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_msg_ram, MSM8916_SLAVE_MSG_RAM, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_mss, MSM8916_SLAVE_MSS, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_pdm, MSM8916_SLAVE_PDM, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_pmic_arb, MSM8916_SLAVE_PMIC_ARB, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_pnoc_cfg, MSM8916_SLAVE_PNOC_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_prng, MSM8916_SLAVE_PRNG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_qdss_cfg, MSM8916_SLAVE_QDSS_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_qdss_stm, MSM8916_SLAVE_QDSS_STM, 0, 4, 0, -1, 30, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_rbcpr_cfg, MSM8916_SLAVE_RBCPR_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_sdcc_1, MSM8916_SLAVE_SDCC_1, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_sdcc_2, MSM8916_SLAVE_SDCC_2, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_security, MSM8916_SLAVE_SECURITY, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_snoc_cfg, MSM8916_SLAVE_SNOC_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_spdm, MSM8916_SLAVE_SPDM, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_srvc_snoc, MSM8916_SLAVE_SRVC_SNOC, 0, 8, 0, -1, 29, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_tcsr, MSM8916_SLAVE_TCSR, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_tlmm, MSM8916_SLAVE_TLMM, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_usb_hs, MSM8916_SLAVE_USB_HS, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_venus_cfg, MSM8916_SLAVE_VENUS_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(snoc_bimc_0_mas, MSM8916_SNOC_BIMC_0_MAS, 0, 8, 0, 3, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_SNOC_BIMC_0_SLV); +DEFINE_QNODE(snoc_bimc_0_slv, MSM8916_SNOC_BIMC_0_SLV, 0, 8, 0, -1, 24, QCOM_QOS_MODE_FIXED, 1, MSM8916_SLAVE_EBI_CH0); +DEFINE_QNODE(snoc_bimc_1_mas, MSM8916_SNOC_BIMC_1_MAS, 0, 16, 1, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_SNOC_BIMC_1_SLV); +DEFINE_QNODE(snoc_bimc_1_slv, MSM8916_SNOC_BIMC_1_SLV, 0, 8, 1, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_SLAVE_EBI_CH0); +DEFINE_QNODE(snoc_int_0, MSM8916_SNOC_INT_0, 0, 8, 0, 99, 130, QCOM_QOS_MODE_FIXED, 3, MSM8916_SLAVE_QDSS_STM, MSM8916_SLAVE_IMEM, MSM8916_SNOC_PNOC_MAS); +DEFINE_QNODE(snoc_int_1, MSM8916_SNOC_INT_1, 0, 8, 0, 100, 131, QCOM_QOS_MODE_FIXED, 3, MSM8916_SLAVE_APSS, MSM8916_SLAVE_CATS_128, MSM8916_SLAVE_OCMEM_64); +DEFINE_QNODE(snoc_int_bimc, MSM8916_SNOC_INT_BIMC, 0, 8, 0, 101, 132, QCOM_QOS_MODE_FIXED, 1, MSM8916_SNOC_BIMC_0_MAS); +DEFINE_QNODE(snoc_pnoc_mas, MSM8916_SNOC_PNOC_MAS, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_SNOC_PNOC_SLV); +DEFINE_QNODE(snoc_pnoc_slv, MSM8916_SNOC_PNOC_SLV, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, MSM8916_PNOC_INT_0); + +static struct qcom_icc_node *msm8916_snoc_nodes[] = { + [BIMC_SNOC_SLV] = &bimc_snoc_slv, + [MASTER_JPEG] = &mas_jpeg, + [MASTER_MDP_PORT0] = &mas_mdp, + [MASTER_QDSS_BAM] = &mas_qdss_bam, + [MASTER_QDSS_ETR] = &mas_qdss_etr, + [MASTER_SNOC_CFG] = &mas_snoc_cfg, + [MASTER_VFE] = &mas_vfe, + [MASTER_VIDEO_P0] = &mas_video, + [SNOC_MM_INT_0] = &mm_int_0, + [SNOC_MM_INT_1] = &mm_int_1, + [SNOC_MM_INT_2] = &mm_int_2, + [SNOC_MM_INT_BIMC] = &mm_int_bimc, + [PNOC_SNOC_SLV] = &pnoc_snoc_slv, + [SLAVE_APSS] = &slv_apss, + [SLAVE_CATS_128] = &slv_cats_0, + [SLAVE_OCMEM_64] = &slv_cats_1, + [SLAVE_IMEM] = &slv_imem, + [SLAVE_QDSS_STM] = &slv_qdss_stm, + [SLAVE_SRVC_SNOC] = &slv_srvc_snoc, + [SNOC_BIMC_0_MAS] = &snoc_bimc_0_mas, + [SNOC_BIMC_1_MAS] = &snoc_bimc_1_mas, + [SNOC_INT_0] = &snoc_int_0, + [SNOC_INT_1] = &snoc_int_1, + [SNOC_INT_BIMC] = &snoc_int_bimc, + [SNOC_PNOC_MAS] = &snoc_pnoc_mas, + [SNOC_QDSS_INT] = &qdss_int, +}; + +static struct qcom_icc_desc msm8916_snoc = { + .nodes = msm8916_snoc_nodes, + .num_nodes = ARRAY_SIZE(msm8916_snoc_nodes), +}; + +static struct qcom_icc_node *msm8916_bimc_nodes[] = { + [BIMC_SNOC_MAS] = &bimc_snoc_mas, + [MASTER_AMPSS_M0] = &mas_apss, + [MASTER_GRAPHICS_3D] = &mas_gfx, + [MASTER_TCU0] = &mas_tcu0, + [MASTER_TCU1] = &mas_tcu1, + [SLAVE_AMPSS_L2] = &slv_apps_l2, + [SLAVE_EBI_CH0] = &slv_ebi_ch0, + [SNOC_BIMC_0_SLV] = &snoc_bimc_0_slv, + [SNOC_BIMC_1_SLV] = &snoc_bimc_1_slv, +}; + +static struct qcom_icc_desc msm8916_bimc = { + .nodes = msm8916_bimc_nodes, + .num_nodes = ARRAY_SIZE(msm8916_bimc_nodes), +}; + +static struct qcom_icc_node *msm8916_pnoc_nodes[] = { + [MASTER_BLSP_1] = &mas_blsp_1, + [MASTER_DEHR] = &mas_dehr, + [MASTER_LPASS] = &mas_audio, + [MASTER_CRYPTO_CORE0] = &mas_pnoc_crypto_0, + [MASTER_SDCC_1] = &mas_pnoc_sdcc_1, + [MASTER_SDCC_2] = &mas_pnoc_sdcc_2, + [MASTER_SPDM] = &mas_spdm, + [MASTER_USB_HS] = &mas_usb_hs, + [PNOC_INT_0] = &pnoc_int_0, + [PNOC_INT_1] = &pnoc_int_1, + [PNOC_MAS_0] = &pnoc_m_0, + [PNOC_MAS_1] = &pnoc_m_1, + [PNOC_SLV_0] = &pnoc_s_0, + [PNOC_SLV_1] = &pnoc_s_1, + [PNOC_SLV_2] = &pnoc_s_2, + [PNOC_SLV_3] = &pnoc_s_3, + [PNOC_SLV_4] = &pnoc_s_4, + [PNOC_SLV_8] = &pnoc_s_8, + [PNOC_SLV_9] = &pnoc_s_9, + [PNOC_SNOC_MAS] = &pnoc_snoc_mas, + [SLAVE_BIMC_CFG] = &slv_bimc_cfg, + [SLAVE_BLSP_1] = &slv_blsp_1, + [SLAVE_BOOT_ROM] = &slv_boot_rom, + [SLAVE_CAMERA_CFG] = &slv_camera_cfg, + [SLAVE_CLK_CTL] = &slv_clk_ctl, + [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg, + [SLAVE_DEHR_CFG] = &slv_dehr_cfg, + [SLAVE_DISPLAY_CFG] = &slv_display_cfg, + [SLAVE_GRAPHICS_3D_CFG] = &slv_gfx_cfg, + [SLAVE_IMEM_CFG] = &slv_imem_cfg, + [SLAVE_LPASS] = &slv_audio, + [SLAVE_MPM] = &slv_mpm, + [SLAVE_MSG_RAM] = &slv_msg_ram, + [SLAVE_MSS] = &slv_mss, + [SLAVE_PDM] = &slv_pdm, + [SLAVE_PMIC_ARB] = &slv_pmic_arb, + [SLAVE_PNOC_CFG] = &slv_pnoc_cfg, + [SLAVE_PRNG] = &slv_prng, + [SLAVE_QDSS_CFG] = &slv_qdss_cfg, + [SLAVE_RBCPR_CFG] = &slv_rbcpr_cfg, + [SLAVE_SDCC_1] = &slv_sdcc_1, + [SLAVE_SDCC_2] = &slv_sdcc_2, + [SLAVE_SECURITY] = &slv_security, + [SLAVE_SNOC_CFG] = &slv_snoc_cfg, + [SLAVE_SPDM] = &slv_spdm, + [SLAVE_TCSR] = &slv_tcsr, + [SLAVE_TLMM] = &slv_tlmm, + [SLAVE_USB_HS] = &slv_usb_hs, + [SLAVE_VENUS_CFG] = &slv_venus_cfg, + [SNOC_PNOC_SLV] = &snoc_pnoc_slv, +}; + +static struct qcom_icc_desc msm8916_pnoc = { + .nodes = msm8916_pnoc_nodes, + .num_nodes = ARRAY_SIZE(msm8916_pnoc_nodes), +}; + +static int qcom_icc_aggregate(struct icc_node *node, u8 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + *agg_avg += avg_bw; + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct qcom_icc_provider *qp; + struct qcom_icc_node *qn; + struct icc_provider *provider; + struct icc_node *n; + u64 sum_bw; + u64 max_peak_bw; + u64 rate; + u32 agg_avg = 0; + u32 agg_peak = 0; + int ret = 0; + + qn = src->data; + provider = src->provider; + qp = to_qcom_provider(provider); + + list_for_each_entry(n, &provider->nodes, node_list) + qcom_icc_aggregate(n, 0, n->avg_bw, n->peak_bw, + &agg_avg, &agg_peak); + + sum_bw = icc_units_to_bps(agg_avg); + max_peak_bw = icc_units_to_bps(agg_peak); + + /* set bandwidth */ + if (qn->ap_owned) { + /* TODO: set QoS */ + } else { + /* send message to the RPM processor */ + if (qn->mas_rpm_id != -1) { + ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, + RPM_BUS_MASTER_REQ, + qn->mas_rpm_id, + sum_bw); + if (ret) { + pr_err("qcom_icc_rpm_smd_send mas %d error %d\n", qn->mas_rpm_id, ret); + return ret; + } + } + + if (qn->slv_rpm_id != -1) { + ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, + RPM_BUS_SLAVE_REQ, + qn->slv_rpm_id, + sum_bw); + if (ret) { + pr_err("qcom_icc_rpm_smd_send slv error %d\n", + ret); + return ret; + } + } + } + + rate = max(sum_bw, max_peak_bw); + + do_div(rate, qn->buswidth); + + if (qn->rate != rate) { + ret = clk_set_rate(qp->bus_clk, rate); + if (ret) { + pr_err("set clk rate %lld error %d\n", rate, ret); + return ret; + } + + ret = clk_set_rate(qp->bus_a_clk, rate); + if (ret) { + pr_err("set clk rate %lld error %d\n", rate, ret); + return ret; + } + + qn->rate = rate; + } + + return ret; +} + +static int qnoc_probe(struct platform_device *pdev) +{ + const struct qcom_icc_desc *desc; + struct icc_onecell_data *data; + struct icc_provider *provider; + struct qcom_icc_node **qnodes; + struct qcom_icc_provider *qp; + struct icc_node *node; + struct resource *res; + size_t num_nodes, i; + int ret; + + /* wait for RPM */ + if (!qcom_icc_rpm_smd_available()) + return -EPROBE_DEFER; + + desc = of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + qnodes = desc->nodes; + num_nodes = desc->num_nodes; + + qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL); + if (!qp) + return -ENOMEM; + + data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL); + if (!data) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + qp->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(qp->base)) + return PTR_ERR(qp->base); + + qp->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); + if (IS_ERR(qp->bus_clk)) + return PTR_ERR(qp->bus_clk); + + ret = clk_prepare_enable(qp->bus_clk); + if (ret) { + dev_err(&pdev->dev, "error enabling bus_clk: %d\n", ret); + return ret; + } + + qp->bus_a_clk = devm_clk_get(&pdev->dev, "bus_a_clk"); + if (IS_ERR(qp->bus_a_clk)) + return PTR_ERR(qp->bus_a_clk); + + ret = clk_prepare_enable(qp->bus_a_clk); + if (ret) { + dev_err(&pdev->dev, "error enabling bus_a_clk: %d\n", ret); + clk_disable_unprepare(qp->bus_clk); + return ret; + } + + provider = &qp->provider; + INIT_LIST_HEAD(&provider->nodes); + provider->dev = &pdev->dev; + provider->set = qcom_icc_set; + provider->aggregate = qcom_icc_aggregate; + provider->xlate = of_icc_xlate_onecell; + provider->data = data; + + ret = icc_provider_add(provider); + if (ret) { + dev_err(&pdev->dev, "error adding interconnect provider\n"); + clk_disable_unprepare(qp->bus_clk); + clk_disable_unprepare(qp->bus_a_clk); + return ret; + } + + for (i = 0; i < num_nodes; i++) { + size_t j; + + node = icc_node_create(qnodes[i]->id); + if (IS_ERR(node)) { + ret = PTR_ERR(node); + goto err; + } + + node->name = qnodes[i]->name; + node->data = qnodes[i]; + icc_node_add(node, provider); + + dev_dbg(&pdev->dev, "registered node %s\n", node->name); + + /* populate links */ + for (j = 0; j < qnodes[i]->num_links; j++) + icc_link_create(node, qnodes[i]->links[j]); + + data->nodes[i] = node; + } + data->num_nodes = num_nodes; + + platform_set_drvdata(pdev, qp); + + return ret; +err: + list_for_each_entry(node, &provider->nodes, node_list) { + icc_node_del(node); + icc_node_destroy(node->id); + } + clk_disable_unprepare(qp->bus_clk); + clk_disable_unprepare(qp->bus_a_clk); + icc_provider_del(provider); + + return ret; +} + +static int qnoc_remove(struct platform_device *pdev) +{ + struct qcom_icc_provider *qp = platform_get_drvdata(pdev); + struct icc_provider *provider = &qp->provider; + struct icc_node *n; + + list_for_each_entry(n, &provider->nodes, node_list) { + icc_node_del(n); + icc_node_destroy(n->id); + } + clk_disable_unprepare(qp->bus_clk); + clk_disable_unprepare(qp->bus_a_clk); + + return icc_provider_del(provider); +} + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,msm8916-pnoc", .data = &msm8916_pnoc }, + { .compatible = "qcom,msm8916-snoc", .data = &msm8916_snoc }, + { .compatible = "qcom,msm8916-bimc", .data = &msm8916_bimc }, + { }, +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qnoc_probe, + .remove = qnoc_remove, + .driver = { + .name = "qnoc-msm8916", + .of_match_table = qnoc_of_match, + }, +}; +module_platform_driver(qnoc_driver); +MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>"); +MODULE_DESCRIPTION("Qualcomm msm8916 NoC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/qcom/msm8916_ids.h b/drivers/interconnect/qcom/msm8916_ids.h new file mode 100644 index 000000000000..44963e005950 --- /dev/null +++ b/drivers/interconnect/qcom/msm8916_ids.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Qualcomm MSM8916 interconnect IDs + * + * Copyright (c) 2018, Linaro Ltd. + * Author: Georgi Djakov <georgi.djakov@linaro.org> + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_MSM8916_H +#define __DRIVERS_INTERCONNECT_QCOM_MSM8916_H + +#define MSM8916_BIMC_SNOC_MAS 0 +#define MSM8916_BIMC_SNOC_SLV 1 +#define MSM8916_MASTER_AMPSS_M0 2 +#define MSM8916_MASTER_LPASS 3 +#define MSM8916_MASTER_BLSP_1 4 +#define MSM8916_MASTER_DEHR 5 +#define MSM8916_MASTER_GRAPHICS_3D 6 +#define MSM8916_MASTER_JPEG 7 +#define MSM8916_MASTER_MDP_PORT0 8 +#define MSM8916_MASTER_CRYPTO_CORE0 9 +#define MSM8916_MASTER_SDCC_1 10 +#define MSM8916_MASTER_SDCC_2 11 +#define MSM8916_MASTER_QDSS_BAM 12 +#define MSM8916_MASTER_QDSS_ETR 13 +#define MSM8916_MASTER_SNOC_CFG 14 +#define MSM8916_MASTER_SPDM 15 +#define MSM8916_MASTER_TCU0 16 +#define MSM8916_MASTER_TCU1 17 +#define MSM8916_MASTER_USB_HS 18 +#define MSM8916_MASTER_VFE 19 +#define MSM8916_MASTER_VIDEO_P0 20 +#define MSM8916_SNOC_MM_INT_0 21 +#define MSM8916_SNOC_MM_INT_1 22 +#define MSM8916_SNOC_MM_INT_2 23 +#define MSM8916_SNOC_MM_INT_BIMC 24 +#define MSM8916_PNOC_INT_0 25 +#define MSM8916_PNOC_INT_1 26 +#define MSM8916_PNOC_MAS_0 27 +#define MSM8916_PNOC_MAS_1 28 +#define MSM8916_PNOC_SLV_0 29 +#define MSM8916_PNOC_SLV_1 30 +#define MSM8916_PNOC_SLV_2 31 +#define MSM8916_PNOC_SLV_3 32 +#define MSM8916_PNOC_SLV_4 33 +#define MSM8916_PNOC_SLV_8 34 +#define MSM8916_PNOC_SLV_9 35 +#define MSM8916_PNOC_SNOC_MAS 36 +#define MSM8916_PNOC_SNOC_SLV 37 +#define MSM8916_SNOC_QDSS_INT 38 +#define MSM8916_SLAVE_AMPSS_L2 39 +#define MSM8916_SLAVE_APSS 40 +#define MSM8916_SLAVE_LPASS 41 +#define MSM8916_SLAVE_BIMC_CFG 42 +#define MSM8916_SLAVE_BLSP_1 43 +#define MSM8916_SLAVE_BOOT_ROM 44 +#define MSM8916_SLAVE_CAMERA_CFG 45 +#define MSM8916_SLAVE_CATS_128 46 +#define MSM8916_SLAVE_OCMEM_64 47 +#define MSM8916_SLAVE_CLK_CTL 48 +#define MSM8916_SLAVE_CRYPTO_0_CFG 49 +#define MSM8916_SLAVE_DEHR_CFG 50 +#define MSM8916_SLAVE_DISPLAY_CFG 51 +#define MSM8916_SLAVE_EBI_CH0 52 +#define MSM8916_SLAVE_GRAPHICS_3D_CFG 53 +#define MSM8916_SLAVE_IMEM_CFG 54 +#define MSM8916_SLAVE_IMEM 55 +#define MSM8916_SLAVE_MPM 56 +#define MSM8916_SLAVE_MSG_RAM 57 +#define MSM8916_SLAVE_MSS 58 +#define MSM8916_SLAVE_PDM 59 +#define MSM8916_SLAVE_PMIC_ARB 60 +#define MSM8916_SLAVE_PNOC_CFG 61 +#define MSM8916_SLAVE_PRNG 62 +#define MSM8916_SLAVE_QDSS_CFG 63 +#define MSM8916_SLAVE_QDSS_STM 64 +#define MSM8916_SLAVE_RBCPR_CFG 65 +#define MSM8916_SLAVE_SDCC_1 66 +#define MSM8916_SLAVE_SDCC_2 67 +#define MSM8916_SLAVE_SECURITY 68 +#define MSM8916_SLAVE_SNOC_CFG 69 +#define MSM8916_SLAVE_SPDM 70 +#define MSM8916_SLAVE_SRVC_SNOC 71 +#define MSM8916_SLAVE_TCSR 72 +#define MSM8916_SLAVE_TLMM 73 +#define MSM8916_SLAVE_USB_HS 74 +#define MSM8916_SLAVE_VENUS_CFG 75 +#define MSM8916_SNOC_BIMC_0_MAS 76 +#define MSM8916_SNOC_BIMC_0_SLV 77 +#define MSM8916_SNOC_BIMC_1_MAS 78 +#define MSM8916_SNOC_BIMC_1_SLV 79 +#define MSM8916_SNOC_INT_0 80 +#define MSM8916_SNOC_INT_1 81 +#define MSM8916_SNOC_INT_BIMC 82 +#define MSM8916_SNOC_PNOC_MAS 83 +#define MSM8916_SNOC_PNOC_SLV 84 + +#endif diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c new file mode 100644 index 000000000000..c7998281fb87 --- /dev/null +++ b/drivers/interconnect/qcom/msm8996.c @@ -0,0 +1,666 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Linaro Ltd + * Author: Georgi Djakov <georgi.djakov@linaro.org> + */ + +#include <dt-bindings/interconnect/qcom,msm8996.h> +#include <linux/clk.h> +#include <linux/device.h> +#include <linux/interconnect-provider.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include "msm8996_ids.h" +#include "smd-rpm.h" + +#define RPM_MASTER_FIELD_BW 0x00007762 +#define RPM_BUS_MASTER_REQ 0x73616d62 +#define RPM_BUS_SLAVE_REQ 0x766c7362 + +#define to_qcom_provider(_provider) \ + container_of(_provider, struct qcom_icc_provider, provider) + +enum qcom_qos_mode { + QCOM_QOS_MODE_BYPASS = 0, + QCOM_QOS_MODE_FIXED, + QCOM_QOS_MODE_MAX, +}; + +struct qcom_icc_provider { + struct icc_provider provider; + void __iomem *base; + struct clk *bus_clk; + struct clk *bus_a_clk; +}; + +#define MSM8996_MAX_LINKS 38 + +/** + * struct qcom_icc_node - Qualcomm specific interconnect nodes + * @name: the node name used in debugfs + * @id: a unique node identifier + * @links: an array of nodes where we can go next while traversing + * @num_links: the total number of @links + * @port: the offset index into the masters QoS register space + * @agg_ports: the number of aggregation ports on the bus + * @buswidth: width of the interconnect between a node and the bus (bytes) + * @ap_owned: the AP CPU does the writing to QoS registers + * @qos_mode: QoS mode for ap_owned resources + * @mas_rpm_id: RPM id for devices that are bus masters + * @slv_rpm_id: RPM id for devices that are bus slaves + * @rate: current bus clock rate in Hz + */ +struct qcom_icc_node { + unsigned char *name; + u16 id; + u16 links[MSM8996_MAX_LINKS]; + u16 num_links; + u16 port; + u16 agg_ports; + u16 buswidth; + bool ap_owned; + enum qcom_qos_mode qos_mode; + int mas_rpm_id; + int slv_rpm_id; + u64 rate; +}; + +struct qcom_icc_desc { + struct qcom_icc_node **nodes; + size_t num_nodes; +}; + +#define DEFINE_QNODE(_name, _id, _port, _agg_ports, _buswidth, \ + _qos_mode, _ap_owned, _mas_rpm_id, _slv_rpm_id, \ + _numlinks, ...) \ + static struct qcom_icc_node _name = { \ + .name = #_name, \ + .id = _id, \ + .port = _port, \ + .agg_ports = _agg_ports, \ + .buswidth = _buswidth, \ + .qos_mode = _qos_mode, \ + .ap_owned = _ap_owned, \ + .mas_rpm_id = _mas_rpm_id, \ + .slv_rpm_id = _slv_rpm_id, \ + .num_links = _numlinks, \ + .links = { __VA_ARGS__ }, \ + } + +DEFINE_QNODE(mas_a0noc_snoc, MSM8996_A0NOC_SNOC_MAS, 0, 1, 16, QCOM_QOS_MODE_FIXED, 1, 110, -1, 5, MSM8996_SNOC_PNOC_SLV, MSM8996_SLAVE_OCIMEM, MSM8996_SLAVE_APPSS, MSM8996_SNOC_BIMC_SLV, MSM8996_SLAVE_PIMEM); +DEFINE_QNODE(mas_a1noc_snoc, MSM8996_A1NOC_SNOC_MAS, 0, 1, 16, QCOM_QOS_MODE_FIXED, 0, 111, -1, 13, MSM8996_SLAVE_SNOC_VMEM, MSM8996_SLAVE_USB3, MSM8996_SLAVE_PCIE_0, MSM8996_SLAVE_PIMEM, MSM8996_SLAVE_PCIE_2, MSM8996_SLAVE_LPASS, MSM8996_SLAVE_PCIE_1, MSM8996_SLAVE_APPSS, MSM8996_SNOC_BIMC_SLV, MSM8996_SNOC_CNOC_SLV, MSM8996_SNOC_PNOC_SLV, MSM8996_SLAVE_OCIMEM, MSM8996_SLAVE_QDSS_STM); +DEFINE_QNODE(mas_a2noc_snoc, MSM8996_A2NOC_SNOC_MAS, 0, 1, 16, QCOM_QOS_MODE_FIXED, 0, 112, -1, 12, MSM8996_SLAVE_SNOC_VMEM, MSM8996_SLAVE_USB3, MSM8996_SLAVE_PCIE_1, MSM8996_SLAVE_PIMEM, MSM8996_SLAVE_PCIE_2, MSM8996_SLAVE_QDSS_STM, MSM8996_SLAVE_LPASS, MSM8996_SNOC_BIMC_SLV, MSM8996_SNOC_CNOC_SLV, MSM8996_SNOC_PNOC_SLV, MSM8996_SLAVE_OCIMEM, MSM8996_SLAVE_PCIE_0); +DEFINE_QNODE(mas_apps_proc, MSM8996_MASTER_AMPSS_M0, 0, 2, 8, QCOM_QOS_MODE_FIXED, 1, 0, -1, 3, MSM8996_BIMC_SNOC_1_SLV, MSM8996_SLAVE_EBI_CH0, MSM8996_BIMC_SNOC_SLV); +DEFINE_QNODE(mas_bimc_snoc_0, MSM8996_BIMC_SNOC_MAS, 0, 1, 16, QCOM_QOS_MODE_FIXED, 1, 21, -1, 9, MSM8996_SLAVE_SNOC_VMEM, MSM8996_SLAVE_USB3, MSM8996_SLAVE_PIMEM, MSM8996_SLAVE_LPASS, MSM8996_SLAVE_APPSS, MSM8996_SNOC_CNOC_SLV, MSM8996_SNOC_PNOC_SLV, MSM8996_SLAVE_OCIMEM, MSM8996_SLAVE_QDSS_STM); +DEFINE_QNODE(mas_bimc_snoc_1, MSM8996_BIMC_SNOC_1_MAS, 0, 1, 16, QCOM_QOS_MODE_FIXED, 1, 109, -1, 3, MSM8996_SLAVE_PCIE_2, MSM8996_SLAVE_PCIE_1, MSM8996_SLAVE_PCIE_0); +DEFINE_QNODE(mas_blsp_1, MSM8996_MASTER_BLSP_1, 0, 1, 4, QCOM_QOS_MODE_BYPASS, 0, 41, -1, 1, MSM8996_PNOC_A1NOC_SLV); +DEFINE_QNODE(mas_blsp_2, MSM8996_MASTER_BLSP_2, 0, 1, 4, QCOM_QOS_MODE_BYPASS, 0, 39, -1, 1, MSM8996_PNOC_A1NOC_SLV); +DEFINE_QNODE(mas_cnoc_a1noc, MSM8996_CNOC_A1NOC_MAS, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, 116, -1, 1, MSM8996_A1NOC_SNOC_SLV); +DEFINE_QNODE(mas_cnoc_mnoc_cfg, MSM8996_MASTER_CNOC_MNOC_CFG, 0, 1, 8, QCOM_QOS_MODE_BYPASS, 1, 5, -1, 1, MSM8996_SLAVE_SERVICE_MNOC); +DEFINE_QNODE(mas_cnoc_mnoc_mmss_cfg, MSM8996_MASTER_CNOC_MNOC_MMSS_CFG, 0, 1, 8, QCOM_QOS_MODE_BYPASS, 1, 4, -1, 21, MSM8996_SLAVE_MMAGIC_CFG, MSM8996_SLAVE_DSA_MPU_CFG, MSM8996_SLAVE_MMSS_CLK_CFG, MSM8996_SLAVE_CAMERA_THROTTLE_CFG, MSM8996_SLAVE_VENUS_CFG, MSM8996_SLAVE_SMMU_VFE_CFG, MSM8996_SLAVE_MISC_CFG, MSM8996_SLAVE_SMMU_CPP_CFG, MSM8996_SLAVE_GRAPHICS_3D_CFG, MSM8996_SLAVE_DISPLAY_THROTTLE_CFG, MSM8996_SLAVE_VENUS_THROTTLE_CFG, MSM8996_SLAVE_CAMERA_CFG, MSM8996_SLAVE_DISPLAY_CFG, MSM8996_SLAVE_CPR_CFG, MSM8996_SLAVE_SMMU_ROTATOR_CFG, MSM8996_SLAVE_DSA_CFG, MSM8996_SLAVE_SMMU_VENUS_CFG, MSM8996_SLAVE_VMEM_CFG, MSM8996_SLAVE_SMMU_JPEG_CFG, MSM8996_SLAVE_SMMU_MDP_CFG, MSM8996_SLAVE_MNOC_MPU_CFG); +DEFINE_QNODE(mas_cpp, MSM8996_MASTER_CPP, 5, 1, 32, QCOM_QOS_MODE_BYPASS, 1, 115, -1, 1, MSM8996_MNOC_BIMC_SLV); +DEFINE_QNODE(mas_crypto_c0, MSM8996_MASTER_CRYPTO_CORE0, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, 23, -1, 1, MSM8996_A1NOC_SNOC_SLV); +DEFINE_QNODE(mas_hmss, MSM8996_MASTER_HMSS, 4, 1, 8, QCOM_QOS_MODE_FIXED, 1, 118, -1, 3, MSM8996_SLAVE_PIMEM, MSM8996_SLAVE_OCIMEM, MSM8996_SNOC_BIMC_SLV); +DEFINE_QNODE(mas_ipa, MSM8996_MASTER_IPA, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, 59, -1, 1, MSM8996_A2NOC_SNOC_SLV); +DEFINE_QNODE(mas_jpeg, MSM8996_MASTER_JPEG, 7, 1, 32, QCOM_QOS_MODE_BYPASS, 1, 7, -1, 1, MSM8996_MNOC_BIMC_SLV); +DEFINE_QNODE(mas_mdp_p0, MSM8996_MASTER_MDP_PORT0, 1, 1, 32, QCOM_QOS_MODE_BYPASS, 1, 8, -1, 1, MSM8996_MNOC_BIMC_SLV); +DEFINE_QNODE(mas_mdp_p1, MSM8996_MASTER_MDP_PORT1, 2, 1, 32, QCOM_QOS_MODE_BYPASS, 1, 61, -1, 1, MSM8996_MNOC_BIMC_SLV); +DEFINE_QNODE(mas_mnoc_bimc, MSM8996_MNOC_BIMC_MAS, 2, 2, 8, QCOM_QOS_MODE_BYPASS, 1, 2, -1, 4, MSM8996_BIMC_SNOC_1_SLV, MSM8996_SLAVE_HMSS_L3, MSM8996_SLAVE_EBI_CH0, MSM8996_BIMC_SNOC_SLV); +DEFINE_QNODE(mas_oxili, MSM8996_MASTER_GRAPHICS_3D, 1, 2, 8, QCOM_QOS_MODE_BYPASS, 1, 6, -1, 4, MSM8996_BIMC_SNOC_1_SLV, MSM8996_SLAVE_HMSS_L3, MSM8996_SLAVE_EBI_CH0, MSM8996_BIMC_SNOC_SLV); +DEFINE_QNODE(mas_pcie_0, MSM8996_MASTER_PCIE, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, 65, -1, 1, MSM8996_A0NOC_SNOC_SLV); +DEFINE_QNODE(mas_pcie_1, MSM8996_MASTER_PCIE_1, 1, 1, 8, QCOM_QOS_MODE_FIXED, 1, 66, -1, 1, MSM8996_A0NOC_SNOC_SLV); +DEFINE_QNODE(mas_pcie_2, MSM8996_MASTER_PCIE_2, 2, 1, 8, QCOM_QOS_MODE_FIXED, 1, 119, -1, 1, MSM8996_A0NOC_SNOC_SLV); +DEFINE_QNODE(mas_pnoc_a1noc, MSM8996_PNOC_A1NOC_MAS, 1, 1, 8, QCOM_QOS_MODE_FIXED, 0, 117, -1, 1, MSM8996_A1NOC_SNOC_SLV); +DEFINE_QNODE(mas_qdss_bam, MSM8996_MASTER_QDSS_BAM, 2, 1, 16, QCOM_QOS_MODE_FIXED, 1, 19, -1, 5, MSM8996_SLAVE_PIMEM, MSM8996_SLAVE_USB3, MSM8996_SLAVE_OCIMEM, MSM8996_SNOC_BIMC_SLV, MSM8996_SNOC_PNOC_SLV); +DEFINE_QNODE(mas_qdss_dap, MSM8996_MASTER_QDSS_DAP, 0, 1, 8, QCOM_QOS_MODE_BYPASS, 1, 49, -1, 38, MSM8996_SLAVE_QDSS_RBCPR_APU_CFG, MSM8996_SLAVE_RBCPR_CX, MSM8996_SLAVE_A2NOC_SMMU_CFG, MSM8996_SLAVE_A0NOC_MPU_CFG, MSM8996_SLAVE_MESSAGE_RAM, MSM8996_SLAVE_PCIE_0_CFG, MSM8996_SLAVE_TLMM, MSM8996_SLAVE_MPM, MSM8996_SLAVE_A0NOC_SMMU_CFG, MSM8996_SLAVE_EBI1_PHY_CFG, MSM8996_SLAVE_BIMC_CFG, MSM8996_SLAVE_PIMEM_CFG, MSM8996_SLAVE_RBCPR_MX, MSM8996_SLAVE_CLK_CTL, MSM8996_SLAVE_PRNG, MSM8996_SLAVE_PCIE20_AHB2PHY, MSM8996_SLAVE_A2NOC_MPU_CFG, MSM8996_SLAVE_QDSS_CFG, MSM8996_SLAVE_A2NOC_CFG, MSM8996_SLAVE_A0NOC_CFG, MSM8996_SLAVE_UFS_CFG, MSM8996_SLAVE_CRYPTO_0_CFG, MSM8996_CNOC_SNOC_SLV, MSM8996_SLAVE_PCIE_1_CFG, MSM8996_SLAVE_SNOC_CFG, MSM8996_SLAVE_SNOC_MPU_CFG, MSM8996_SLAVE_A1NOC_MPU_CFG, MSM8996_SLAVE_A1NOC_SMMU_CFG, MSM8996_SLAVE_PCIE_2_CFG, MSM8996_SLAVE_CNOC_MNOC_CFG, MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG, MSM8996_SLAVE_PMIC_ARB, MSM8996_SLAVE_IMEM_CFG, MSM8996_SLAVE_A1NOC_CFG, MSM8996_SLAVE_SSC_CFG, MSM8996_SLAVE_TCSR, MSM8996_SLAVE_LPASS_SMMU_CFG, MSM8996_SLAVE_DCC_CFG); +DEFINE_QNODE(mas_qdss_etr, MSM8996_MASTER_QDSS_ETR, 3, 1, 16, QCOM_QOS_MODE_FIXED, 1, 31, -1, 5, MSM8996_SLAVE_PIMEM, MSM8996_SLAVE_USB3, MSM8996_SLAVE_OCIMEM, MSM8996_SNOC_BIMC_SLV, MSM8996_SNOC_PNOC_SLV); +DEFINE_QNODE(mas_rotator, MSM8996_MASTER_ROTATOR, 0, 1, 32, QCOM_QOS_MODE_BYPASS, 1, 120, -1, 1, MSM8996_MNOC_BIMC_SLV); +DEFINE_QNODE(mas_sdcc_1, MSM8996_MASTER_SDCC_1, 0, 1, 8, QCOM_QOS_MODE_BYPASS, 0, 33, -1, 1, MSM8996_PNOC_A1NOC_SLV); +DEFINE_QNODE(mas_sdcc_2, MSM8996_MASTER_SDCC_2, 0, 1, 8, QCOM_QOS_MODE_BYPASS, 0, 35, -1, 1, MSM8996_PNOC_A1NOC_SLV); +DEFINE_QNODE(mas_sdcc_4, MSM8996_MASTER_SDCC_4, 0, 1, 8, QCOM_QOS_MODE_BYPASS, 0, 36, -1, 1, MSM8996_PNOC_A1NOC_SLV); +DEFINE_QNODE(mas_snoc_bimc, MSM8996_SNOC_BIMC_MAS, 0, 2, 8, QCOM_QOS_MODE_BYPASS, 0, 3, -1, 2, MSM8996_SLAVE_HMSS_L3, MSM8996_SLAVE_EBI_CH0); +DEFINE_QNODE(mas_snoc_cfg, MSM8996_MASTER_SNOC_CFG, 0, 1, 16, QCOM_QOS_MODE_FIXED, 1, 20, -1, 1, MSM8996_SLAVE_SERVICE_SNOC); +DEFINE_QNODE(mas_snoc_cnoc, MSM8996_SNOC_CNOC_MAS, 0, 1, 8, QCOM_QOS_MODE_BYPASS, 0, 52, -1, 37, MSM8996_SLAVE_CLK_CTL, MSM8996_SLAVE_RBCPR_CX, MSM8996_SLAVE_A2NOC_SMMU_CFG, MSM8996_SLAVE_A0NOC_MPU_CFG, MSM8996_SLAVE_MESSAGE_RAM, MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG, MSM8996_SLAVE_PCIE_0_CFG, MSM8996_SLAVE_TLMM, MSM8996_SLAVE_MPM, MSM8996_SLAVE_A0NOC_SMMU_CFG, MSM8996_SLAVE_EBI1_PHY_CFG, MSM8996_SLAVE_BIMC_CFG, MSM8996_SLAVE_PIMEM_CFG, MSM8996_SLAVE_RBCPR_MX, MSM8996_SLAVE_PRNG, MSM8996_SLAVE_PCIE20_AHB2PHY, MSM8996_SLAVE_A2NOC_MPU_CFG, MSM8996_SLAVE_QDSS_CFG, MSM8996_SLAVE_A2NOC_CFG, MSM8996_SLAVE_A0NOC_CFG, MSM8996_SLAVE_UFS_CFG, MSM8996_SLAVE_CRYPTO_0_CFG, MSM8996_SLAVE_PCIE_1_CFG, MSM8996_SLAVE_SNOC_CFG, MSM8996_SLAVE_SNOC_MPU_CFG, MSM8996_SLAVE_A1NOC_MPU_CFG, MSM8996_SLAVE_A1NOC_SMMU_CFG, MSM8996_SLAVE_PCIE_2_CFG, MSM8996_SLAVE_CNOC_MNOC_CFG, MSM8996_SLAVE_QDSS_RBCPR_APU_CFG, MSM8996_SLAVE_PMIC_ARB, MSM8996_SLAVE_IMEM_CFG, MSM8996_SLAVE_A1NOC_CFG, MSM8996_SLAVE_SSC_CFG, MSM8996_SLAVE_TCSR, MSM8996_SLAVE_LPASS_SMMU_CFG, MSM8996_SLAVE_DCC_CFG); +DEFINE_QNODE(mas_snoc_pnoc, MSM8996_SNOC_PNOC_MAS, 0, 1, 8, QCOM_QOS_MODE_BYPASS, 0, 44, -1, 9, MSM8996_SLAVE_BLSP_1, MSM8996_SLAVE_BLSP_2, MSM8996_SLAVE_USB_HS, MSM8996_SLAVE_SDCC_1, MSM8996_SLAVE_SDCC_2, MSM8996_SLAVE_SDCC_4, MSM8996_SLAVE_TSIF, MSM8996_SLAVE_PDM, MSM8996_SLAVE_AHB2PHY); +DEFINE_QNODE(mas_snoc_vmem, MSM8996_MASTER_SNOC_VMEM, 0, 1, 32, QCOM_QOS_MODE_BYPASS, 1, 114, -1, 1, MSM8996_SLAVE_VMEM_CFG); +DEFINE_QNODE(mas_tsif, MSM8996_MASTER_TSIF, 0, 1, 4, QCOM_QOS_MODE_BYPASS, 0, 37, -1, 1, MSM8996_PNOC_A1NOC_SLV); +DEFINE_QNODE(mas_ufs, MSM8996_MASTER_UFS, 2, 1, 8, QCOM_QOS_MODE_FIXED, 1, 68, -1, 1, MSM8996_A2NOC_SNOC_SLV); +DEFINE_QNODE(mas_usb3, MSM8996_MASTER_USB3, 3, 1, 8, QCOM_QOS_MODE_FIXED, 1, 32, -1, 1, MSM8996_A2NOC_SNOC_SLV); +DEFINE_QNODE(mas_usb_hs, MSM8996_MASTER_USB_HS, 0, 1, 8, QCOM_QOS_MODE_BYPASS, 0, 42, -1, 1, MSM8996_PNOC_A1NOC_SLV); +DEFINE_QNODE(mas_venus, MSM8996_MASTER_VIDEO_P0, 3, 2, 32, QCOM_QOS_MODE_BYPASS, 1, 9, -1, 1, MSM8996_MNOC_BIMC_SLV); +DEFINE_QNODE(mas_venus_vmem, MSM8996_MASTER_VIDEO_P0_OCMEM, 0, 1, 32, QCOM_QOS_MODE_BYPASS, 1, 121, -1, 1, MSM8996_SLAVE_VMEM_CFG); +DEFINE_QNODE(mas_vfe, MSM8996_MASTER_VFE, 6, 1, 32, QCOM_QOS_MODE_BYPASS, 1, 11, -1, 1, MSM8996_MNOC_BIMC_SLV); +DEFINE_QNODE(slv_a0noc_cfg, MSM8996_SLAVE_A0NOC_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 144, 0, 0); +DEFINE_QNODE(slv_a0noc_mpu_cfg, MSM8996_SLAVE_A0NOC_MPU_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 145, 0, 0); +DEFINE_QNODE(slv_a0noc_smmu_cfg, MSM8996_SLAVE_A0NOC_SMMU_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 146, 0, 0); +DEFINE_QNODE(slv_a0noc_snoc, MSM8996_A0NOC_SNOC_SLV, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 141, 1, MSM8996_A0NOC_SNOC_MAS); +DEFINE_QNODE(slv_a1noc_cfg, MSM8996_SLAVE_A1NOC_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 147, 0, 0); +DEFINE_QNODE(slv_a1noc_mpu_cfg, MSM8996_SLAVE_A1NOC_MPU_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 148, 0, 0); +DEFINE_QNODE(slv_a1noc_smmu_cfg, MSM8996_SLAVE_A1NOC_SMMU_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 149, 0, 0); +DEFINE_QNODE(slv_a1noc_snoc, MSM8996_A1NOC_SNOC_SLV, 0, 1, 8, QCOM_QOS_MODE_FIXED, 0, -1, 142, 1, MSM8996_A1NOC_SNOC_MAS); +DEFINE_QNODE(slv_a2noc_cfg, MSM8996_SLAVE_A2NOC_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 150, 0, 0); +DEFINE_QNODE(slv_a2noc_mpu_cfg, MSM8996_SLAVE_A2NOC_MPU_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 151, 0, 0); +DEFINE_QNODE(slv_a2noc_smmu_cfg, MSM8996_SLAVE_A2NOC_SMMU_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 152, 0, 0); +DEFINE_QNODE(slv_a2noc_snoc, MSM8996_A2NOC_SNOC_SLV, 0, 1, 8, QCOM_QOS_MODE_FIXED, 0, -1, 143, 1, MSM8996_A2NOC_SNOC_MAS); +DEFINE_QNODE(slv_ahb2phy, MSM8996_SLAVE_AHB2PHY, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 153, 0, 0); +DEFINE_QNODE(slv_bimc_cfg, MSM8996_SLAVE_BIMC_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 56, 0, 0); +DEFINE_QNODE(slv_bimc_snoc_0, MSM8996_BIMC_SNOC_SLV, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 2, 1, MSM8996_BIMC_SNOC_MAS); +DEFINE_QNODE(slv_bimc_snoc_1, MSM8996_BIMC_SNOC_1_SLV, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 138, 1, MSM8996_BIMC_SNOC_1_MAS); +DEFINE_QNODE(slv_blsp_1, MSM8996_SLAVE_BLSP_1, 0, 1, 4, QCOM_QOS_MODE_FIXED, 0, -1, 39, 0, 0); +DEFINE_QNODE(slv_blsp_2, MSM8996_SLAVE_BLSP_2, 0, 1, 4, QCOM_QOS_MODE_FIXED, 0, -1, 37, 0, 0); +DEFINE_QNODE(slv_camera_cfg, MSM8996_SLAVE_CAMERA_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 3, 0, 0); +DEFINE_QNODE(slv_camera_throttle_cfg, MSM8996_SLAVE_CAMERA_THROTTLE_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 154, 0, 0); +DEFINE_QNODE(slv_clk_ctl, MSM8996_SLAVE_CLK_CTL, 0, 1, 4, QCOM_QOS_MODE_FIXED, 0, -1, 47, 0, 0); +DEFINE_QNODE(slv_cnoc_a1noc, MSM8996_CNOC_SNOC_SLV, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 75, 1, MSM8996_CNOC_A1NOC_MAS); +DEFINE_QNODE(slv_cnoc_mnoc_cfg, MSM8996_SLAVE_CNOC_MNOC_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 66, 1, MSM8996_MASTER_CNOC_MNOC_CFG); +DEFINE_QNODE(slv_cnoc_mnoc_mmss_cfg, MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 58, 1, MSM8996_MASTER_CNOC_MNOC_MMSS_CFG); +DEFINE_QNODE(slv_cpr_apu_cfg, MSM8996_SLAVE_QDSS_RBCPR_APU_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 168, 0, 0); +DEFINE_QNODE(slv_cpr_cfg, MSM8996_SLAVE_CPR_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 6, 0, 0); +DEFINE_QNODE(slv_crypto0_cfg, MSM8996_SLAVE_CRYPTO_0_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 52, 0, 0); +DEFINE_QNODE(slv_dcc_cfg, MSM8996_SLAVE_DCC_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 155, 0, 0); +DEFINE_QNODE(slv_display_cfg, MSM8996_SLAVE_DISPLAY_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 4, 0, 0); +DEFINE_QNODE(slv_display_throttle_cfg, MSM8996_SLAVE_DISPLAY_THROTTLE_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 156, 0, 0); +DEFINE_QNODE(slv_dsa_cfg, MSM8996_SLAVE_DSA_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 157, 0, 0); +DEFINE_QNODE(slv_dsa_mpu_cfg, MSM8996_SLAVE_DSA_MPU_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 158, 0, 0); +DEFINE_QNODE(slv_ebi1_phy_cfg, MSM8996_SLAVE_EBI1_PHY_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 73, 0, 0); +DEFINE_QNODE(slv_ebi, MSM8996_SLAVE_EBI_CH0, 0, 2, 8, QCOM_QOS_MODE_FIXED, 0, -1, 0, 0, 0); +DEFINE_QNODE(slv_hmss_l3, MSM8996_SLAVE_HMSS_L3, 0, 1, 8, QCOM_QOS_MODE_FIXED, 0, -1, 160, 0, 0); +DEFINE_QNODE(slv_hmss, MSM8996_SLAVE_APPSS, 0, 1, 16, QCOM_QOS_MODE_FIXED, 1, -1, 20, 0, 0); +DEFINE_QNODE(slv_imem_cfg, MSM8996_SLAVE_IMEM_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 54, 0, 0); +DEFINE_QNODE(slv_imem, MSM8996_SLAVE_OCIMEM, 0, 1, 16, QCOM_QOS_MODE_FIXED, 0, -1, 26, 0, 0); +DEFINE_QNODE(slv_lpass, MSM8996_SLAVE_LPASS, 0, 1, 16, QCOM_QOS_MODE_FIXED, 1, -1, 21, 0, 0); +DEFINE_QNODE(slv_lpass_smmu_cfg, MSM8996_SLAVE_LPASS_SMMU_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 161, 0, 0); +DEFINE_QNODE(slv_message_ram, MSM8996_SLAVE_MESSAGE_RAM, 0, 1, 4, QCOM_QOS_MODE_FIXED, 0, -1, 55, 0, 0); +DEFINE_QNODE(slv_misc_cfg, MSM8996_SLAVE_MISC_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 8, 0, 0); +DEFINE_QNODE(slv_mmagic_cfg, MSM8996_SLAVE_MMAGIC_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 162, 0, 0); +DEFINE_QNODE(slv_mnoc_bimc, MSM8996_MNOC_BIMC_SLV, 0, 2, 32, QCOM_QOS_MODE_FIXED, 1, -1, 16, 1, MSM8996_MNOC_BIMC_MAS); +DEFINE_QNODE(slv_mnoc_clocks_cfg, MSM8996_SLAVE_MMSS_CLK_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 12, 0, 0); +DEFINE_QNODE(slv_mnoc_mpu_cfg, MSM8996_SLAVE_MNOC_MPU_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 14, 0, 0); +DEFINE_QNODE(slv_mpm, MSM8996_SLAVE_MPM, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 62, 0, 0); +DEFINE_QNODE(slv_oxili_cfg, MSM8996_SLAVE_GRAPHICS_3D_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 11, 0, 0); +DEFINE_QNODE(slv_pcie_0_cfg, MSM8996_SLAVE_PCIE_0_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 88, 0, 0); +DEFINE_QNODE(slv_pcie_0, MSM8996_SLAVE_PCIE_0, 0, 1, 16, QCOM_QOS_MODE_FIXED, 1, -1, 84, 0, 0); +DEFINE_QNODE(slv_pcie_1_cfg, MSM8996_SLAVE_PCIE_1_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 89, 0, 0); +DEFINE_QNODE(slv_pcie_1, MSM8996_SLAVE_PCIE_1, 0, 1, 16, QCOM_QOS_MODE_FIXED, 1, -1, 85, 0, 0); +DEFINE_QNODE(slv_pcie20_ahb2phy, MSM8996_SLAVE_PCIE20_AHB2PHY, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 163, 0, 0); +DEFINE_QNODE(slv_pcie_2_cfg, MSM8996_SLAVE_PCIE_2_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 165, 0, 0); +DEFINE_QNODE(slv_pcie_2, MSM8996_SLAVE_PCIE_2, 0, 1, 16, QCOM_QOS_MODE_FIXED, 1, -1, 164, 0, 0); +DEFINE_QNODE(slv_pdm, MSM8996_SLAVE_PDM, 0, 1, 4, QCOM_QOS_MODE_FIXED, 0, -1, 41, 0, 0); +DEFINE_QNODE(slv_pimem_cfg, MSM8996_SLAVE_PIMEM_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 167, 0, 0); +DEFINE_QNODE(slv_pimem, MSM8996_SLAVE_PIMEM, 0, 1, 16, QCOM_QOS_MODE_FIXED, 0, -1, 166, 0, 0); +DEFINE_QNODE(slv_pmic_arb, MSM8996_SLAVE_PMIC_ARB, 0, 1, 4, QCOM_QOS_MODE_FIXED, 0, -1, 59, 0, 0); +DEFINE_QNODE(slv_pnoc_a1noc, MSM8996_PNOC_A1NOC_SLV, 0, 1, 8, QCOM_QOS_MODE_FIXED, 0, -1, 139, 1, MSM8996_PNOC_A1NOC_MAS); +DEFINE_QNODE(slv_prng, MSM8996_SLAVE_PRNG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 44, 0, 0); +DEFINE_QNODE(slv_qdss_cfg, MSM8996_SLAVE_QDSS_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 63, 0, 0); +DEFINE_QNODE(slv_qdss_stm, MSM8996_SLAVE_QDSS_STM, 0, 1, 16, QCOM_QOS_MODE_FIXED, 0, -1, 30, 0, 0); +DEFINE_QNODE(slv_rbcpr_cx, MSM8996_SLAVE_RBCPR_CX, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 169, 0, 0); +DEFINE_QNODE(slv_rbcpr_mx, MSM8996_SLAVE_RBCPR_MX, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 170, 0, 0); +DEFINE_QNODE(slv_sdcc_1, MSM8996_SLAVE_SDCC_1, 0, 1, 4, QCOM_QOS_MODE_FIXED, 0, -1, 31, 0, 0); +DEFINE_QNODE(slv_sdcc_2, MSM8996_SLAVE_SDCC_2, 0, 1, 4, QCOM_QOS_MODE_FIXED, 0, -1, 33, 0, 0); +DEFINE_QNODE(slv_sdcc_4, MSM8996_SLAVE_SDCC_4, 0, 1, 4, QCOM_QOS_MODE_FIXED, 0, -1, 34, 0, 0); +DEFINE_QNODE(slv_smmu_cpp_cfg, MSM8996_SLAVE_SMMU_CPP_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 171, 0, 0); +DEFINE_QNODE(slv_smmu_jpeg_cfg, MSM8996_SLAVE_SMMU_JPEG_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 172, 0, 0); +DEFINE_QNODE(slv_smmu_mdp_cfg, MSM8996_SLAVE_SMMU_MDP_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 173, 0, 0); +DEFINE_QNODE(slv_smmu_rot_cfg, MSM8996_SLAVE_SMMU_ROTATOR_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 174, 0, 0); +DEFINE_QNODE(slv_smmu_venus_cfg, MSM8996_SLAVE_SMMU_VENUS_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 175, 0, 0); +DEFINE_QNODE(slv_smmu_vfe_cfg, MSM8996_SLAVE_SMMU_VFE_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 176, 0, 0); +DEFINE_QNODE(slv_snoc_bimc, MSM8996_SNOC_BIMC_SLV, 0, 2, 32, QCOM_QOS_MODE_FIXED, 0, -1, 24, 1, MSM8996_SNOC_BIMC_MAS); +DEFINE_QNODE(slv_snoc_cfg, MSM8996_SLAVE_SNOC_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 70, 0, 0); +DEFINE_QNODE(slv_snoc_cnoc, MSM8996_SNOC_CNOC_SLV, 0, 1, 16, QCOM_QOS_MODE_FIXED, 0, -1, 25, 1, MSM8996_SNOC_CNOC_MAS); +DEFINE_QNODE(slv_snoc_mpu_cfg, MSM8996_SLAVE_SNOC_MPU_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 67, 0, 0); +DEFINE_QNODE(slv_snoc_pnoc, MSM8996_SNOC_PNOC_SLV, 0, 1, 16, QCOM_QOS_MODE_FIXED, 0, -1, 28, 1, MSM8996_SNOC_PNOC_MAS); +DEFINE_QNODE(slv_snoc_vmem, MSM8996_SLAVE_SNOC_VMEM, 0, 1, 16, QCOM_QOS_MODE_FIXED, 1, -1, 140, 1, MSM8996_MASTER_SNOC_VMEM); +DEFINE_QNODE(slv_srvc_mnoc, MSM8996_SLAVE_SERVICE_MNOC, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 17, 0, 0); +DEFINE_QNODE(slv_srvc_snoc, MSM8996_SLAVE_SERVICE_SNOC, 0, 1, 16, QCOM_QOS_MODE_FIXED, 1, -1, 29, 0, 0); +DEFINE_QNODE(slv_ssc_cfg, MSM8996_SLAVE_SSC_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 177, 0, 0); +DEFINE_QNODE(slv_tcsr, MSM8996_SLAVE_TCSR, 0, 1, 4, QCOM_QOS_MODE_FIXED, 0, -1, 50, 0, 0); +DEFINE_QNODE(slv_tlmm, MSM8996_SLAVE_TLMM, 0, 1, 4, QCOM_QOS_MODE_FIXED, 0, -1, 51, 0, 0); +DEFINE_QNODE(slv_tsif, MSM8996_SLAVE_TSIF, 0, 1, 4, QCOM_QOS_MODE_FIXED, 0, -1, 35, 0, 0); +DEFINE_QNODE(slv_ufs_cfg, MSM8996_SLAVE_UFS_CFG, 0, 1, 4, QCOM_QOS_MODE_FIXED, 1, -1, 92, 0, 0); +DEFINE_QNODE(slv_usb3, MSM8996_SLAVE_USB3, 0, 1, 16, QCOM_QOS_MODE_FIXED, 1, -1, 22, 0, 0); +DEFINE_QNODE(slv_usb_hs, MSM8996_SLAVE_USB_HS, 0, 1, 4, QCOM_QOS_MODE_FIXED, 0, -1, 40, 0, 0); +DEFINE_QNODE(slv_venus_cfg, MSM8996_SLAVE_VENUS_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 10, 0, 0); +DEFINE_QNODE(slv_venus_throttle_cfg, MSM8996_SLAVE_VENUS_THROTTLE_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 178, 0, 0); +DEFINE_QNODE(slv_vmem_cfg, MSM8996_SLAVE_VMEM_CFG, 0, 1, 8, QCOM_QOS_MODE_FIXED, 1, -1, 180, 0, 0); +DEFINE_QNODE(slv_vmem, MSM8996_SLAVE_VMEM, 0, 1, 32, QCOM_QOS_MODE_FIXED, 1, -1, 179, 0, 0); + +static struct qcom_icc_node *msm8996_snoc_nodes[] = { + [A0NOC_SNOC_MAS] = &mas_a0noc_snoc, + [A0NOC_SNOC_SLV] = &slv_a0noc_snoc, + [A1NOC_SNOC_MAS] = &mas_a1noc_snoc, + [A1NOC_SNOC_SLV] = &slv_a1noc_snoc, + [A2NOC_SNOC_MAS] = &mas_a2noc_snoc, + [A2NOC_SNOC_SLV] = &slv_a2noc_snoc, + [BIMC_SNOC_1_MAS] = &mas_bimc_snoc_1, + [BIMC_SNOC_MAS] = &mas_bimc_snoc_0, + [MASTER_HMSS] = &mas_hmss, + [MASTER_QDSS_BAM] = &mas_qdss_bam, + [MASTER_QDSS_ETR] = &mas_qdss_etr, + [MASTER_SNOC_CFG] = &mas_snoc_cfg, + [SLAVE_APPSS] = &slv_hmss, + [SLAVE_LPASS] = &slv_lpass, + [SLAVE_OCIMEM] = &slv_imem, + [SLAVE_PCIE_0] = &slv_pcie_0, + [SLAVE_PCIE_1] = &slv_pcie_1, + [SLAVE_PCIE_2] = &slv_pcie_2, + [SLAVE_PIMEM] = &slv_pimem, + [SLAVE_QDSS_STM] = &slv_qdss_stm, + [SLAVE_SERVICE_SNOC] = &slv_srvc_snoc, + [SLAVE_SNOC_VMEM] = &slv_snoc_vmem, + [SLAVE_USB3] = &slv_usb3, + [SNOC_BIMC_SLV] = &slv_snoc_bimc, + [SNOC_CNOC_SLV] = &slv_snoc_cnoc, + [SNOC_PNOC_SLV] = &slv_snoc_pnoc, +}; + +static struct qcom_icc_desc msm8996_snoc = { + .nodes = msm8996_snoc_nodes, + .num_nodes = ARRAY_SIZE(msm8996_snoc_nodes), +}; + +static struct qcom_icc_node *msm8996_bimc_nodes[] = { + [BIMC_SNOC_SLV] = &slv_bimc_snoc_0, + [BIMC_SNOC_1_SLV] = &slv_bimc_snoc_1, + [MASTER_AMPSS_M0] = &mas_apps_proc, + [MASTER_GRAPHICS_3D] = &mas_oxili, + [MNOC_BIMC_MAS] = &mas_mnoc_bimc, + [SLAVE_EBI_CH0] = &slv_ebi, + [SLAVE_HMSS_L3] = &slv_hmss_l3, + [SNOC_BIMC_MAS] = &mas_snoc_bimc, +}; + +static struct qcom_icc_desc msm8996_bimc = { + .nodes = msm8996_bimc_nodes, + .num_nodes = ARRAY_SIZE(msm8996_bimc_nodes), +}; + +static struct qcom_icc_node *msm8996_pnoc_nodes[] = { + [MASTER_BLSP_1] = &mas_blsp_1, + [MASTER_BLSP_2] = &mas_blsp_2, + [MASTER_SDCC_1] = &mas_sdcc_1, + [MASTER_SDCC_2] = &mas_sdcc_2, + [MASTER_SDCC_4] = &mas_sdcc_4, + [MASTER_TSIF] = &mas_tsif, + [MASTER_USB_HS] = &mas_usb_hs, + [PNOC_A1NOC_SLV] = &slv_pnoc_a1noc, + [SLAVE_AHB2PHY] = &slv_ahb2phy, + [SLAVE_BLSP_1] = &slv_blsp_1, + [SLAVE_BLSP_2] = &slv_blsp_2, + [SLAVE_PDM] = &slv_pdm, + [SLAVE_SDCC_1] = &slv_sdcc_1, + [SLAVE_SDCC_2] = &slv_sdcc_2, + [SLAVE_SDCC_4] = &slv_sdcc_4, + [SLAVE_TSIF] = &slv_tsif, + [SLAVE_USB_HS] = &slv_usb_hs, + [SNOC_PNOC_MAS] = &mas_snoc_pnoc, +}; + +static struct qcom_icc_desc msm8996_pnoc = { + .nodes = msm8996_pnoc_nodes, + .num_nodes = ARRAY_SIZE(msm8996_pnoc_nodes), +}; + +static struct qcom_icc_node *msm8996_cnoc_nodes[] = { + [CNOC_SNOC_SLV] = &slv_cnoc_a1noc, + [MASTER_QDSS_DAP] = &mas_qdss_dap, + [SLAVE_A0NOC_CFG] = &slv_a0noc_cfg, + [SLAVE_A0NOC_MPU_CFG] = &slv_a0noc_mpu_cfg, + [SLAVE_A0NOC_SMMU_CFG] = &slv_a0noc_smmu_cfg, + [SLAVE_A1NOC_CFG] = &slv_a1noc_cfg, + [SLAVE_A1NOC_MPU_CFG] = &slv_a1noc_mpu_cfg, + [SLAVE_A1NOC_SMMU_CFG] = &slv_a1noc_smmu_cfg, + [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg, + [SLAVE_A2NOC_MPU_CFG] = &slv_a2noc_mpu_cfg, + [SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg, + [SLAVE_BIMC_CFG] = &slv_bimc_cfg, + [SLAVE_CLK_CTL] = &slv_clk_ctl, + [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg, + [SLAVE_CNOC_MNOC_MMSS_CFG] &slv_cnoc_mnoc_mmss_cfg, + [SLAVE_CRYPTO_0_CFG] = &slv_crypto0_cfg, + [SLAVE_DCC_CFG] = &slv_dcc_cfg, + [SLAVE_EBI1_PHY_CFG] = &slv_ebi1_phy_cfg, + [SLAVE_IMEM_CFG] = &slv_imem_cfg, + [SLAVE_LPASS_SMMU_CFG] = &slv_lpass_smmu_cfg, + [SLAVE_MESSAGE_RAM] = &slv_message_ram, + [SLAVE_MPM] = &slv_mpm, + [SLAVE_PCIE_0_CFG] = &slv_pcie_0_cfg, + [SLAVE_PCIE_1_CFG] = &slv_pcie_1_cfg, + [SLAVE_PCIE20_AHB2PHY] = &slv_pcie20_ahb2phy, + [SLAVE_PCIE_2_CFG] = &slv_pcie_2_cfg, + [SLAVE_PIMEM_CFG] = &slv_pimem_cfg, + [SLAVE_PMIC_ARB] = &slv_pmic_arb, + [SLAVE_PRNG] = &slv_prng, + [SLAVE_QDSS_CFG] = &slv_qdss_cfg, + [SLAVE_QDSS_RBCPR_APU_CFG] = &slv_cpr_apu_cfg, + [SLAVE_RBCPR_CX] = &slv_rbcpr_cx, + [SLAVE_RBCPR_MX] = &slv_rbcpr_mx, + [SLAVE_SNOC_CFG] = &slv_snoc_cfg, + [SLAVE_SNOC_MPU_CFG] = &slv_snoc_mpu_cfg, + [SLAVE_SSC_CFG] = &slv_ssc_cfg, + [SLAVE_TCSR] = &slv_tcsr, + [SLAVE_TLMM] = &slv_tlmm, + [SLAVE_UFS_CFG] = &slv_ufs_cfg, + [SNOC_CNOC_MAS] = &mas_snoc_cnoc, +}; + +static struct qcom_icc_desc msm8996_cnoc = { + .nodes = msm8996_cnoc_nodes, + .num_nodes = ARRAY_SIZE(msm8996_cnoc_nodes), +}; + +static struct qcom_icc_node *msm8996_mnoc_nodes[] = { + [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg, + [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg, + [MASTER_CPP] = &mas_cpp, + [MASTER_JPEG] = &mas_jpeg, + [MASTER_MDP_PORT0] = &mas_mdp_p0, + [MASTER_MDP_PORT1] = &mas_mdp_p1, + [MASTER_ROTATOR] = &mas_rotator, + [MASTER_SNOC_VMEM] = &mas_snoc_vmem, + [MASTER_VFE] = &mas_vfe, + [MASTER_VIDEO_P0] = &mas_venus, + [MASTER_VIDEO_P0_OCMEM] = &mas_venus_vmem, + [MNOC_BIMC_SLV] = &slv_mnoc_bimc, + [SLAVE_CAMERA_CFG] = &slv_camera_cfg, + [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg, + [SLAVE_CPR_CFG] = &slv_cpr_cfg, + [SLAVE_DISPLAY_CFG] = &slv_display_cfg, + [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg, + [SLAVE_DSA_CFG] = &slv_dsa_cfg, + [SLAVE_DSA_MPU_CFG] = &slv_dsa_mpu_cfg, + [SLAVE_GRAPHICS_3D_CFG] = &slv_oxili_cfg, + [SLAVE_MISC_CFG] = &slv_misc_cfg, + [SLAVE_MMAGIC_CFG] = &slv_mmagic_cfg, + [SLAVE_MMSS_CLK_CFG] = &slv_mnoc_clocks_cfg, + [SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg, + [SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc, + [SLAVE_SMMU_CPP_CFG] = &slv_smmu_cpp_cfg, + [SLAVE_SMMU_JPEG_CFG] = &slv_smmu_jpeg_cfg, + [SLAVE_SMMU_MDP_CFG] = &slv_smmu_mdp_cfg, + [SLAVE_SMMU_ROTATOR_CFG] = &slv_smmu_rot_cfg, + [SLAVE_SMMU_VENUS_CFG] = &slv_smmu_venus_cfg, + [SLAVE_SMMU_VFE_CFG] = &slv_smmu_vfe_cfg, + [SLAVE_VENUS_CFG] = &slv_venus_cfg, + [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg, + [SLAVE_VMEM_CFG] = &slv_vmem_cfg, + [SLAVE_VMEM] = &slv_vmem, +}; + +static struct qcom_icc_desc msm8996_mnoc = { + .nodes = msm8996_mnoc_nodes, + .num_nodes = ARRAY_SIZE(msm8996_mnoc_nodes), +}; + +static struct qcom_icc_node *msm8996_a0noc_nodes[] = { + [MASTER_PCIE] = &mas_pcie_0, + [MASTER_PCIE_1] = &mas_pcie_1, + [MASTER_PCIE_2] = &mas_pcie_2, +}; + +static struct qcom_icc_desc msm8996_a0noc = { + .nodes = msm8996_a0noc_nodes, + .num_nodes = ARRAY_SIZE(msm8996_a0noc_nodes), +}; + +static struct qcom_icc_node *msm8996_a1noc_nodes[] = { + [CNOC_A1NOC_MAS] = &mas_cnoc_a1noc, + [MASTER_CRYPTO_CORE0] = &mas_crypto_c0, + [PNOC_A1NOC_MAS] = &mas_pnoc_a1noc, +}; + +static struct qcom_icc_desc msm8996_a1noc = { + .nodes = msm8996_a1noc_nodes, + .num_nodes = ARRAY_SIZE(msm8996_a1noc_nodes), +}; + +static struct qcom_icc_node *msm8996_a2noc_nodes[] = { + [MASTER_IPA] = &mas_ipa, + [MASTER_UFS] = &mas_ufs, + [MASTER_USB3] = &mas_usb3, +}; + +static struct qcom_icc_desc msm8996_a2noc = { + .nodes = msm8996_a2noc_nodes, + .num_nodes = ARRAY_SIZE(msm8996_a2noc_nodes), +}; + +static int qcom_icc_aggregate(struct icc_node *node, u8 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + *agg_avg += avg_bw; + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct qcom_icc_provider *qp; + struct qcom_icc_node *qn; + struct icc_provider *provider; + struct icc_node *n; + u64 sum_bw; + u64 max_peak_bw; + u64 rate; + u32 agg_avg = 0; + u32 agg_peak = 0; + int ret = 0; + + qn = src->data; + provider = src->provider; + qp = to_qcom_provider(provider); + list_for_each_entry(n, &provider->nodes, node_list) + qcom_icc_aggregate(n, 0, n->avg_bw, n->peak_bw, + &agg_avg, &agg_peak); + + sum_bw = icc_units_to_bps(agg_avg); + max_peak_bw = icc_units_to_bps(agg_peak); + + /* set bandwidth */ + if (qn->ap_owned) { + /* TODO: set QoS */ + } else { + /* send message to the RPM processor */ + + if (qn->mas_rpm_id != -1) { + ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, + RPM_BUS_MASTER_REQ, + qn->mas_rpm_id, + sum_bw); + if (ret) { + pr_err("qcom_icc_rpm_smd_send mas %d error %d\n", qn->mas_rpm_id, ret); + return ret; + } + } + + if (qn->slv_rpm_id != -1) { + ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, + RPM_BUS_SLAVE_REQ, + qn->slv_rpm_id, + sum_bw); + if (ret) { + pr_err("qcom_icc_rpm_smd_send slv error %d\n", + ret); + return ret; + } + } + } + + rate = max(sum_bw, max_peak_bw); + + do_div(rate, qn->buswidth); + + if (qn->rate != rate) { + ret = clk_set_rate(qp->bus_clk, rate); + if (ret) { + pr_err("set clk rate %lld error %d\n", rate, ret); + return ret; + } + + ret = clk_set_rate(qp->bus_a_clk, rate); + if (ret) { + pr_err("set clk rate %lld error %d\n", rate, ret); + return ret; + } + + qn->rate = rate; + } + + return ret; +} + +static int qnoc_probe(struct platform_device *pdev) +{ + const struct qcom_icc_desc *desc; + struct icc_onecell_data *data; + struct icc_provider *provider; + struct qcom_icc_node **qnodes; + struct qcom_icc_provider *qp; + struct icc_node *node; + struct resource *res; + size_t num_nodes, i; + int ret; + + /* wait for RPM */ + if (!qcom_icc_rpm_smd_available()) + return -EPROBE_DEFER; + + desc = of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + qnodes = desc->nodes; + num_nodes = desc->num_nodes; + + qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL); + if (!qp) + return -ENOMEM; + + data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL); + if (!data) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + qp->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(qp->base)) + return PTR_ERR(qp->base); + + qp->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); + if (IS_ERR(qp->bus_clk)) + return PTR_ERR(qp->bus_clk); + + ret = clk_prepare_enable(qp->bus_clk); + if (ret) { + dev_err(&pdev->dev, "error enabling bus_clk: %d\n", ret); + return ret; + } + + qp->bus_a_clk = devm_clk_get(&pdev->dev, "bus_a_clk"); + if (IS_ERR(qp->bus_a_clk)) + return PTR_ERR(qp->bus_a_clk); + + ret = clk_prepare_enable(qp->bus_a_clk); + if (ret) { + dev_err(&pdev->dev, "error enabling bus_a_clk: %d\n", ret); + clk_disable_unprepare(qp->bus_clk); + return ret; + } + + provider = &qp->provider; + INIT_LIST_HEAD(&provider->nodes); + provider->dev = &pdev->dev; + provider->set = qcom_icc_set; + provider->aggregate = qcom_icc_aggregate; + provider->xlate = of_icc_xlate_onecell; + provider->data = data; + + ret = icc_provider_add(provider); + if (ret) { + dev_err(&pdev->dev, "error adding interconnect provider\n"); + clk_disable_unprepare(qp->bus_clk); + clk_disable_unprepare(qp->bus_a_clk); + return ret; + } + + for (i = 0; i < num_nodes; i++) { + size_t j; + + node = icc_node_create(qnodes[i]->id); + if (IS_ERR(node)) { + ret = PTR_ERR(node); + goto err; + } + node->name = qnodes[i]->name; + node->data = qnodes[i]; + icc_node_add(node, provider); + + dev_dbg(&pdev->dev, "registered node %s\n", node->name); + + /* populate links */ + for (j = 0; j < qnodes[i]->num_links; j++) + icc_link_create(node, qnodes[i]->links[j]); + data->nodes[i] = node; + } + data->num_nodes = num_nodes; + + platform_set_drvdata(pdev, qp); + + return ret; +err: + list_for_each_entry(node, &provider->nodes, node_list) { + icc_node_del(node); + icc_node_destroy(node->id); + } + clk_disable_unprepare(qp->bus_clk); + clk_disable_unprepare(qp->bus_a_clk); + icc_provider_del(provider); + + return ret; +} + +static int qnoc_remove(struct platform_device *pdev) +{ + struct qcom_icc_provider *qp = platform_get_drvdata(pdev); + struct icc_provider *provider = &qp->provider; + struct icc_node *n; + + list_for_each_entry(n, &provider->nodes, node_list) { + icc_node_del(n); + icc_node_destroy(n->id); + } + clk_disable_unprepare(qp->bus_clk); + clk_disable_unprepare(qp->bus_a_clk); + + return icc_provider_del(provider); +} + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,msm8996-bimc", .data = &msm8996_bimc }, + { .compatible = "qcom,msm8996-cnoc", .data = &msm8996_cnoc }, + { .compatible = "qcom,msm8996-snoc", .data = &msm8996_snoc }, + { .compatible = "qcom,msm8996-a0noc", .data = &msm8996_a0noc }, + { .compatible = "qcom,msm8996-a1noc", .data = &msm8996_a1noc }, + { .compatible = "qcom,msm8996-a2noc", .data = &msm8996_a2noc }, + { .compatible = "qcom,msm8996-mmnoc", .data = &msm8996_mnoc }, + { .compatible = "qcom,msm8996-pnoc", .data = &msm8996_pnoc }, + { }, +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qnoc_probe, + .remove = qnoc_remove, + .driver = { + .name = "qnoc-msm8996", + .of_match_table = qnoc_of_match, + }, +}; +module_platform_driver(qnoc_driver); +MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>"); +MODULE_DESCRIPTION("Qualcomm msm8996 NoC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/qcom/msm8996_ids.h b/drivers/interconnect/qcom/msm8996_ids.h new file mode 100644 index 000000000000..e025bad65765 --- /dev/null +++ b/drivers/interconnect/qcom/msm8996_ids.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Qualcomm MSM8996 interconnect IDs + * + * Copyright (c) 2018, Linaro Ltd. + * Author: Georgi Djakov <georgi.djakov@linaro.org> + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_MSM8996_H +#define __DRIVERS_INTERCONNECT_QCOM_MSM8996_H + +#define MSM8996_A0NOC_SNOC_MAS 0 +#define MSM8996_A1NOC_SNOC_MAS 1 +#define MSM8996_A2NOC_SNOC_MAS 2 +#define MSM8996_MASTER_AMPSS_M0 3 +#define MSM8996_BIMC_SNOC_MAS 4 +#define MSM8996_BIMC_SNOC_1_MAS 5 +#define MSM8996_MASTER_BLSP_1 6 +#define MSM8996_MASTER_BLSP_2 7 +#define MSM8996_CNOC_A1NOC_MAS 8 +#define MSM8996_MASTER_CNOC_MNOC_CFG 9 +#define MSM8996_MASTER_CNOC_MNOC_MMSS_CFG 10 +#define MSM8996_MASTER_CPP 11 +#define MSM8996_MASTER_CRYPTO_CORE0 12 +#define MSM8996_MASTER_HMSS 13 +#define MSM8996_MASTER_IPA 14 +#define MSM8996_MASTER_JPEG 15 +#define MSM8996_MASTER_MDP_PORT0 16 +#define MSM8996_MASTER_MDP_PORT1 17 +#define MSM8996_MNOC_BIMC_MAS 18 +#define MSM8996_MASTER_GRAPHICS_3D 19 +#define MSM8996_MASTER_PCIE 20 +#define MSM8996_MASTER_PCIE_1 21 +#define MSM8996_MASTER_PCIE_2 22 +#define MSM8996_PNOC_A1NOC_MAS 23 +#define MSM8996_MASTER_QDSS_BAM 24 +#define MSM8996_MASTER_QDSS_DAP 25 +#define MSM8996_MASTER_QDSS_ETR 26 +#define MSM8996_MASTER_ROTATOR 27 +#define MSM8996_MASTER_SDCC_1 28 +#define MSM8996_MASTER_SDCC_2 29 +#define MSM8996_MASTER_SDCC_4 30 +#define MSM8996_SNOC_BIMC_MAS 31 +#define MSM8996_MASTER_SNOC_CFG 32 +#define MSM8996_SNOC_CNOC_MAS 33 +#define MSM8996_SNOC_PNOC_MAS 34 +#define MSM8996_MASTER_SNOC_VMEM 35 +#define MSM8996_MASTER_TSIF 36 +#define MSM8996_MASTER_UFS 37 +#define MSM8996_MASTER_USB3 38 +#define MSM8996_MASTER_USB_HS 39 +#define MSM8996_MASTER_VIDEO_P0 40 +#define MSM8996_MASTER_VIDEO_P0_OCMEM 41 +#define MSM8996_MASTER_VFE 42 +#define MSM8996_SLAVE_A0NOC_CFG 43 +#define MSM8996_SLAVE_A0NOC_MPU_CFG 44 +#define MSM8996_SLAVE_A0NOC_SMMU_CFG 45 +#define MSM8996_A0NOC_SNOC_SLV 46 +#define MSM8996_SLAVE_A1NOC_CFG 47 +#define MSM8996_SLAVE_A1NOC_MPU_CFG 48 +#define MSM8996_SLAVE_A1NOC_SMMU_CFG 49 +#define MSM8996_A1NOC_SNOC_SLV 50 +#define MSM8996_SLAVE_A2NOC_CFG 51 +#define MSM8996_SLAVE_A2NOC_MPU_CFG 52 +#define MSM8996_SLAVE_A2NOC_SMMU_CFG 53 +#define MSM8996_A2NOC_SNOC_SLV 54 +#define MSM8996_SLAVE_AHB2PHY 55 +#define MSM8996_SLAVE_BIMC_CFG 56 +#define MSM8996_BIMC_SNOC_SLV 57 +#define MSM8996_BIMC_SNOC_1_SLV 58 +#define MSM8996_SLAVE_BLSP_1 59 +#define MSM8996_SLAVE_BLSP_2 60 +#define MSM8996_SLAVE_CAMERA_CFG 61 +#define MSM8996_SLAVE_CAMERA_THROTTLE_CFG 62 +#define MSM8996_SLAVE_CLK_CTL 63 +#define MSM8996_CNOC_SNOC_SLV 64 +#define MSM8996_SLAVE_CNOC_MNOC_CFG 65 +#define MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG 66 +#define MSM8996_SLAVE_QDSS_RBCPR_APU_CFG 67 +#define MSM8996_SLAVE_CPR_CFG 68 +#define MSM8996_SLAVE_CRYPTO_0_CFG 69 +#define MSM8996_SLAVE_DCC_CFG 70 +#define MSM8996_SLAVE_DISPLAY_CFG 71 +#define MSM8996_SLAVE_DISPLAY_THROTTLE_CFG 72 +#define MSM8996_SLAVE_DSA_CFG 73 +#define MSM8996_SLAVE_DSA_MPU_CFG 74 +#define MSM8996_SLAVE_EBI1_PHY_CFG 75 +#define MSM8996_SLAVE_EBI_CH0 76 +#define MSM8996_SLAVE_HMSS_L3 77 +#define MSM8996_SLAVE_APPSS 78 +#define MSM8996_SLAVE_IMEM_CFG 79 +#define MSM8996_SLAVE_OCIMEM 80 +#define MSM8996_SLAVE_LPASS 81 +#define MSM8996_SLAVE_LPASS_SMMU_CFG 82 +#define MSM8996_SLAVE_MESSAGE_RAM 83 +#define MSM8996_SLAVE_MISC_CFG 84 +#define MSM8996_SLAVE_MMAGIC_CFG 85 +#define MSM8996_MNOC_BIMC_SLV 86 +#define MSM8996_SLAVE_MMSS_CLK_CFG 87 +#define MSM8996_SLAVE_MNOC_MPU_CFG 88 +#define MSM8996_SLAVE_MPM 89 +#define MSM8996_SLAVE_GRAPHICS_3D_CFG 90 +#define MSM8996_SLAVE_PCIE_0_CFG 91 +#define MSM8996_SLAVE_PCIE_0 92 +#define MSM8996_SLAVE_PCIE_1_CFG 93 +#define MSM8996_SLAVE_PCIE_1 94 +#define MSM8996_SLAVE_PCIE20_AHB2PHY 95 +#define MSM8996_SLAVE_PCIE_2_CFG 96 +#define MSM8996_SLAVE_PCIE_2 97 +#define MSM8996_SLAVE_PDM 98 +#define MSM8996_SLAVE_PIMEM_CFG 99 +#define MSM8996_SLAVE_PIMEM 100 +#define MSM8996_SLAVE_PMIC_ARB 101 +#define MSM8996_PNOC_A1NOC_SLV 102 +#define MSM8996_SLAVE_PRNG 103 +#define MSM8996_SLAVE_QDSS_CFG 104 +#define MSM8996_SLAVE_QDSS_STM 105 +#define MSM8996_SLAVE_RBCPR_CX 106 +#define MSM8996_SLAVE_RBCPR_MX 107 +#define MSM8996_SLAVE_SDCC_1 108 +#define MSM8996_SLAVE_SDCC_2 109 +#define MSM8996_SLAVE_SDCC_4 110 +#define MSM8996_SLAVE_SMMU_CPP_CFG 111 +#define MSM8996_SLAVE_SMMU_JPEG_CFG 112 +#define MSM8996_SLAVE_SMMU_MDP_CFG 113 +#define MSM8996_SLAVE_SMMU_ROTATOR_CFG 114 +#define MSM8996_SLAVE_SMMU_VENUS_CFG 115 +#define MSM8996_SLAVE_SMMU_VFE_CFG 116 +#define MSM8996_SNOC_BIMC_SLV 117 +#define MSM8996_SLAVE_SNOC_CFG 118 +#define MSM8996_SNOC_CNOC_SLV 119 +#define MSM8996_SLAVE_SNOC_MPU_CFG 120 +#define MSM8996_SNOC_PNOC_SLV 121 +#define MSM8996_SLAVE_SNOC_VMEM 122 +#define MSM8996_SLAVE_SERVICE_MNOC 123 +#define MSM8996_SLAVE_SERVICE_SNOC 124 +#define MSM8996_SLAVE_SSC_CFG 125 +#define MSM8996_SLAVE_TCSR 126 +#define MSM8996_SLAVE_TLMM 127 +#define MSM8996_SLAVE_TSIF 128 +#define MSM8996_SLAVE_UFS_CFG 129 +#define MSM8996_SLAVE_USB3 130 +#define MSM8996_SLAVE_USB_HS 131 +#define MSM8996_SLAVE_VENUS_CFG 132 +#define MSM8996_SLAVE_VENUS_THROTTLE_CFG 133 +#define MSM8996_SLAVE_VMEM_CFG 134 +#define MSM8996_SLAVE_VMEM 135 + +#endif diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c index 4915b78da673..481842c7edaa 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -65,6 +65,12 @@ struct bcm_db { #define SDM845_MAX_BCMS 30 #define SDM845_MAX_BCM_PER_NODE 2 #define SDM845_MAX_VCD 10 +#define SDM845_MAX_CTX 2 +#define SDM845_EE_STATE 2 +#define EE_STATE_WAKE 0 +#define EE_STATE_SLEEP 1 +#define AO_CTX 0 +#define DUAL_CTX 1 /** * struct qcom_icc_node - Qualcomm specific interconnect nodes @@ -86,8 +92,8 @@ struct qcom_icc_node { u16 num_links; u16 channels; u16 buswidth; - u64 sum_avg; - u64 max_peak; + u64 sum_avg[SDM845_MAX_CTX]; + u64 max_peak[SDM845_MAX_CTX]; struct qcom_icc_bcm *bcms[SDM845_MAX_BCM_PER_NODE]; size_t num_bcms; }; @@ -112,8 +118,8 @@ struct qcom_icc_bcm { const char *name; u32 type; u32 addr; - u64 vote_x; - u64 vote_y; + u64 vote_x[SDM845_EE_STATE]; + u64 vote_y[SDM845_EE_STATE]; bool dirty; bool keepalive; struct bcm_db aux_data; @@ -555,7 +561,7 @@ inline void tcs_cmd_gen(struct tcs_cmd *cmd, u64 vote_x, u64 vote_y, cmd->wait = true; } -static void tcs_list_gen(struct list_head *bcm_list, +static void tcs_list_gen(struct list_head *bcm_list, int ee_state, struct tcs_cmd tcs_list[SDM845_MAX_VCD], int n[SDM845_MAX_VCD]) { @@ -573,8 +579,8 @@ static void tcs_list_gen(struct list_head *bcm_list, commit = true; cur_vcd_size = 0; } - tcs_cmd_gen(&tcs_list[idx], bcm->vote_x, bcm->vote_y, - bcm->addr, commit); + tcs_cmd_gen(&tcs_list[idx], bcm->vote_x[ee_state], + bcm->vote_y[ee_state], bcm->addr, commit); idx++; n[batch]++; /* @@ -595,50 +601,62 @@ static void tcs_list_gen(struct list_head *bcm_list, static void bcm_aggregate(struct qcom_icc_bcm *bcm) { - size_t i; - u64 agg_avg = 0; - u64 agg_peak = 0; + size_t i, ctx_idx; + u64 agg_avg[SDM845_MAX_CTX] = {0}; + u64 agg_peak[SDM845_MAX_CTX] = {0}; u64 temp; - for (i = 0; i < bcm->num_nodes; i++) { - temp = bcm->nodes[i]->sum_avg * bcm->aux_data.width; - do_div(temp, bcm->nodes[i]->buswidth * bcm->nodes[i]->channels); - agg_avg = max(agg_avg, temp); + for (ctx_idx = 0; ctx_idx < SDM845_MAX_CTX; ctx_idx++) { + for (i = 0; i < bcm->num_nodes; i++) { + temp = bcm->nodes[i]->sum_avg[ctx_idx] * bcm->aux_data.width; + do_div(temp, bcm->nodes[i]->buswidth * bcm->nodes[i]->channels); + agg_avg[ctx_idx] = max(agg_avg[ctx_idx], temp); - temp = bcm->nodes[i]->max_peak * bcm->aux_data.width; - do_div(temp, bcm->nodes[i]->buswidth); - agg_peak = max(agg_peak, temp); + temp = bcm->nodes[i]->max_peak[ctx_idx] * bcm->aux_data.width; + do_div(temp, bcm->nodes[i]->buswidth); + agg_peak[ctx_idx] = max(agg_peak[ctx_idx], temp); + } } - temp = agg_avg * 1000ULL; + temp = agg_avg[AO_CTX] + agg_avg[DUAL_CTX] * 1000ULL; + do_div(temp, bcm->aux_data.unit); + bcm->vote_x[EE_STATE_WAKE] = temp; + + temp = max(agg_peak[AO_CTX], agg_peak[DUAL_CTX]) * 1000ULL; + do_div(temp, bcm->aux_data.unit); + bcm->vote_y[EE_STATE_WAKE] = temp; + + temp = agg_avg[DUAL_CTX] * 1000ULL; do_div(temp, bcm->aux_data.unit); - bcm->vote_x = temp; + bcm->vote_x[EE_STATE_SLEEP] = temp; - temp = agg_peak * 1000ULL; + temp = agg_peak[DUAL_CTX] * 1000ULL; do_div(temp, bcm->aux_data.unit); - bcm->vote_y = temp; + bcm->vote_y[EE_STATE_SLEEP] = temp; if (bcm->keepalive && bcm->vote_x == 0 && bcm->vote_y == 0) { - bcm->vote_x = 1; - bcm->vote_y = 1; + bcm->vote_x[EE_STATE_WAKE] = 1; + bcm->vote_y[EE_STATE_WAKE] = 1; } bcm->dirty = false; } -static int qcom_icc_aggregate(struct icc_node *node, u32 avg_bw, +static int qcom_icc_aggregate(struct icc_node *node, u8 tag, u32 avg_bw, u32 peak_bw, u32 *agg_avg, u32 *agg_peak) { size_t i; struct qcom_icc_node *qn; + u32 ctx_idx = 0; qn = node->data; + ctx_idx = (!!tag) ? AO_CTX : DUAL_CTX; *agg_avg += avg_bw; *agg_peak = max_t(u32, *agg_peak, peak_bw); - qn->sum_avg = *agg_avg; - qn->max_peak = *agg_peak; + qn->sum_avg[ctx_idx] = *agg_avg; + qn->max_peak[ctx_idx] = *agg_peak; for (i = 0; i < qn->num_bcms; i++) qn->bcms[i]->dirty = true; @@ -675,7 +693,7 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) * Construct the command list based on a pre ordered list of BCMs * based on VCD. */ - tcs_list_gen(&commit_list, cmds, commit_idx); + tcs_list_gen(&commit_list, EE_STATE_WAKE, cmds, commit_idx); if (!commit_idx[0]) return ret; @@ -693,6 +711,37 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) return ret; } + INIT_LIST_HEAD(&commit_list); + + for (i = 0; i < qp->num_bcms; i++) { + /* Only generate WAKE and SLEEP commands if a resource's + * requirements change as the execution environment transitions + * between different power states. + */ + if (qp->bcms[i]->vote_x[EE_STATE_WAKE] != + qp->bcms[i]->vote_x[EE_STATE_SLEEP] || + qp->bcms[i]->vote_y[EE_STATE_WAKE] != + qp->bcms[i]->vote_y[EE_STATE_SLEEP]) { + list_add_tail(&qp->bcms[i]->list, &commit_list); + } + } + + tcs_list_gen(&commit_list, EE_STATE_WAKE, cmds, commit_idx); + + ret = rpmh_write_batch(qp->dev, RPMH_WAKE_ONLY_STATE, cmds, commit_idx); + if (ret) { + pr_err("Error sending WAKE RPMH requests (%d)\n", ret); + return ret; + } + + tcs_list_gen(&commit_list, EE_STATE_SLEEP, cmds, commit_idx); + + ret = rpmh_write_batch(qp->dev, RPMH_SLEEP_STATE, cmds, commit_idx); + if (ret) { + pr_err("Error sending SLEEP RPMH requests (%d)\n", ret); + return ret; + } + return ret; } diff --git a/drivers/interconnect/qcom/smd-rpm.c b/drivers/interconnect/qcom/smd-rpm.c new file mode 100644 index 000000000000..48b7a2a6eb84 --- /dev/null +++ b/drivers/interconnect/qcom/smd-rpm.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RPM over SMD communication wrapper for interconnects + * + * Copyright (C) 2018 Linaro Ltd + * Author: Georgi Djakov <georgi.djakov@linaro.org> + */ + +#include <linux/interconnect-provider.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/soc/qcom/smd-rpm.h> +#include "smd-rpm.h" + +#define RPM_KEY_BW 0x00007762 + +static struct qcom_icc_rpm { + struct qcom_smd_rpm *rpm; +} icc_rpm_smd; + +struct icc_rpm_smd_req { + __le32 key; + __le32 nbytes; + __le32 value; +}; + +bool qcom_icc_rpm_smd_available(void) +{ + if (!icc_rpm_smd.rpm) + return false; + + return true; +} +EXPORT_SYMBOL_GPL(qcom_icc_rpm_smd_available); + +int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val) +{ + struct icc_rpm_smd_req req = { + .key = cpu_to_le32(RPM_KEY_BW), + .nbytes = cpu_to_le32(sizeof(u32)), + .value = cpu_to_le32(val), + }; + + return qcom_rpm_smd_write(icc_rpm_smd.rpm, ctx, rsc_type, id, &req, + sizeof(req)); +} +EXPORT_SYMBOL_GPL(qcom_icc_rpm_smd_send); + +static int qcom_icc_rpm_smd_probe(struct platform_device *pdev) +{ + icc_rpm_smd.rpm = dev_get_drvdata(pdev->dev.parent); + if (!icc_rpm_smd.rpm) { + dev_err(&pdev->dev, "unable to retrieve handle to RPM\n"); + return -ENODEV; + } + + return 0; +} + +static const struct of_device_id qcom_icc_rpm_smd_dt_match[] = { + { .compatible = "qcom,interconnect-smd-rpm", }, + { }, +}; + +MODULE_DEVICE_TABLE(of, qcom_icc_rpm_smd_dt_match); + +static struct platform_driver qcom_interconnect_rpm_smd_driver = { + .driver = { + .name = "qcom-interconnect-smd-rpm", + .of_match_table = qcom_icc_rpm_smd_dt_match, + }, + .probe = qcom_icc_rpm_smd_probe, +}; + +static int __init rpm_smd_interconnect_init(void) +{ + return platform_driver_register(&qcom_interconnect_rpm_smd_driver); +} +subsys_initcall(rpm_smd_interconnect_init); + +static void __exit rpm_smd_interconnect_exit(void) +{ + platform_driver_unregister(&qcom_interconnect_rpm_smd_driver); +} +module_exit(rpm_smd_interconnect_exit) + +MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>"); +MODULE_DESCRIPTION("Qualcomm SMD RPM interconnect driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/qcom/smd-rpm.h b/drivers/interconnect/qcom/smd-rpm.h new file mode 100644 index 000000000000..11c280eb86dc --- /dev/null +++ b/drivers/interconnect/qcom/smd-rpm.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, Linaro Ltd. + * Author: Georgi Djakov <georgi.djakov@linaro.org> + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_SMD_RPM_H +#define __DRIVERS_INTERCONNECT_QCOM_SMD_RPM_H + +#include <linux/soc/qcom/smd-rpm.h> + +bool qcom_icc_rpm_smd_available(void); +int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val); + +#endif diff --git a/include/dt-bindings/interconnect/qcom,msm8916.h b/include/dt-bindings/interconnect/qcom,msm8916.h new file mode 100644 index 000000000000..7531465dd132 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,msm8916.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Qualcomm interconnect IDs + * + * Copyright (c) 2018, Linaro Ltd. + * Author: Georgi Djakov <georgi.djakov@linaro.org> + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H + +#define BIMC_SNOC_SLV 0 +#define MASTER_JPEG 1 +#define MASTER_MDP_PORT0 2 +#define MASTER_QDSS_BAM 3 +#define MASTER_QDSS_ETR 4 +#define MASTER_SNOC_CFG 5 +#define MASTER_VFE 6 +#define MASTER_VIDEO_P0 7 +#define SNOC_MM_INT_0 8 +#define SNOC_MM_INT_1 9 +#define SNOC_MM_INT_2 10 +#define SNOC_MM_INT_BIMC 11 +#define PNOC_SNOC_SLV 12 +#define SLAVE_APSS 13 +#define SLAVE_CATS_128 14 +#define SLAVE_OCMEM_64 15 +#define SLAVE_IMEM 16 +#define SLAVE_QDSS_STM 17 +#define SLAVE_SRVC_SNOC 18 +#define SNOC_BIMC_0_MAS 19 +#define SNOC_BIMC_1_MAS 20 +#define SNOC_INT_0 21 +#define SNOC_INT_1 22 +#define SNOC_INT_BIMC 23 +#define SNOC_PNOC_MAS 24 +#define SNOC_QDSS_INT 25 + +#define BIMC_SNOC_MAS 0 +#define MASTER_AMPSS_M0 1 +#define MASTER_GRAPHICS_3D 2 +#define MASTER_TCU0 3 +#define MASTER_TCU1 4 +#define SLAVE_AMPSS_L2 5 +#define SLAVE_EBI_CH0 6 +#define SNOC_BIMC_0_SLV 7 +#define SNOC_BIMC_1_SLV 8 + +#define MASTER_BLSP_1 0 +#define MASTER_DEHR 1 +#define MASTER_LPASS 2 +#define MASTER_CRYPTO_CORE0 3 +#define MASTER_SDCC_1 4 +#define MASTER_SDCC_2 5 +#define MASTER_SPDM 6 +#define MASTER_USB_HS 7 +#define PNOC_INT_0 8 +#define PNOC_INT_1 9 +#define PNOC_MAS_0 10 +#define PNOC_MAS_1 11 +#define PNOC_SLV_0 12 +#define PNOC_SLV_1 13 +#define PNOC_SLV_2 14 +#define PNOC_SLV_3 15 +#define PNOC_SLV_4 16 +#define PNOC_SLV_8 17 +#define PNOC_SLV_9 18 +#define PNOC_SNOC_MAS 19 +#define SLAVE_BIMC_CFG 20 +#define SLAVE_BLSP_1 21 +#define SLAVE_BOOT_ROM 22 +#define SLAVE_CAMERA_CFG 23 +#define SLAVE_CLK_CTL 24 +#define SLAVE_CRYPTO_0_CFG 25 +#define SLAVE_DEHR_CFG 26 +#define SLAVE_DISPLAY_CFG 27 +#define SLAVE_GRAPHICS_3D_CFG 28 +#define SLAVE_IMEM_CFG 29 +#define SLAVE_LPASS 30 +#define SLAVE_MPM 31 +#define SLAVE_MSG_RAM 32 +#define SLAVE_MSS 33 +#define SLAVE_PDM 34 +#define SLAVE_PMIC_ARB 35 +#define SLAVE_PNOC_CFG 36 +#define SLAVE_PRNG 37 +#define SLAVE_QDSS_CFG 38 +#define SLAVE_RBCPR_CFG 39 +#define SLAVE_SDCC_1 40 +#define SLAVE_SDCC_2 41 +#define SLAVE_SECURITY 42 +#define SLAVE_SNOC_CFG 43 +#define SLAVE_SPDM 44 +#define SLAVE_TCSR 45 +#define SLAVE_TLMM 46 +#define SLAVE_USB_HS 47 +#define SLAVE_VENUS_CFG 48 +#define SNOC_PNOC_SLV 49 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,msm8996.h b/include/dt-bindings/interconnect/qcom,msm8996.h new file mode 100644 index 000000000000..33cbce89b878 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,msm8996.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Qualcomm interconnect IDs + * + * Copyright (c) 2018, Linaro Ltd. + * Author: Georgi Djakov <georgi.djakov@linaro.org> + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H + +#define A0NOC_SNOC_MAS 0 +#define A0NOC_SNOC_SLV 1 +#define A1NOC_SNOC_MAS 2 +#define A1NOC_SNOC_SLV 3 +#define A2NOC_SNOC_MAS 4 +#define A2NOC_SNOC_SLV 5 +#define BIMC_SNOC_1_MAS 6 +#define BIMC_SNOC_MAS 7 +#define MASTER_HMSS 8 +#define MASTER_QDSS_BAM 9 +#define MASTER_QDSS_ETR 10 +#define MASTER_SNOC_CFG 11 +#define SLAVE_APPSS 12 +#define SLAVE_LPASS 13 +#define SLAVE_OCIMEM 14 +#define SLAVE_PCIE_0 15 +#define SLAVE_PCIE_1 16 +#define SLAVE_PCIE_2 17 +#define SLAVE_PIMEM 18 +#define SLAVE_QDSS_STM 19 +#define SLAVE_SERVICE_SNOC 20 +#define SLAVE_SNOC_VMEM 21 +#define SLAVE_USB3 22 +#define SNOC_BIMC_SLV 23 +#define SNOC_CNOC_SLV 24 +#define SNOC_PNOC_SLV 25 + +#define BIMC_SNOC_SLV 0 +#define BIMC_SNOC_1_SLV 1 +#define MASTER_AMPSS_M0 2 +#define MASTER_GRAPHICS_3D 3 +#define MNOC_BIMC_MAS 4 +#define SLAVE_EBI_CH0 5 +#define SLAVE_HMSS_L3 6 +#define SNOC_BIMC_MAS 7 + +#define MASTER_BLSP_1 0 +#define MASTER_BLSP_2 1 +#define MASTER_SDCC_1 2 +#define MASTER_SDCC_2 3 +#define MASTER_SDCC_4 4 +#define MASTER_TSIF 5 +#define MASTER_USB_HS 6 +#define PNOC_A1NOC_SLV 7 +#define SLAVE_AHB2PHY 8 +#define SLAVE_BLSP_1 9 +#define SLAVE_BLSP_2 10 +#define SLAVE_PDM 11 +#define SLAVE_SDCC_1 12 +#define SLAVE_SDCC_2 13 +#define SLAVE_SDCC_4 14 +#define SLAVE_TSIF 15 +#define SLAVE_USB_HS 16 +#define SNOC_PNOC_MAS 17 + +#define CNOC_SNOC_SLV 0 +#define MASTER_QDSS_DAP 1 +#define SLAVE_A0NOC_CFG 2 +#define SLAVE_A0NOC_MPU_CFG 3 +#define SLAVE_A0NOC_SMMU_CFG 4 +#define SLAVE_A1NOC_CFG 5 +#define SLAVE_A1NOC_MPU_CFG 6 +#define SLAVE_A1NOC_SMMU_CFG 7 +#define SLAVE_A2NOC_CFG 8 +#define SLAVE_A2NOC_MPU_CFG 9 +#define SLAVE_A2NOC_SMMU_CFG 10 +#define SLAVE_BIMC_CFG 11 +#define SLAVE_CLK_CTL 12 +#define SLAVE_CNOC_MNOC_CFG 13 +#define SLAVE_CNOC_MNOC_MMSS_CFG 14 +#define SLAVE_CRYPTO_0_CFG 15 +#define SLAVE_DCC_CFG 16 +#define SLAVE_EBI1_PHY_CFG 17 +#define SLAVE_IMEM_CFG 18 +#define SLAVE_LPASS_SMMU_CFG 19 +#define SLAVE_MESSAGE_RAM 20 +#define SLAVE_MPM 21 +#define SLAVE_PCIE_0_CFG 22 +#define SLAVE_PCIE_1_CFG 23 +#define SLAVE_PCIE20_AHB2PHY 24 +#define SLAVE_PCIE_2_CFG 25 +#define SLAVE_PIMEM_CFG 26 +#define SLAVE_PMIC_ARB 27 +#define SLAVE_PRNG 28 +#define SLAVE_QDSS_CFG 29 +#define SLAVE_QDSS_RBCPR_APU_CFG 30 +#define SLAVE_RBCPR_CX 31 +#define SLAVE_RBCPR_MX 32 +#define SLAVE_SNOC_CFG 33 +#define SLAVE_SNOC_MPU_CFG 34 +#define SLAVE_SSC_CFG 35 +#define SLAVE_TCSR 36 +#define SLAVE_TLMM 37 +#define SLAVE_UFS_CFG 38 +#define SNOC_CNOC_MAS 39 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CNOC_MNOC_MMSS_CFG 1 +#define MASTER_CPP 2 +#define MASTER_JPEG 3 +#define MASTER_MDP_PORT0 4 +#define MASTER_MDP_PORT1 5 +#define MASTER_ROTATOR 6 +#define MASTER_SNOC_VMEM 7 +#define MASTER_VFE 8 +#define MASTER_VIDEO_P0 9 +#define MASTER_VIDEO_P0_OCMEM 10 +#define MNOC_BIMC_SLV 11 +#define SLAVE_CAMERA_CFG 12 +#define SLAVE_CAMERA_THROTTLE_CFG 13 +#define SLAVE_CPR_CFG 14 +#define SLAVE_DISPLAY_CFG 15 +#define SLAVE_DISPLAY_THROTTLE_CFG 16 +#define SLAVE_DSA_CFG 17 +#define SLAVE_DSA_MPU_CFG 18 +#define SLAVE_GRAPHICS_3D_CFG 19 +#define SLAVE_MISC_CFG 20 +#define SLAVE_MMAGIC_CFG 21 +#define SLAVE_MMSS_CLK_CFG 22 +#define SLAVE_MNOC_MPU_CFG 23 +#define SLAVE_SERVICE_MNOC 24 +#define SLAVE_SMMU_CPP_CFG 25 +#define SLAVE_SMMU_JPEG_CFG 26 +#define SLAVE_SMMU_MDP_CFG 27 +#define SLAVE_SMMU_ROTATOR_CFG 28 +#define SLAVE_SMMU_VENUS_CFG 29 +#define SLAVE_SMMU_VFE_CFG 30 +#define SLAVE_VENUS_CFG 31 +#define SLAVE_VENUS_THROTTLE_CFG 32 +#define SLAVE_VMEM_CFG 33 +#define SLAVE_VMEM 34 + +#define MASTER_PCIE 0 +#define MASTER_PCIE_1 1 +#define MASTER_PCIE_2 2 + +#define CNOC_A1NOC_MAS 0 +#define MASTER_CRYPTO_CORE0 1 +#define PNOC_A1NOC_MAS 2 + +#define MASTER_IPA 0 +#define MASTER_UFS 1 +#define MASTER_USB3 2 + +#endif diff --git a/include/linux/interconnect-provider.h b/include/linux/interconnect-provider.h index 63caccadc2db..7ea40e82416b 100644 --- a/include/linux/interconnect-provider.h +++ b/include/linux/interconnect-provider.h @@ -45,8 +45,8 @@ struct icc_provider { struct list_head provider_list; struct list_head nodes; int (*set)(struct icc_node *src, struct icc_node *dst); - int (*aggregate)(struct icc_node *node, u32 avg_bw, u32 peak_bw, - u32 *agg_avg, u32 *agg_peak); + int (*aggregate)(struct icc_node *node, u8 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak); struct icc_node* (*xlate)(struct of_phandle_args *spec, void *data); struct device *dev; int users; diff --git a/include/linux/interconnect.h b/include/linux/interconnect.h index dc25864755ba..6b51bf118f13 100644 --- a/include/linux/interconnect.h +++ b/include/linux/interconnect.h @@ -30,6 +30,7 @@ struct icc_path *icc_get(struct device *dev, const int src_id, struct icc_path *of_icc_get(struct device *dev, const char *name); void icc_put(struct icc_path *path); int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw); +void icc_set_tag(struct icc_path *path, u8 tag); #else @@ -54,6 +55,10 @@ static inline int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw) return 0; } +static inline void icc_set_tag(struct icc_path *path, u8 tag) +{ +} + #endif /* CONFIG_INTERCONNECT */ #endif /* __LINUX_INTERCONNECT_H */ |