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| author | Georgi Djakov <georgi.djakov@linaro.org> | 2018-05-16 13:42:00 +0300 |
|---|---|---|
| committer | Georgi Djakov <georgi.djakov@linaro.org> | 2019-01-29 17:25:06 +0200 |
| commit | a540643e88d9c594b384af6b747233c9e4d42678 (patch) | |
| tree | f81ccc4e5459707c77b6e4d0b3ab77ba84f76ec8 | |
| parent | cb4ec1a414f69adb3b14f0775a2ef6c6fcf4a78e (diff) | |
arm64: dts: msm8996: Add interconnect properties for i2c
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/msm8996.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 81893c6756b6..26320a0fac7a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -470,6 +470,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp2_i2c0_default>; pinctrl-1 = <&blsp2_i2c0_sleep>; + interconnects = <&pnoc MASTER_BLSP_2 &bimc SLAVE_EBI_CH0>; + interconnect-names = "ddr"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -482,6 +484,8 @@ clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; + interconnects = <&pnoc MASTER_BLSP_2 &bimc SLAVE_EBI_CH0>; + interconnect-names = "ddr"; status = "disabled"; }; @@ -495,6 +499,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp2_i2c1_default>; pinctrl-1 = <&blsp2_i2c1_sleep>; + interconnects = <&pnoc MASTER_BLSP_2 &bimc SLAVE_EBI_CH0>; + interconnect-names = "ddr"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -520,6 +526,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp1_i2c2_default>; pinctrl-1 = <&blsp1_i2c2_sleep>; + interconnects = <&pnoc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; + interconnect-names = "ddr"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; |