diff options
author | Linaro CI <ci_notify@linaro.org> | 2018-07-28 17:24:13 +0000 |
---|---|---|
committer | Linaro CI <ci_notify@linaro.org> | 2018-07-28 17:24:13 +0000 |
commit | 8d52d03a1c8a31939f83ae1d36dcbcae2b1d2e03 (patch) | |
tree | f78ec2d27ca5936c3a5d9a0798ad0245cf920b89 | |
parent | b7f60f0ec987cadb5673880fa36af8485eedcbe3 (diff) | |
parent | 30ef0f5450ebb28e22a2964d87ca552bc7d34bc8 (diff) |
Merge remote-tracking branch 'slimbus/tracking-qcomlt-slimbus' into integration-linux-qcomlt
-rw-r--r-- | Documentation/devicetree/bindings/slimbus/slim-ngd-qcom-ctrl.txt | 84 | ||||
-rw-r--r-- | drivers/base/regmap/regmap-slimbus.c | 27 | ||||
-rw-r--r-- | drivers/slimbus/Kconfig | 12 | ||||
-rw-r--r-- | drivers/slimbus/Makefile | 5 | ||||
-rw-r--r-- | drivers/slimbus/core.c | 39 | ||||
-rw-r--r-- | drivers/slimbus/messaging.c | 176 | ||||
-rw-r--r-- | drivers/slimbus/qcom-ngd-ctrl.c | 1489 | ||||
-rw-r--r-- | drivers/slimbus/slimbus.h | 124 | ||||
-rw-r--r-- | drivers/slimbus/stream.c | 357 | ||||
-rw-r--r-- | include/linux/slimbus.h | 61 |
10 files changed, 2334 insertions, 40 deletions
diff --git a/Documentation/devicetree/bindings/slimbus/slim-ngd-qcom-ctrl.txt b/Documentation/devicetree/bindings/slimbus/slim-ngd-qcom-ctrl.txt new file mode 100644 index 000000000000..e94a2ad3a710 --- /dev/null +++ b/Documentation/devicetree/bindings/slimbus/slim-ngd-qcom-ctrl.txt @@ -0,0 +1,84 @@ +Qualcomm SLIMBus Non Generic Device (NGD) Controller binding + +SLIMBus NGD controller is a light-weight driver responsible for communicating +with SLIMBus slaves directly over the bus using messaging interface and +communicating with master component residing on ADSP for bandwidth and +data-channel management + +Please refer to slimbus/bus.txt for details of the common SLIMBus bindings. + +- compatible: + Usage: required + Value type: <stringlist> + Definition: must be "qcom,slim-ngd-v<MAJOR>.<MINOR>.<STEP>" + must be one of the following. + "qcom,slim-ngd-v1.5.0" for MSM8996 + "qcom,slim-ngd-v2.1.0" for SDM845 + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: must specify the base address and size of the controller + register space. +- dmas + Usage: required + Value type: <array of phandles> + Definition: List of rx and tx dma channels + +- dma-names + Usage: required + Value type: <stringlist> + Definition: must be "rx" and "tx". + +- interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: must list controller IRQ. + +#address-cells + Usage: required + Value type: <u32> + Definition: Should be 1, reflecting the instance id of ngd. + +#size-cells + Usage: required + Value type: <u32> + Definition: Should be 0 + += NGD Devices +Each subnode represents an instance of NGD, must contain the following +properties: + +- reg: + Usage: required + Value type: <u32> + Definition: Should be instance id of ngd. + +#address-cells + Usage: required + Refer to slimbus/bus.txt for details of the common SLIMBus bindings. + +#size-cells + Usage: required + Refer to slimbus/bus.txt for details of the common SLIMBus bindings. + += EXAMPLE + +slim@91c0000 { + compatible = "qcom,slim-ngd-v1.5.0"; + reg = <0x91c0000 0x2c000>; + interrupts = <0 163 0>; + dmas = <&slimbam 3>, <&slimbam 4>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + ngd@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <1>; + codec@1 { + compatible = "slim217,1a0"; + reg = <1 0>; + }; + }; +}; diff --git a/drivers/base/regmap/regmap-slimbus.c b/drivers/base/regmap/regmap-slimbus.c index 91d501eda8a9..321f3c029250 100644 --- a/drivers/base/regmap/regmap-slimbus.c +++ b/drivers/base/regmap/regmap-slimbus.c @@ -31,9 +31,32 @@ static int regmap_slimbus_byte_reg_write(void *context, unsigned int reg, return slim_writeb(sdev, reg, val); } +#define REG_BYTES 2 + +static int regmap_slimbus_write(void *context, const void *data, size_t count) +{ + struct slim_device *sdev = context; + unsigned short reg; + + reg = *(u16 *)data + 0x800; + + return slim_write(sdev, reg, count - REG_BYTES, data + REG_BYTES); +} + +static int regmap_slimbus_read(void *context, const void *reg, size_t reg_size, + void *val, size_t val_size) +{ + struct slim_device *sdev = context; + + return slim_read(sdev, *(u16 *)reg + 0x800, val_size, val); + +} + static struct regmap_bus regmap_slimbus_bus = { - .reg_write = regmap_slimbus_byte_reg_write, - .reg_read = regmap_slimbus_byte_reg_read, + //.reg_write = regmap_slimbus_byte_reg_write, + //.reg_read = regmap_slimbus_byte_reg_read, + .write = regmap_slimbus_write, + .read = regmap_slimbus_read, .reg_format_endian_default = REGMAP_ENDIAN_LITTLE, .val_format_endian_default = REGMAP_ENDIAN_LITTLE, }; diff --git a/drivers/slimbus/Kconfig b/drivers/slimbus/Kconfig index 1a632fad597e..9d73ad806698 100644 --- a/drivers/slimbus/Kconfig +++ b/drivers/slimbus/Kconfig @@ -15,10 +15,20 @@ if SLIMBUS # SLIMbus controllers config SLIM_QCOM_CTRL tristate "Qualcomm SLIMbus Manager Component" - depends on SLIMBUS depends on HAS_IOMEM help Select driver if Qualcomm's SLIMbus Manager Component is programmed using Linux kernel. +config SLIM_QCOM_NGD_CTRL + tristate "Qualcomm SLIMbus Satellite Non-Generic Device Component" + depends on QCOM_QMI_HELPERS + depends on HAS_IOMEM && DMA_ENGINE + help + Select driver if Qualcomm's SLIMbus Satellite Non-Generic Device + Component is programmed using Linux kernel. + This is light-weight slimbus controller driver responsible for + communicating with slave HW directly over the bus using messaging + interface, and communicating with master component residing on ADSP + for bandwidth and data-channel management. endif diff --git a/drivers/slimbus/Makefile b/drivers/slimbus/Makefile index a35a3da4eb78..d9aa011b6804 100644 --- a/drivers/slimbus/Makefile +++ b/drivers/slimbus/Makefile @@ -3,8 +3,11 @@ # Makefile for kernel SLIMbus framework. # obj-$(CONFIG_SLIMBUS) += slimbus.o -slimbus-y := core.o messaging.o sched.o +slimbus-y := core.o messaging.o sched.o stream.o #Controllers obj-$(CONFIG_SLIM_QCOM_CTRL) += slim-qcom-ctrl.o slim-qcom-ctrl-y := qcom-ctrl.o + +obj-$(CONFIG_SLIM_QCOM_NGD_CTRL) += slim-qcom-ngd-ctrl.o +slim-qcom-ngd-ctrl-y := qcom-ngd-ctrl.o diff --git a/drivers/slimbus/core.c b/drivers/slimbus/core.c index 7ddfc675b131..88248a4ecad9 100644 --- a/drivers/slimbus/core.c +++ b/drivers/slimbus/core.c @@ -356,6 +356,45 @@ struct slim_device *slim_get_device(struct slim_controller *ctrl, } EXPORT_SYMBOL_GPL(slim_get_device); +static int of_slim_match_dev(struct device *dev, void *data) +{ + struct device_node *np = data; + struct slim_device *sbdev = to_slim_device(dev); + + return (sbdev->dev.of_node == np); +} + +static struct slim_device *of_find_slim_device(struct slim_controller *ctrl, + struct device_node *np) +{ + struct slim_device *sbdev; + struct device *dev; + + dev = device_find_child(ctrl->dev, np, of_slim_match_dev); + if (dev) { + sbdev = to_slim_device(dev); + return sbdev; + } + + return NULL; +} + +/** + * of_slim_get_device() - get handle to a device using dt node. + * + * @ctrl: Controller on which this device will be added/queried + * @np: node pointer to device + * + * Return: pointer to a device if it has already reported. Creates a new + * device and returns pointer to it if the device has not yet enumerated. + */ +struct slim_device *of_slim_get_device(struct slim_controller *ctrl, + struct device_node *np) +{ + return of_find_slim_device(ctrl, np); +} +EXPORT_SYMBOL_GPL(of_slim_get_device); + static int slim_device_alloc_laddr(struct slim_device *sbdev, bool report_present) { diff --git a/drivers/slimbus/messaging.c b/drivers/slimbus/messaging.c index 457ea1f8db30..9608f6309f9e 100644 --- a/drivers/slimbus/messaging.c +++ b/drivers/slimbus/messaging.c @@ -7,6 +7,70 @@ #include <linux/pm_runtime.h> #include "slimbus.h" +static char *mc_strs[] = { +[0x0] ="SLIM_USR_MC_MASTER_CAPABILITY", +[0x1] ="SLIM_MSG_MC_REPORT_PRESENT", +[0x2] ="SLIM_MSG_MC_ASSIGN_LOGICAL_ADDRESS", +[0x4] ="SLIM_MSG_MC_RESET_DEVICE", +[0x8] ="SLIM_MSG_MC_CHANGE_LOGICAL_ADDRESS", +[0x9] ="SLIM_MSG_MC_CHANGE_ARBITRATION_PRIORITY", +[0xC] ="SLIM_MSG_MC_REQUEST_SELF_ANNOUNCEMENT", +[0xD] ="SLIM_USR_MC_ADDR_QUERY", +[0xE] ="SLIM_USR_MC_ADDR_REPLY", +[0xF] ="SLIM_MSG_MC_REPORT_ABSENT", +[0x10] ="SLIM_MSG_MC_CONNECT_SOURCE", +[0x11] ="SLIM_MSG_MC_CONNECT_SINK", +[0x14] ="SLIM_MSG_MC_DISCONNECT_PORT", +[0x18] ="SLIM_MSG_MC_CHANGE_CONTENT", +[0x20] ="SLIM_MSG_MC_REQUEST_INFORMATION", +[0x21] ="SLIM_MSG_MC_REQUEST_CLEAR_INFORMATION", +[0x24] ="SLIM_MSG_MC_REPLY_INFORMATION", +[0x28] ="SLIM_MSG_MC_CLEAR_INFORMATION", +[0x29] ="SLIM_MSG_MC_REPORT_INFORMATION", +[0x40] ="SLIM_MSG_MC_BEGIN_RECONFIGURATION", +[0x44] ="SLIM_MSG_MC_NEXT_ACTIVE_FRAMER", +[0x45] ="SLIM_MSG_MC_NEXT_SUBFRAME_MODE", +[0x46] ="SLIM_MSG_MC_NEXT_CLOCK_GEAR", +[0x47] ="SLIM_MSG_MC_NEXT_ROOT_FREQUENCY", +[0x4A] ="SLIM_MSG_MC_NEXT_PAUSE_CLOCK", +[0x4B] ="SLIM_MSG_MC_NEXT_RESET_BUS", +[0x4C] ="SLIM_MSG_MC_NEXT_SHUTDOWN_BUS", +[0x50] ="SLIM_MSG_MC_NEXT_DEFINE_CHANNEL", +[0x51] ="SLIM_MSG_MC_NEXT_DEFINE_CONTENT", +[0x54] ="SLIM_MSG_MC_NEXT_ACTIVATE_CHANNEL", +[0x55] ="SLIM_MSG_MC_NEXT_DEACTIVATE_CHANNEL", +[0x58] ="SLIM_MSG_MC_NEXT_REMOVE_CHANNEL", +[0x5F] ="SLIM_MSG_MC_RECONFIGURE_NOW", +[0x60] ="SLIM_MSG_MC_REQUEST_VALUE", +[0x61] ="SLIM_MSG_MC_REQUEST_CHANGE_VALUE", +[0x64] ="SLIM_MSG_MC_REPLY_VALUE", +[0x68] ="SLIM_MSG_MC_CHANGE_VALUE", +[0x25] = "SLIM_USR_MC_GENERIC_ACK", +[0x0] = "SLIM_USR_MC_MASTER_CAPABILITY", +[0x1] = "SLIM_USR_MC_REPORT_SATELLITE", +[0xD] = "SLIM_USR_MC_ADDR_QUERY", +[0xE] = "SLIM_USR_MC_ADDR_REPLY", +[0x20] = "SLIM_USR_MC_DEFINE_CHAN", +[0x21] = "SLIM_USR_MC_DEF_ACT_CHAN", +[0x23] = "SLIM_USR_MC_CHAN_CTRL", +[0x24] = "SLIM_USR_MC_RECONFIG_NOW", +[0x28] = "SLIM_USR_MC_REQ_BW", +[0x2C] = "SLIM_USR_MC_CONNECT_SRC", +[0x2D] = "SLIM_USR_MC_CONNECT_SINK", +[0x2E] = "SLIM_USR_MC_DISCONNECT_PORT", +}; + +char * get_mc_name(int mc) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mc_strs); i++) + if (i == mc) + return mc_strs[i]; + + return "NULL"; +} +EXPORT_SYMBOL_GPL(get_mc_name); /** * slim_msg_response() - Deliver Message response received from a device to the * framework. @@ -56,6 +120,69 @@ void slim_msg_response(struct slim_controller *ctrl, u8 *reply, u8 tid, u8 len) EXPORT_SYMBOL_GPL(slim_msg_response); /** + * slim_alloc_tid() - Allocate a tid to txn + * + * @ctrl: Controller handle + * @txn: transaction to be allocated with tid. + * + * Called by controller to assign a tid totransaction + * + * Return: zero on success with valid txn->tid and error code on failures. + */ +int slim_alloc_tid(struct slim_controller *ctrl, struct slim_msg_txn *txn) +{ + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&ctrl->txn_lock, flags); + ret = idr_alloc_cyclic(&ctrl->tid_idr, txn, 0, SLIM_MAX_TIDS, GFP_ATOMIC); + if (ret < 0) { + spin_unlock_irqrestore(&ctrl->txn_lock, flags); + return ret; + } + txn->tid = ret; + spin_unlock_irqrestore(&ctrl->txn_lock, flags); + return 0; +} +EXPORT_SYMBOL_GPL(slim_alloc_tid); + +/** + * slim_prepare_txn() - Prepare a transaction + * + * @ctrl: Controller handle + * @txn: transaction to be prepared + * @done: completion for transaction if msg does not have completion + * @need_tid: flag to indicate if tid is required for this txn + * note, user defined commands would need tid. + * + * Called by controller to prepare a transaction + * + * Return: zero on success and error code on failures. + */ +int slim_prepare_txn(struct slim_controller *ctrl, struct slim_msg_txn *txn, + struct completion *done, bool need_tid) +{ + int ret; + + txn->need_tid = need_tid; + if (!need_tid) + return 0; + + ret = slim_alloc_tid(ctrl, txn); + if (ret < 0) + return ret; + + if (!txn->msg->comp) + txn->comp = done; + else + txn->comp = txn->msg->comp; + + return ret; +} +EXPORT_SYMBOL_GPL(slim_prepare_txn); + + +/** * slim_do_transfer() - Process a SLIMbus-messaging transaction * * @ctrl: Controller handle @@ -70,10 +197,9 @@ EXPORT_SYMBOL_GPL(slim_msg_response); */ int slim_do_transfer(struct slim_controller *ctrl, struct slim_msg_txn *txn) { - DECLARE_COMPLETION_ONSTACK(done); - bool need_tid = false, clk_pause_msg = false; + bool clk_pause_msg = false; unsigned long flags; - int ret, tid, timeout; + int ret, timeout; /* * do not vote for runtime-PM if the transactions are part of clock @@ -94,28 +220,8 @@ int slim_do_transfer(struct slim_controller *ctrl, struct slim_msg_txn *txn) } } - need_tid = slim_tid_txn(txn->mt, txn->mc); - - if (need_tid) { - spin_lock_irqsave(&ctrl->txn_lock, flags); - tid = idr_alloc(&ctrl->tid_idr, txn, 0, - SLIM_MAX_TIDS, GFP_ATOMIC); - txn->tid = tid; - - if (!txn->msg->comp) - txn->comp = &done; - else - txn->comp = txn->comp; - - spin_unlock_irqrestore(&ctrl->txn_lock, flags); - - if (tid < 0) - return tid; - } - ret = ctrl->xfer_msg(ctrl, txn); - - if (ret && need_tid && !txn->msg->comp) { + if (!ret && txn->need_tid && !txn->msg->comp) { unsigned long ms = txn->rl + HZ; timeout = wait_for_completion_timeout(txn->comp, @@ -123,7 +229,7 @@ int slim_do_transfer(struct slim_controller *ctrl, struct slim_msg_txn *txn) if (!timeout) { ret = -ETIMEDOUT; spin_lock_irqsave(&ctrl->txn_lock, flags); - idr_remove(&ctrl->tid_idr, tid); + idr_remove(&ctrl->tid_idr, txn->tid); spin_unlock_irqrestore(&ctrl->txn_lock, flags); } } @@ -133,13 +239,14 @@ int slim_do_transfer(struct slim_controller *ctrl, struct slim_msg_txn *txn) txn->mt, txn->mc, txn->la, ret); slim_xfer_err: - if (!clk_pause_msg && (!need_tid || ret == -ETIMEDOUT)) { + if (!clk_pause_msg && (!txn->need_tid || ret == -ETIMEDOUT)) { /* * remove runtime-pm vote if this was TX only, or * if there was error during this transaction */ pm_runtime_mark_last_busy(ctrl->dev); - pm_runtime_mark_last_busy(ctrl->dev); + pm_runtime_put_autosuspend(ctrl->dev); + } return ret; } @@ -205,6 +312,8 @@ int slim_xfer_msg(struct slim_device *sbdev, struct slim_val_inf *msg, DEFINE_SLIM_LDEST_TXN(txn_stack, mc, 6, sbdev->laddr, msg); struct slim_msg_txn *txn = &txn_stack; struct slim_controller *ctrl = sbdev->ctrl; + DECLARE_COMPLETION_ONSTACK(done); + bool need_tid = false; int ret; u16 sl; @@ -232,10 +341,16 @@ int slim_xfer_msg(struct slim_device *sbdev, struct slim_val_inf *msg, break; } - if (slim_tid_txn(txn->mt, txn->mc)) + if (slim_tid_txn(txn->mt, txn->mc)) { txn->rl++; + need_tid = true; + } + + ret = slim_prepare_txn(ctrl, txn, &done, need_tid); + if (!ret) + return slim_do_transfer(ctrl, txn); - return slim_do_transfer(ctrl, txn); + return ret; } EXPORT_SYMBOL_GPL(slim_xfer_msg); @@ -246,6 +361,7 @@ static void slim_fill_msg(struct slim_val_inf *msg, u32 addr, msg->num_bytes = count; msg->rbuf = rbuf; msg->wbuf = wbuf; + msg->comp = NULL; } /** @@ -307,7 +423,7 @@ int slim_write(struct slim_device *sdev, u32 addr, size_t count, u8 *val) { struct slim_val_inf msg; - slim_fill_msg(&msg, addr, count, val, NULL); + slim_fill_msg(&msg, addr, count, NULL, val); return slim_xfer_msg(sdev, &msg, SLIM_MSG_MC_CHANGE_VALUE); } diff --git a/drivers/slimbus/qcom-ngd-ctrl.c b/drivers/slimbus/qcom-ngd-ctrl.c new file mode 100644 index 000000000000..6d70fadcc7d8 --- /dev/null +++ b/drivers/slimbus/qcom-ngd-ctrl.c @@ -0,0 +1,1489 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. +// Copyright (c) 2018, Linaro Limited +//TODO: +// Bandwidth Mangement +// +#include <linux/irq.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <linux/dmaengine.h> +#include <linux/slimbus.h> +#include <linux/delay.h> +#include <linux/pm_runtime.h> +#include <linux/of.h> +#include <linux/io.h> +#include <linux/soc/qcom/qmi.h> +#include <net/sock.h> +#include "slimbus.h" + +/* NGD (Non-ported Generic Device) registers */ +#define NGD_CFG 0x0 +#define NGD_CFG_ENABLE BIT(0) +#define NGD_CFG_RX_MSGQ_EN BIT(1) +#define NGD_CFG_TX_MSGQ_EN BIT(2) +#define NGD_STATUS 0x4 +#define NGD_LADDR BIT(1) +#define NGD_RX_MSGQ_CFG 0x8 +#define NGD_INT_EN 0x10 +#define NGD_INT_RECFG_DONE BIT(24) +#define NGD_INT_TX_NACKED_2 BIT(25) +#define NGD_INT_MSG_BUF_CONTE BIT(26) +#define NGD_INT_MSG_TX_INVAL BIT(27) +#define NGD_INT_IE_VE_CHG BIT(28) +#define NGD_INT_DEV_ERR BIT(29) +#define NGD_INT_RX_MSG_RCVD BIT(30) +#define NGD_INT_TX_MSG_SENT BIT(31) +#define NGD_INT_STAT 0x14 +#define NGD_INT_CLR 0x18 +#define DEF_NGD_INT_MASK (NGD_INT_TX_NACKED_2 | NGD_INT_MSG_BUF_CONTE | \ + NGD_INT_MSG_TX_INVAL | NGD_INT_IE_VE_CHG | \ + NGD_INT_DEV_ERR | NGD_INT_TX_MSG_SENT | \ + NGD_INT_RX_MSG_RCVD) + +/* Slimbus QMI service */ +#define SLIMBUS_QMI_SVC_ID 0x0301 +#define SLIMBUS_QMI_SVC_V1 1 +#define SLIMBUS_QMI_INS_ID 0 +#define SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01 0x0020 +#define SLIMBUS_QMI_SELECT_INSTANCE_RESP_V01 0x0020 +#define SLIMBUS_QMI_POWER_REQ_V01 0x0021 +#define SLIMBUS_QMI_POWER_RESP_V01 0x0021 +#define SLIMBUS_QMI_CHECK_FRAMER_STATUS_REQ 0x0022 +#define SLIMBUS_QMI_CHECK_FRAMER_STATUS_RESP 0x0022 +#define SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN 14 +#define SLIMBUS_QMI_POWER_RESP_MAX_MSG_LEN 7 +#define SLIMBUS_QMI_SELECT_INSTANCE_REQ_MAX_MSG_LEN 14 +#define SLIMBUS_QMI_SELECT_INSTANCE_RESP_MAX_MSG_LEN 7 +#define SLIMBUS_QMI_CHECK_FRAMER_STAT_RESP_MAX_MSG_LEN 7 +/* QMI response timeout of 500ms */ +#define SLIMBUS_QMI_RESP_TOUT 1000 + +/* User defined commands */ +#define SLIM_USR_MC_GENERIC_ACK 0x25 +#define SLIM_USR_MC_MASTER_CAPABILITY 0x0 +#define SLIM_USR_MC_REPORT_SATELLITE 0x1 +#define SLIM_USR_MC_ADDR_QUERY 0xD +#define SLIM_USR_MC_ADDR_REPLY 0xE +#define SLIM_USR_MC_DEFINE_CHAN 0x20 +#define SLIM_USR_MC_DEF_ACT_CHAN 0x21 +#define SLIM_USR_MC_CHAN_CTRL 0x23 +#define SLIM_USR_MC_RECONFIG_NOW 0x24 +#define SLIM_USR_MC_REQ_BW 0x28 +#define SLIM_USR_MC_CONNECT_SRC 0x2C +#define SLIM_USR_MC_CONNECT_SINK 0x2D +#define SLIM_USR_MC_DISCONNECT_PORT 0x2E +#define SLIM_USR_MC_REPEAT_CHANGE_VALUE 0x0 + +#define QCOM_SLIM_NGD_AUTOSUSPEND MSEC_PER_SEC +#define SLIM_RX_MSGQ_TIMEOUT_VAL 0x10000 + +#define SLIM_LA_MGR 0xFF +#define SLIM_ROOT_FREQ 24576000 +#define LADDR_RETRY 5 + +/* Per spec.max 40 bytes per received message */ +#define SLIM_MSGQ_BUF_LEN 40 +#define QCOM_SLIM_NGD_DESC_NUM 32 + +#define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \ + ((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16)) + +#define INIT_MX_RETRIES 10 +#define DEF_RETRY_MS 10 +#define SAT_MAGIC_LSB 0xD9 +#define SAT_MAGIC_MSB 0xC5 +#define SAT_MSG_VER 0x1 +#define SAT_MSG_PROT 0x1 +#define to_ngd(d) container_of(d, struct qcom_slim_ngd, dev) + +struct ngd_reg_offset_data { + u32 offset, size; +}; + +static const struct ngd_reg_offset_data ngd_v1_5_offset_info = { + .offset = 0x1000, + .size = 0x1000, +}; + +enum qcom_slim_ngd_state { + QCOM_SLIM_NGD_CTRL_AWAKE, + QCOM_SLIM_NGD_CTRL_IDLE, + QCOM_SLIM_NGD_CTRL_ASLEEP, + QCOM_SLIM_NGD_CTRL_DOWN, +}; + +struct qcom_slim_ngd_qmi { + struct qmi_handle qmi; + struct sockaddr_qrtr svc_info; + struct qmi_handle svc_event_hdl; + struct qmi_response_type_v01 resp; + struct qmi_handle *handle; + struct completion qmi_comp; +}; + +struct qcom_slim_ngd_ctrl; +struct qcom_slim_ngd; + +struct qcom_slim_ngd_dma_desc { + struct dma_async_tx_descriptor *desc; + struct qcom_slim_ngd_ctrl *ctrl; + struct completion *comp; + dma_cookie_t cookie; + dma_addr_t phys; + void *base; +}; + +struct qcom_slim_ngd { + struct platform_device *pdev; + void __iomem *base; + int id; +}; + +struct qcom_slim_ngd_ctrl { + struct slim_framer framer; + struct slim_controller ctrl; + struct qcom_slim_ngd_qmi qmi; + struct qcom_slim_ngd *ngd; + struct device *dev; + void __iomem *base; + struct dma_chan *dma_rx_channel; + struct dma_chan *dma_tx_channel; + struct qcom_slim_ngd_dma_desc rx_desc[QCOM_SLIM_NGD_DESC_NUM]; + struct qcom_slim_ngd_dma_desc txdesc[QCOM_SLIM_NGD_DESC_NUM]; + struct completion reconf; + struct work_struct m_work; + struct workqueue_struct *mwq; + spinlock_t tx_buf_lock; + enum qcom_slim_ngd_state state; + dma_addr_t rx_phys_base; + dma_addr_t tx_phys_base; + void *rx_base; + void *tx_base; + int tx_tail; + int tx_head; + u32 ver; +}; + +enum slimbus_mode_enum_type_v01 { + /* To force a 32 bit signed enum. Do not change or use*/ + SLIMBUS_MODE_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN, + SLIMBUS_MODE_SATELLITE_V01 = 1, + SLIMBUS_MODE_MASTER_V01 = 2, + SLIMBUS_MODE_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX, +}; + +enum slimbus_pm_enum_type_v01 { + /* To force a 32 bit signed enum. Do not change or use*/ + SLIMBUS_PM_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN, + SLIMBUS_PM_INACTIVE_V01 = 1, + SLIMBUS_PM_ACTIVE_V01 = 2, + SLIMBUS_PM_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX, +}; + +enum slimbus_resp_enum_type_v01 { + SLIMBUS_RESP_ENUM_TYPE_MIN_VAL_V01 = INT_MIN, + SLIMBUS_RESP_SYNCHRONOUS_V01 = 1, + SLIMBUS_RESP_ENUM_TYPE_MAX_VAL_V01 = INT_MAX, +}; + +struct slimbus_select_inst_req_msg_v01 { + uint32_t instance; + uint8_t mode_valid; + enum slimbus_mode_enum_type_v01 mode; +}; + +struct slimbus_select_inst_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +struct slimbus_power_req_msg_v01 { + enum slimbus_pm_enum_type_v01 pm_req; + uint8_t resp_type_valid; + enum slimbus_resp_enum_type_v01 resp_type; +}; + +struct slimbus_power_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +static struct qmi_elem_info slimbus_select_inst_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(uint32_t), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct slimbus_select_inst_req_msg_v01, + instance), + .ei_array = NULL, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct slimbus_select_inst_req_msg_v01, + mode_valid), + .ei_array = NULL, + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(enum slimbus_mode_enum_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct slimbus_select_inst_req_msg_v01, + mode), + .ei_array = NULL, + }, + { + .data_type = QMI_EOTI, + .elem_len = 0, + .elem_size = 0, + .array_type = NO_ARRAY, + .tlv_type = 0x00, + .offset = 0, + .ei_array = NULL, + }, +}; + +static struct qmi_elem_info slimbus_select_inst_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct slimbus_select_inst_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .elem_len = 0, + .elem_size = 0, + .array_type = NO_ARRAY, + .tlv_type = 0x00, + .offset = 0, + .ei_array = NULL, + }, +}; + +static struct qmi_elem_info slimbus_power_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(enum slimbus_pm_enum_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct slimbus_power_req_msg_v01, + pm_req), + .ei_array = NULL, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(uint8_t), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct slimbus_power_req_msg_v01, + resp_type_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum slimbus_resp_enum_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct slimbus_power_req_msg_v01, + resp_type), + }, + { + .data_type = QMI_EOTI, + .elem_len = 0, + .elem_size = 0, + .array_type = NO_ARRAY, + .tlv_type = 0x00, + .offset = 0, + .ei_array = NULL, + }, +}; + +static struct qmi_elem_info slimbus_power_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct slimbus_power_resp_msg_v01, resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .elem_len = 0, + .elem_size = 0, + .array_type = NO_ARRAY, + .tlv_type = 0x00, + .offset = 0, + .ei_array = NULL, + }, +}; + +static int qcom_slim_qmi_send_select_inst_req(struct qcom_slim_ngd_ctrl *ctrl, + struct slimbus_select_inst_req_msg_v01 *req) +{ + struct slimbus_select_inst_resp_msg_v01 resp = { { 0, 0 } }; + struct qmi_txn txn; + int rc; + + rc = qmi_txn_init(ctrl->qmi.handle, &txn, + slimbus_select_inst_resp_msg_v01_ei, &resp); + if (rc < 0) { + dev_err(ctrl->dev, "QMI TXN init fail: %d\n", rc); + return rc; + } + + rc = qmi_send_request(ctrl->qmi.handle, NULL, &txn, + SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01, + SLIMBUS_QMI_SELECT_INSTANCE_REQ_MAX_MSG_LEN, + slimbus_select_inst_req_msg_v01_ei, req); + if (rc < 0) { + dev_err(ctrl->dev, "QMI send req fail %d\n", rc); + qmi_txn_cancel(&txn); + return rc; + } + + rc = qmi_txn_wait(&txn, SLIMBUS_QMI_RESP_TOUT); + if (rc < 0) { + dev_err(ctrl->dev, "QMI TXN wait fail: %d\n", rc); + return rc; + } + /* Check the response */ + if (resp.resp.result != QMI_RESULT_SUCCESS_V01) { + dev_err(ctrl->dev, "QMI request failed 0x%x\n", + resp.resp.result); + return -EREMOTEIO; + } + + return 0; +} + +static void qcom_slim_qmi_power_resp_cb(struct qmi_handle *handle, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, const void *data) +{ + struct slimbus_power_resp_msg_v01 *resp; + + resp = (struct slimbus_power_resp_msg_v01 *)data; + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) + pr_err("QMI power request failed 0x%x\n", + resp->resp.result); + + complete(&txn->completion); +} + +static int qcom_slim_qmi_send_power_request(struct qcom_slim_ngd_ctrl *ctrl, + struct slimbus_power_req_msg_v01 *req) +{ + struct slimbus_power_resp_msg_v01 resp = { { 0, 0 } }; + struct qmi_txn txn; + int rc; + + rc = qmi_txn_init(ctrl->qmi.handle, &txn, + slimbus_power_resp_msg_v01_ei, &resp); + + rc = qmi_send_request(ctrl->qmi.handle, NULL, &txn, + SLIMBUS_QMI_POWER_REQ_V01, + SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN, + slimbus_power_req_msg_v01_ei, req); + if (rc < 0) { + dev_err(ctrl->dev, "QMI send req fail %d\n", rc); + qmi_txn_cancel(&txn); + return rc; + } + + rc = qmi_txn_wait(&txn, SLIMBUS_QMI_RESP_TOUT); + if (rc < 0) { + dev_err(ctrl->dev, "QMI TXN wait fail: %d\n", rc); + return rc; + } + + /* Check the response */ + if (resp.resp.result != QMI_RESULT_SUCCESS_V01) { + dev_err(ctrl->dev, "QMI request failed 0x%x\n", + resp.resp.result); + return -EREMOTEIO; + } + + return 0; +} + +static struct qmi_msg_handler qcom_slim_qmi_msg_handlers[] = { + { + .type = QMI_RESPONSE, + .msg_id = SLIMBUS_QMI_POWER_RESP_V01, + .ei = slimbus_power_resp_msg_v01_ei, + .decoded_size = sizeof(struct slimbus_power_resp_msg_v01), + .fn = qcom_slim_qmi_power_resp_cb, + }, + {} +}; + +static int qcom_slim_qmi_init(struct qcom_slim_ngd_ctrl *ctrl, + bool apps_is_master) +{ + struct slimbus_select_inst_req_msg_v01 req; + struct qmi_handle *handle; + int rc; + + handle = devm_kzalloc(ctrl->dev, sizeof(*handle), GFP_KERNEL); + if (!handle) + return -ENOMEM; + + rc = qmi_handle_init(handle, SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN, + NULL, qcom_slim_qmi_msg_handlers); + if (rc < 0) { + dev_err(ctrl->dev, "QMI client init failed: %d\n", rc); + goto qmi_handle_init_failed; + } + + rc = kernel_connect(handle->sock, + (struct sockaddr *)&ctrl->qmi.svc_info, + sizeof(ctrl->qmi.svc_info), 0); + if (rc < 0) { + dev_err(ctrl->dev, "Remote Service connect failed: %d\n", rc); + goto qmi_connect_to_service_failed; + } + + /* Instance is 0 based */ + req.instance = (ctrl->ngd->id >> 1); + req.mode_valid = 1; + + /* Mode indicates the role of the ADSP */ + if (apps_is_master) + req.mode = SLIMBUS_MODE_SATELLITE_V01; + else + req.mode = SLIMBUS_MODE_MASTER_V01; + + ctrl->qmi.handle = handle; + + rc = qcom_slim_qmi_send_select_inst_req(ctrl, &req); + if (rc) { + dev_err(ctrl->dev, "failed to select h/w instance\n"); + goto qmi_select_instance_failed; + } + + return 0; + +qmi_select_instance_failed: + ctrl->qmi.handle = NULL; +qmi_connect_to_service_failed: + qmi_handle_release(handle); +qmi_handle_init_failed: + devm_kfree(ctrl->dev, handle); + return rc; +} + +static void qcom_slim_qmi_exit(struct qcom_slim_ngd_ctrl *ctrl) +{ + if (!ctrl->qmi.handle) + return; + + qmi_handle_release(ctrl->qmi.handle); + devm_kfree(ctrl->dev, ctrl->qmi.handle); + ctrl->qmi.handle = NULL; +} + +static int qcom_slim_qmi_power_request(struct qcom_slim_ngd_ctrl *ctrl, + bool active) +{ + struct slimbus_power_req_msg_v01 req; + + if (active) + req.pm_req = SLIMBUS_PM_ACTIVE_V01; + else + req.pm_req = SLIMBUS_PM_INACTIVE_V01; + + req.resp_type_valid = 0; + + return qcom_slim_qmi_send_power_request(ctrl, &req); +} + +static u32 *qcom_slim_ngd_tx_msg_get(struct qcom_slim_ngd_ctrl *ctrl, int len, + struct completion *comp) +{ + struct qcom_slim_ngd_dma_desc *desc; + unsigned long flags; + + spin_lock_irqsave(&ctrl->tx_buf_lock, flags); + + if ((ctrl->tx_tail + 1) % QCOM_SLIM_NGD_DESC_NUM == ctrl->tx_head) { + spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags); + return NULL; + } + desc = &ctrl->txdesc[ctrl->tx_tail]; + desc->base = ctrl->tx_base + ctrl->tx_tail * SLIM_MSGQ_BUF_LEN; + desc->comp = comp; + ctrl->tx_tail = (ctrl->tx_tail + 1) % QCOM_SLIM_NGD_DESC_NUM; + + spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags); + + return desc->base; +} + +static void qcom_slim_ngd_tx_msg_dma_cb(void *args) +{ + struct qcom_slim_ngd_dma_desc *desc = args; + struct qcom_slim_ngd_ctrl *ctrl = desc->ctrl; + unsigned long flags; + + spin_lock_irqsave(&ctrl->tx_buf_lock, flags); + + if (desc->comp) { + complete(desc->comp); + desc->comp = NULL; + } + + ctrl->tx_head = (ctrl->tx_head + 1) % QCOM_SLIM_NGD_DESC_NUM; + spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags); +} + +static int qcom_slim_ngd_tx_msg_post(struct qcom_slim_ngd_ctrl *ctrl, + void *buf, int len) +{ + struct qcom_slim_ngd_dma_desc *desc; + unsigned long flags; + int index, offset; + + spin_lock_irqsave(&ctrl->tx_buf_lock, flags); + offset = buf - ctrl->tx_base; + index = offset/SLIM_MSGQ_BUF_LEN; + + desc = &ctrl->txdesc[index]; + desc->phys = ctrl->tx_phys_base + offset; + desc->base = ctrl->tx_base + offset; + desc->ctrl = ctrl; + len = (len + 3) & 0xfc; + + desc->desc = dmaengine_prep_slave_single(ctrl->dma_tx_channel, + desc->phys, len, + DMA_MEM_TO_DEV, + DMA_PREP_INTERRUPT); + if (!desc->desc) { + dev_err(ctrl->dev, "unable to prepare channel\n"); + spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags); + return -EINVAL; + } + + desc->desc->callback = qcom_slim_ngd_tx_msg_dma_cb; + desc->desc->callback_param = desc; + desc->desc->cookie = dmaengine_submit(desc->desc); + dma_async_issue_pending(ctrl->dma_tx_channel); + spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags); + + return 0; +} + +static void qcom_slim_ngd_rx(struct qcom_slim_ngd_ctrl *ctrl, u8 *buf) +{ + u8 mc, mt, len; + + mt = SLIM_HEADER_GET_MT(buf[0]); + len = SLIM_HEADER_GET_RL(buf[0]); + mc = SLIM_HEADER_GET_MC(buf[1]); + + if (mc == SLIM_USR_MC_MASTER_CAPABILITY && + mt == SLIM_MSG_MT_SRC_REFERRED_USER) + queue_work(ctrl->mwq, &ctrl->m_work); + + if (mc == SLIM_MSG_MC_REPLY_INFORMATION || + mc == SLIM_MSG_MC_REPLY_VALUE || (mc == SLIM_USR_MC_ADDR_REPLY && + mt == SLIM_MSG_MT_SRC_REFERRED_USER) || + (mc == SLIM_USR_MC_GENERIC_ACK && mt == SLIM_MSG_MT_SRC_REFERRED_USER)) { + slim_msg_response(&ctrl->ctrl, &buf[4], buf[3], len - 4); + pm_runtime_mark_last_busy(ctrl->dev); + } +} + +static void qcom_slim_ngd_rx_msgq_cb(void *args) +{ + struct qcom_slim_ngd_dma_desc *desc = args; + struct qcom_slim_ngd_ctrl *ctrl = desc->ctrl; + + qcom_slim_ngd_rx(ctrl, (u8 *)desc->base); + /* Add descriptor back to the queue */ + desc->desc = dmaengine_prep_slave_single(ctrl->dma_rx_channel, + desc->phys, SLIM_MSGQ_BUF_LEN, + DMA_DEV_TO_MEM, + DMA_PREP_INTERRUPT); + if (!desc->desc) { + dev_err(ctrl->dev, "Unable to prepare rx channel\n"); + return; + } + + desc->desc->callback = qcom_slim_ngd_rx_msgq_cb; + desc->desc->callback_param = desc; + desc->desc->cookie = dmaengine_submit(desc->desc); + dma_async_issue_pending(ctrl->dma_rx_channel); +} + +static int qcom_slim_ngd_post_rx_msgq(struct qcom_slim_ngd_ctrl *ctrl) +{ + struct qcom_slim_ngd_dma_desc *desc; + int i; + + for (i = 0; i < QCOM_SLIM_NGD_DESC_NUM; i++) { + desc = &ctrl->rx_desc[i]; + desc->phys = ctrl->rx_phys_base + i * SLIM_MSGQ_BUF_LEN; + desc->ctrl = ctrl; + desc->base = ctrl->rx_base + i * SLIM_MSGQ_BUF_LEN; + desc->desc = dmaengine_prep_slave_single(ctrl->dma_rx_channel, + desc->phys, SLIM_MSGQ_BUF_LEN, + DMA_DEV_TO_MEM, + DMA_PREP_INTERRUPT); + if (!desc->desc) { + dev_err(ctrl->dev, "Unable to prepare rx channel\n"); + return -EINVAL; + } + + desc->desc->callback = qcom_slim_ngd_rx_msgq_cb; + desc->desc->callback_param = desc; + desc->desc->cookie = dmaengine_submit(desc->desc); + } + dma_async_issue_pending(ctrl->dma_rx_channel); + + return 0; +} + +static int qcom_slim_ngd_init_rx_msgq(struct qcom_slim_ngd_ctrl *ctrl) +{ + struct device *dev = ctrl->dev; + int ret, size; + + ctrl->dma_rx_channel = dma_request_slave_channel(dev, "rx"); + if (!ctrl->dma_rx_channel) { + dev_err(dev, "Failed to request dma channels"); + return -EINVAL; + } + + size = QCOM_SLIM_NGD_DESC_NUM * SLIM_MSGQ_BUF_LEN; + ctrl->rx_base = dma_alloc_coherent(dev, size, &ctrl->rx_phys_base, + GFP_KERNEL); + if (!ctrl->rx_base) { + dev_err(dev, "dma_alloc_coherent failed\n"); + ret = -ENOMEM; + goto rel_rx; + } + + ret = qcom_slim_ngd_post_rx_msgq(ctrl); + if (ret) { + dev_err(dev, "post_rx_msgq() failed 0x%x\n", ret); + goto rx_post_err; + } + + return 0; + +rx_post_err: + dma_free_coherent(dev, size, ctrl->rx_base, ctrl->rx_phys_base); +rel_rx: + dma_release_channel(ctrl->dma_rx_channel); + return ret; +} + +static int qcom_slim_ngd_init_tx_msgq(struct qcom_slim_ngd_ctrl *ctrl) +{ + struct device *dev = ctrl->dev; + unsigned long flags; + int ret = 0; + int size; + + ctrl->dma_tx_channel = dma_request_slave_channel(dev, "tx"); + if (!ctrl->dma_tx_channel) { + dev_err(dev, "Failed to request dma channels"); + return -EINVAL; + } + + size = ((QCOM_SLIM_NGD_DESC_NUM + 1) * SLIM_MSGQ_BUF_LEN); + ctrl->tx_base = dma_alloc_coherent(dev, size, &ctrl->tx_phys_base, + GFP_KERNEL); + if (!ctrl->tx_base) { + dev_err(dev, "dma_alloc_coherent failed\n"); + ret = -EINVAL; + goto rel_tx; + } + + spin_lock_irqsave(&ctrl->tx_buf_lock, flags); + ctrl->tx_tail = 0; + ctrl->tx_head = 0; + spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags); + + return 0; +rel_tx: + dma_release_channel(ctrl->dma_tx_channel); + return ret; +} + +static int qcom_slim_ngd_init_dma(struct qcom_slim_ngd_ctrl *ctrl) +{ + int ret = 0; + + ret = qcom_slim_ngd_init_rx_msgq(ctrl); + if (ret) { + dev_err(ctrl->dev, "rx dma init failed\n"); + return ret; + } + + ret = qcom_slim_ngd_init_tx_msgq(ctrl); + if (ret) + dev_err(ctrl->dev, "tx dma init failed\n"); + + return ret; +} + +static irqreturn_t qcom_slim_ngd_interrupt(int irq, void *d) +{ + struct qcom_slim_ngd_ctrl *ctrl = d; + void __iomem *base = ctrl->ngd->base; + u32 stat = readl(base + NGD_INT_STAT); + + if ((stat & NGD_INT_MSG_BUF_CONTE) || + (stat & NGD_INT_MSG_TX_INVAL) || (stat & NGD_INT_DEV_ERR) || + (stat & NGD_INT_TX_NACKED_2)) { + dev_err(ctrl->dev, "Error Interrupt received 0x%x\n", stat); + } + + writel(stat, base + NGD_INT_CLR); + + return IRQ_HANDLED; +} + +static int qcom_slim_ngd_xfer_msg(struct slim_controller *sctrl, + struct slim_msg_txn *txn) +{ + struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(sctrl->dev); + DECLARE_COMPLETION_ONSTACK(tx_sent); + DECLARE_COMPLETION_ONSTACK(done); + int ret, timeout, i; + u8 wbuf[SLIM_MSGQ_BUF_LEN]; + u8 rbuf[SLIM_MSGQ_BUF_LEN]; + u32 *pbuf; + u8 *puc; + u8 la = txn->la; + + if (txn->mc & SLIM_MSG_CLK_PAUSE_SEQ_FLG) + return -EPROTONOSUPPORT; + + if (txn->mt == SLIM_MSG_MT_CORE && + (txn->mc >= SLIM_MSG_MC_BEGIN_RECONFIGURATION && + txn->mc <= SLIM_MSG_MC_RECONFIGURE_NOW)) + return 0; + + if (txn->dt == SLIM_MSG_DEST_ENUMADDR) + return -EPROTONOSUPPORT; + + if (txn->msg->num_bytes > SLIM_MSGQ_BUF_LEN || + txn->rl > SLIM_MSGQ_BUF_LEN) { + dev_err(ctrl->dev, "msg exeeds HW limit\n"); + return -EINVAL; + } + + pbuf = qcom_slim_ngd_tx_msg_get(ctrl, txn->rl, &tx_sent); + if (!pbuf) { + dev_err(ctrl->dev, "Message buffer unavailable\n"); + return -ENOMEM; + } + + if (txn->mt == SLIM_MSG_MT_CORE && + (txn->mc == SLIM_MSG_MC_CONNECT_SOURCE || + txn->mc == SLIM_MSG_MC_CONNECT_SINK || + txn->mc == SLIM_MSG_MC_DISCONNECT_PORT)) { + + txn->mt = SLIM_MSG_MT_DEST_REFERRED_USER; + if (txn->mc == SLIM_MSG_MC_CONNECT_SOURCE) + txn->mc = SLIM_USR_MC_CONNECT_SRC; + else if (txn->mc == SLIM_MSG_MC_CONNECT_SINK) + txn->mc = SLIM_USR_MC_CONNECT_SINK; + else if (txn->mc == SLIM_MSG_MC_DISCONNECT_PORT) + txn->mc = SLIM_USR_MC_DISCONNECT_PORT; + i = 0; + wbuf[i++] = txn->la; + la = SLIM_LA_MGR; + wbuf[i++] = txn->msg->wbuf[0]; + if (txn->mc != SLIM_USR_MC_DISCONNECT_PORT) + wbuf[i++] = txn->msg->wbuf[1]; + + txn->comp = &done; + ret = slim_alloc_tid(sctrl, txn); + if (ret) { + dev_err(ctrl->dev, "Unable to allocate TID\n"); + return ret; + } + + wbuf[i++] = txn->tid; + + txn->msg->num_bytes = i; + txn->msg->wbuf = wbuf; + txn->msg->rbuf = rbuf; + txn->rl = txn->msg->num_bytes + 4; + } + + /* HW expects length field to be excluded */ + txn->rl--; + puc = (u8 *)pbuf; + *pbuf = 0; + if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) { + *pbuf = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, txn->mc, 0, + la); + puc += 3; + } else { + *pbuf = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, txn->mc, 1, + la); + puc += 2; + } + + if (txn->mc != SLIM_USR_MC_ADDR_QUERY && slim_tid_txn(txn->mt, txn->mc)) + *(puc++) = txn->tid; + + if (slim_ec_txn(txn->mt, txn->mc)) { + *(puc++) = (txn->ec & 0xFF); + *(puc++) = (txn->ec >> 8) & 0xFF; + } + + if (txn->msg && txn->msg->wbuf) + memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes); + + ret = qcom_slim_ngd_tx_msg_post(ctrl, pbuf, txn->rl); + if (ret) + return ret; + + timeout = wait_for_completion_timeout(&tx_sent, HZ); + if (!timeout) { + dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc, + txn->mt); + return -ETIMEDOUT; + } + + if (txn->mt == SLIM_MSG_MT_DEST_REFERRED_USER && + (txn->mc == SLIM_USR_MC_CONNECT_SRC || + txn->mc == SLIM_USR_MC_CONNECT_SINK || + txn->mc == SLIM_USR_MC_DISCONNECT_PORT)) { + timeout = wait_for_completion_timeout(&done, HZ); + if (!timeout) { + dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc, + txn->mt); + //FIXME purge all the transactions if they are failed... + return -ETIMEDOUT; + } + + } + + return 0; +} + +static int qcom_slim_ngd_enable_stream(struct slim_stream_runtime *rt) +{ + struct slim_device *sdev = rt->dev; + struct slim_controller *ctrl = sdev->ctrl; + struct slim_val_inf msg = {0}; + u8 wbuf[SLIM_MSGQ_BUF_LEN]; + u8 rbuf[SLIM_MSGQ_BUF_LEN]; + DECLARE_COMPLETION_ONSTACK(done); + struct slim_msg_txn txn = {0,}; + int i, timeout, ret; + + txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER; + txn.dt = SLIM_MSG_DEST_LOGICALADDR; + txn.la = SLIM_LA_MGR; + txn.ec = 0; + txn.msg = &msg; + txn.msg->num_bytes = 0; + txn.msg->wbuf = wbuf; + txn.msg->rbuf = rbuf; + + for (i = 0; i < rt->num_ports; i++) { + struct slim_port *port = &rt->ports[i]; + if (txn.msg->num_bytes == 0) { + int fl = 1; /* Frequency Locked for ISO Protocol */ + int segrate = rt->ratem;//rt->rate/ctrl->a_framer->superfreq; + int segint = SLIM_SLOTS_PER_SUPERFRAME/segrate; + int pprate, exp; + + /* Per protocol, only last 5 bits for client no. */ + wbuf[txn.msg->num_bytes++] = (u8) (0 << 5) | (sdev->laddr & 0x1f); + + wbuf[txn.msg->num_bytes] = rt->bps >> 2; + exp = segint % 3; + if (exp) + wbuf[txn.msg->num_bytes] |= 1 << 5; + + txn.msg->num_bytes++; + wbuf[txn.msg->num_bytes++] = exp << 4 | rt->prot; + pprate = slim_find_prrate(rt->rate); + wbuf[txn.msg->num_bytes++] = pprate | (fl << 7); + txn.comp = &done; + ret = slim_alloc_tid(ctrl, &txn); + if (ret) { + pr_err("no tid for channel define?\n"); + return -ENXIO; + } + wbuf[txn.msg->num_bytes++] = txn.tid; + } + wbuf[txn.msg->num_bytes++] = port->ch.id; + } + + txn.mc = SLIM_USR_MC_DEF_ACT_CHAN; + txn.rl = txn.msg->num_bytes + 4; + ret = qcom_slim_ngd_xfer_msg(ctrl, &txn); + + timeout = wait_for_completion_timeout(&done, HZ); + if (!timeout) { + dev_err(&sdev->dev, "TX timed out:MC:0x%x,mt:0x%x", txn.mc, + txn.mt); + } + + txn.mc = SLIM_USR_MC_RECONFIG_NOW; + txn.msg->num_bytes = 2; + wbuf[1] = sdev->laddr; + txn.rl = txn.msg->num_bytes + 4; + + txn.comp = &done; + ret = slim_alloc_tid(ctrl, &txn); + if (ret) + return ret; + wbuf[0] = txn.tid; + ret = qcom_slim_ngd_xfer_msg(ctrl, &txn); + timeout = wait_for_completion_timeout(&done, HZ); + if (!timeout) { + dev_err(&sdev->dev, "TX timed out:MC:0x%x,mt:0x%x", txn.mc, + txn.mt); + } + + return 0; +} + +static int qcom_slim_ngd_get_laddr(struct slim_controller *sctrl, + struct slim_eaddr *ea, u8 *laddr) +{ + DECLARE_COMPLETION_ONSTACK(done); + struct slim_val_inf msg = {0}; + struct slim_msg_txn txn; + u8 wbuf[10] = {0}; + u8 rbuf[10] = {0}; + int ret; + + txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER; + txn.dt = SLIM_MSG_DEST_LOGICALADDR; + txn.la = SLIM_LA_MGR; + txn.ec = 0; + + txn.mc = SLIM_USR_MC_ADDR_QUERY; + txn.rl = 11; + txn.msg = &msg; + txn.msg->num_bytes = 7; + txn.msg->wbuf = wbuf; + txn.msg->rbuf = rbuf; + + ret = slim_prepare_txn(sctrl, &txn, &done, true); + if (ret) + return ret; + + wbuf[0] = (u8)txn.tid; + memcpy(&wbuf[1], ea, sizeof(*ea)); + ret = slim_do_transfer(sctrl, &txn); + + *laddr = rbuf[6]; + + return ret; +} + +static int qcom_slim_ngd_exit_dma(struct qcom_slim_ngd_ctrl *ctrl) +{ + if (ctrl->dma_rx_channel) { + dmaengine_terminate_sync(ctrl->dma_rx_channel); + dma_release_channel(ctrl->dma_rx_channel); + } + + if (ctrl->dma_tx_channel) { + dmaengine_terminate_sync(ctrl->dma_tx_channel); + dma_release_channel(ctrl->dma_tx_channel); + } + + ctrl->dma_tx_channel = ctrl->dma_rx_channel = NULL; + + return 0; +} + +static void qcom_slim_ngd_setup(struct qcom_slim_ngd_ctrl *ctrl) +{ + u32 cfg = readl_relaxed(ctrl->ngd->base); + + if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) + qcom_slim_ngd_init_dma(ctrl); + + /* By default enable message queues */ + cfg |= NGD_CFG_RX_MSGQ_EN; + cfg |= NGD_CFG_TX_MSGQ_EN; + + /* Enable NGD if it's not already enabled*/ + if (!(cfg & NGD_CFG_ENABLE)) + cfg |= NGD_CFG_ENABLE; + + writel_relaxed(cfg, ctrl->ngd->base); +} + +static int qcom_slim_ngd_power_up(struct qcom_slim_ngd_ctrl *ctrl) +{ + enum qcom_slim_ngd_state cur_state = ctrl->state; + struct qcom_slim_ngd *ngd = ctrl->ngd; + u32 laddr, rx_msgq; + int timeout, ret = 0; + + if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) { + timeout = wait_for_completion_timeout(&ctrl->qmi.qmi_comp, HZ); + if (!timeout) + return -EREMOTEIO; + } + + if (ctrl->state == QCOM_SLIM_NGD_CTRL_ASLEEP || + ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) { + ret = qcom_slim_qmi_power_request(ctrl, true); + if (ret) { + dev_err(ctrl->dev, "SLIM QMI power request failed:%d\n", + ret); + return ret; + } + } + + ctrl->ver = readl_relaxed(ctrl->base); + /* Version info in 16 MSbits */ + ctrl->ver >>= 16; + + laddr = readl_relaxed(ngd->base + NGD_STATUS); + if (laddr & NGD_LADDR) { + /* + * external MDM restart case where ADSP itself was active framer + * For example, modem restarted when playback was active + */ + if (cur_state == QCOM_SLIM_NGD_CTRL_AWAKE) { + dev_info(ctrl->dev, "Subsys restart: ADSP active framer\n"); + return 0; + } + return 0; + } + + writel_relaxed(DEF_NGD_INT_MASK, ngd->base + NGD_INT_EN); + rx_msgq = readl_relaxed(ngd->base + NGD_RX_MSGQ_CFG); + + writel_relaxed(rx_msgq|SLIM_RX_MSGQ_TIMEOUT_VAL, + ngd->base + NGD_RX_MSGQ_CFG); + qcom_slim_ngd_setup(ctrl); + + timeout = wait_for_completion_timeout(&ctrl->reconf, HZ); + if (!timeout) { + dev_err(ctrl->dev, "capability exchange timed-out\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static void qcom_slim_ngd_notify_slaves(struct qcom_slim_ngd_ctrl *ctrl) +{ + struct slim_device *sbdev; + struct device_node *node; + + for_each_child_of_node(ctrl->ngd->pdev->dev.of_node, node) { + sbdev = of_slim_get_device(&ctrl->ctrl, node); + if (!sbdev) + continue; + + if (slim_get_logical_addr(sbdev)) + dev_err(ctrl->dev, "Failed to get logical address\n"); + } +} + +static void qcom_slim_ngd_master_worker(struct work_struct *work) +{ + struct qcom_slim_ngd_ctrl *ctrl; + struct slim_msg_txn txn; + struct slim_val_inf msg = {0}; + int retries = 0; + u8 wbuf[8]; + int ret = 0; + + ctrl = container_of(work, struct qcom_slim_ngd_ctrl, m_work); + txn.dt = SLIM_MSG_DEST_LOGICALADDR; + txn.ec = 0; + txn.mc = SLIM_USR_MC_REPORT_SATELLITE; + txn.mt = SLIM_MSG_MT_SRC_REFERRED_USER; + txn.la = SLIM_LA_MGR; + wbuf[0] = SAT_MAGIC_LSB; + wbuf[1] = SAT_MAGIC_MSB; + wbuf[2] = SAT_MSG_VER; + wbuf[3] = SAT_MSG_PROT; + txn.msg = &msg; + txn.msg->wbuf = wbuf; + txn.msg->num_bytes = 4; + txn.rl = 8; + + dev_info(ctrl->dev, "SLIM SAT: Rcvd master capability\n"); + +capability_retry: + ret = qcom_slim_ngd_xfer_msg(&ctrl->ctrl, &txn); + if (!ret) { + if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP) + complete(&ctrl->reconf); + else + dev_err(ctrl->dev, "unexpected state:%d\n", + ctrl->state); + + if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) + qcom_slim_ngd_notify_slaves(ctrl); + + } else if (ret == -EIO) { + dev_err(ctrl->dev, "capability message NACKed, retrying\n"); + if (retries < INIT_MX_RETRIES) { + msleep(DEF_RETRY_MS); + retries++; + goto capability_retry; + } + } else { + dev_err(ctrl->dev, "SLIM: capability TX failed:%d\n", ret); + } +} + +static int qcom_slim_ngd_runtime_resume(struct device *dev) +{ + struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev); + int ret = 0; + + if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP) + ret = qcom_slim_ngd_power_up(ctrl); + if (ret) { + /* Did SSR cause this power up failure */ + if (ctrl->state != QCOM_SLIM_NGD_CTRL_DOWN) + ctrl->state = QCOM_SLIM_NGD_CTRL_ASLEEP; + else + dev_err(ctrl->dev, "HW wakeup attempt during SSR\n"); + } else { + ctrl->state = QCOM_SLIM_NGD_CTRL_AWAKE; + } + + return 0; +} + +static int qcom_slim_ngd_enable(struct qcom_slim_ngd_ctrl *ctrl, bool enable) +{ + if (enable) { + int ret = qcom_slim_qmi_init(ctrl, false); + + if (ret) { + dev_err(ctrl->dev, "qmi init fail, ret:%d, state:%d\n", + ret, ctrl->state); + return ret; + } + /* controller state should be in sync with framework state */ + complete(&ctrl->qmi.qmi_comp); + if (!pm_runtime_enabled(ctrl->dev) || + !pm_runtime_suspended(ctrl->dev)) + qcom_slim_ngd_runtime_resume(ctrl->dev); + else + pm_runtime_resume(ctrl->dev); + pm_runtime_mark_last_busy(ctrl->dev); + pm_runtime_put(ctrl->dev); + } else { + qcom_slim_qmi_exit(ctrl); + } + + return 0; +} + +static int qcom_slim_ngd_qmi_new_server(struct qmi_handle *hdl, + struct qmi_service *service) +{ + struct qcom_slim_ngd_qmi *qmi = + container_of(hdl, struct qcom_slim_ngd_qmi, svc_event_hdl); + struct qcom_slim_ngd_ctrl *ctrl = + container_of(qmi, struct qcom_slim_ngd_ctrl, qmi); + + qmi->svc_info.sq_family = AF_QIPCRTR; + qmi->svc_info.sq_node = service->node; + qmi->svc_info.sq_port = service->port; + + qcom_slim_ngd_enable(ctrl, true); + + return 0; +} + +static void qcom_slim_ngd_qmi_del_server(struct qmi_handle *hdl, + struct qmi_service *service) +{ + struct qcom_slim_ngd_qmi *qmi = + container_of(hdl, struct qcom_slim_ngd_qmi, svc_event_hdl); + + qmi->svc_info.sq_node = 0; + qmi->svc_info.sq_port = 0; +} + +static struct qmi_ops qcom_slim_ngd_qmi_svc_event_ops = { + .new_server = qcom_slim_ngd_qmi_new_server, + .del_server = qcom_slim_ngd_qmi_del_server, +}; + +static int qcom_slim_ngd_qmi_svc_event_init(struct qcom_slim_ngd_ctrl *ctrl) +{ + struct qcom_slim_ngd_qmi *qmi = &ctrl->qmi; + int ret; + + ret = qmi_handle_init(&qmi->svc_event_hdl, 0, + &qcom_slim_ngd_qmi_svc_event_ops, NULL); + if (ret < 0) { + dev_err(ctrl->dev, "qmi_handle_init failed: %d\n", ret); + return ret; + } + + ret = qmi_add_lookup(&qmi->svc_event_hdl, SLIMBUS_QMI_SVC_ID, + SLIMBUS_QMI_SVC_V1, SLIMBUS_QMI_INS_ID); + if (ret < 0) { + dev_err(ctrl->dev, "qmi_add_lookup failed: %d\n", ret); + qmi_handle_release(&qmi->svc_event_hdl); + } + return ret; +} + +static void qcom_slim_ngd_qmi_svc_event_deinit(struct qcom_slim_ngd_qmi *qmi) +{ + qmi_handle_release(&qmi->svc_event_hdl); +} + +static struct platform_driver qcom_slim_ngd_driver; +#define QCOM_SLIM_NGD_DRV_NAME "qcom,slim-ngd" + +static const struct of_device_id qcom_slim_ngd_dt_match[] = { + { + .compatible = "qcom,slim-ngd-v1.5.0", + .data = &ngd_v1_5_offset_info, + }, + {} +}; + +MODULE_DEVICE_TABLE(of, qcom_slim_ngd_dt_match); + +static int of_qcom_slim_ngd_register(struct device *parent, + struct qcom_slim_ngd_ctrl *ctrl) +{ + const struct ngd_reg_offset_data *data; + struct qcom_slim_ngd *ngd; + struct device_node *node; + u32 id; + + for_each_available_child_of_node(parent->of_node, node) { + if (of_property_read_u32(node, "reg", &id)) + continue; + + ngd = kzalloc(sizeof(*ngd), GFP_KERNEL); + if (!ngd) + return -ENOMEM; + + ngd->pdev = platform_device_alloc(QCOM_SLIM_NGD_DRV_NAME, id); + ngd->id = id; + ngd->pdev->dev.parent = parent; + ngd->pdev->driver_override = QCOM_SLIM_NGD_DRV_NAME; + ngd->pdev->dev.of_node = node; + ctrl->ngd = ngd; + platform_set_drvdata(ngd->pdev, ctrl); + + platform_device_add(ngd->pdev); + data = of_match_node(qcom_slim_ngd_dt_match, parent->of_node)->data; + ngd->base = ctrl->base + ngd->id * data->offset + (ngd->id - 1) * data->size; + ctrl->ngd = ngd; + platform_driver_register(&qcom_slim_ngd_driver); + + return 0; + } + + return -ENODEV; +} + + +static int qcom_slim_ngd_probe(struct platform_device *pdev) +{ + struct qcom_slim_ngd_ctrl *ctrl = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; + int ret; + + ctrl->ctrl.dev = dev; + ret = slim_register_controller(&ctrl->ctrl); + if (ret) { + dev_err(dev, "error adding slim controller\n"); + return ret; + } + + pm_runtime_use_autosuspend(dev); + pm_runtime_set_autosuspend_delay(dev, QCOM_SLIM_NGD_AUTOSUSPEND); + pm_runtime_set_suspended(dev); + pm_runtime_enable(dev); + pm_runtime_get_noresume(dev); + ret = qcom_slim_ngd_qmi_svc_event_init(ctrl); + if (ret) { + dev_err(&pdev->dev, "QMI service registration failed:%d", ret); + goto err; + } + + INIT_WORK(&ctrl->m_work, qcom_slim_ngd_master_worker); + ctrl->mwq = create_singlethread_workqueue("ngd_master"); + if (!ctrl->mwq) { + dev_err(&pdev->dev, "Failed to start master worker\n"); + ret = -ENOMEM; + goto wq_err; + } + + return 0; +err: + slim_unregister_controller(&ctrl->ctrl); +wq_err: + qcom_slim_ngd_qmi_svc_event_deinit(&ctrl->qmi); + if (ctrl->mwq) + destroy_workqueue(ctrl->mwq); + + return 0; +} + +static int qcom_slim_ngd_ctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct qcom_slim_ngd_ctrl *ctrl; + struct resource *res; + int ret; + + ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + + dev_set_drvdata(dev, ctrl); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + ctrl->base = devm_ioremap_resource(dev, res); + if (IS_ERR(ctrl->base)) + return PTR_ERR(ctrl->base); + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(&pdev->dev, "no slimbus IRQ resource\n"); + return -ENODEV; + } + + ret = devm_request_irq(dev, res->start, qcom_slim_ngd_interrupt, + IRQF_TRIGGER_HIGH, "slim-ngd", ctrl); + if (ret) { + dev_err(&pdev->dev, "request IRQ failed\n"); + return ret; + } + + ctrl->dev = dev; + ctrl->framer.rootfreq = SLIM_ROOT_FREQ >> 3; + ctrl->framer.superfreq = + ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8; + + ctrl->ctrl.a_framer = &ctrl->framer; + ctrl->ctrl.clkgear = SLIM_MAX_CLK_GEAR; + ctrl->ctrl.get_laddr = qcom_slim_ngd_get_laddr; + ctrl->ctrl.enable_stream = qcom_slim_ngd_enable_stream; + ctrl->ctrl.xfer_msg = qcom_slim_ngd_xfer_msg; + ctrl->ctrl.wakeup = NULL; + ctrl->state = QCOM_SLIM_NGD_CTRL_DOWN; + + spin_lock_init(&ctrl->tx_buf_lock); + init_completion(&ctrl->reconf); + init_completion(&ctrl->qmi.qmi_comp); + + return of_qcom_slim_ngd_register(dev, ctrl); +} + +static int qcom_slim_ngd_ctrl_remove(struct platform_device *pdev) +{ + platform_driver_unregister(&qcom_slim_ngd_driver); + + return 0; +} + +static int qcom_slim_ngd_remove(struct platform_device *pdev) +{ + struct qcom_slim_ngd_ctrl *ctrl = platform_get_drvdata(pdev); + + pm_runtime_disable(&pdev->dev); + slim_unregister_controller(&ctrl->ctrl); + qcom_slim_ngd_exit_dma(ctrl); + qcom_slim_ngd_qmi_svc_event_deinit(&ctrl->qmi); + if (ctrl->mwq) + destroy_workqueue(ctrl->mwq); + + kfree(ctrl->ngd); + ctrl->ngd = NULL; + return 0; +} + +static int qcom_slim_ngd_runtime_idle(struct device *dev) +{ + struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev); + + if (ctrl->state == QCOM_SLIM_NGD_CTRL_AWAKE) + ctrl->state = QCOM_SLIM_NGD_CTRL_IDLE; + pm_request_autosuspend(dev); + return -EAGAIN; +} + +#ifdef CONFIG_PM +static int qcom_slim_ngd_runtime_suspend(struct device *dev) +{ + struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev); + int ret = 0; + + ret = qcom_slim_qmi_power_request(ctrl, false); + if (ret && ret != -EBUSY) + dev_info(ctrl->dev, "slim resource not idle:%d\n", ret); + if (!ret || ret == -ETIMEDOUT) + ctrl->state = QCOM_SLIM_NGD_CTRL_ASLEEP; + + return ret; +} +#endif + +static const struct dev_pm_ops qcom_slim_ngd_dev_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS( + qcom_slim_ngd_runtime_suspend, + qcom_slim_ngd_runtime_resume, + qcom_slim_ngd_runtime_idle + ) +}; + +static struct platform_driver qcom_slim_ngd_ctrl_driver = { + .probe = qcom_slim_ngd_ctrl_probe, + .remove = qcom_slim_ngd_ctrl_remove, + .driver = { + .name = "qcom,slim-ngd-ctrl", + .of_match_table = qcom_slim_ngd_dt_match, + }, +}; + +static struct platform_driver qcom_slim_ngd_driver = { + .probe = qcom_slim_ngd_probe, + .remove = qcom_slim_ngd_remove, + .driver = { + .name = QCOM_SLIM_NGD_DRV_NAME, + .pm = &qcom_slim_ngd_dev_pm_ops, + }, +}; + +module_platform_driver(qcom_slim_ngd_ctrl_driver); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Qualcomm SLIMBus NGD controller"); diff --git a/drivers/slimbus/slimbus.h b/drivers/slimbus/slimbus.h index 79f8e05d92dd..1d5017b50a5c 100644 --- a/drivers/slimbus/slimbus.h +++ b/drivers/slimbus/slimbus.h @@ -17,6 +17,8 @@ /* SLIMbus message types. Related to interpretation of message code. */ #define SLIM_MSG_MT_CORE 0x0 +#define SLIM_MSG_MT_DEST_REFERRED_USER 0x2 +#define SLIM_MSG_MT_SRC_REFERRED_USER 0x6 /* * SLIM Broadcast header format @@ -43,11 +45,28 @@ #define SLIM_MSG_MC_ASSIGN_LOGICAL_ADDRESS 0x2 #define SLIM_MSG_MC_REPORT_ABSENT 0xF +/* Data channel management messages */ +#define SLIM_MSG_MC_CONNECT_SOURCE 0x10 +#define SLIM_MSG_MC_CONNECT_SINK 0x11 +#define SLIM_MSG_MC_DISCONNECT_PORT 0x14 +#define SLIM_MSG_MC_CHANGE_CONTENT 0x18 + /* Clock pause Reconfiguration messages */ #define SLIM_MSG_MC_BEGIN_RECONFIGURATION 0x40 #define SLIM_MSG_MC_NEXT_PAUSE_CLOCK 0x4A +#define SLIM_MSG_MC_NEXT_DEFINE_CHANNEL 0x50 +#define SLIM_MSG_MC_NEXT_DEFINE_CONTENT 0x51 +#define SLIM_MSG_MC_NEXT_ACTIVATE_CHANNEL 0x54 +#define SLIM_MSG_MC_NEXT_DEACTIVATE_CHANNEL 0x55 +#define SLIM_MSG_MC_NEXT_REMOVE_CHANNEL 0x58 #define SLIM_MSG_MC_RECONFIGURE_NOW 0x5F +/* + * Clock pause flag to indicate that the reconfig message + * corresponds to clock pause sequence + */ +#define SLIM_MSG_CLK_PAUSE_SEQ_FLG (1U << 8) + /* Clock pause values per SLIMbus spec */ #define SLIM_CLK_FAST 0 #define SLIM_CLK_CONST_PHASE 1 @@ -61,7 +80,16 @@ /* Standard values per SLIMbus spec needed by controllers and devices */ #define SLIM_MAX_CLK_GEAR 10 #define SLIM_MIN_CLK_GEAR 1 +#define SLIM_SLOT_LEN_BITS 4 +/* Standard values per SLIMbus spec needed by controllers and devices */ +#define SLIM_CL_PER_SUPERFRAME 6144 +#define SLIM_CL_PER_SUPERFRAME_DIV8 (SLIM_CL_PER_SUPERFRAME >> 3) +#define SLIM_SLOTS_PER_SUPERFRAME (SLIM_CL_PER_SUPERFRAME >> 2) +#define SLIM_MAX_TXNS 256 +#define SLIM_SL_PER_SUPERFRAME (SLIM_CL_PER_SUPERFRAME >> 2) +#define SLIM_FRM_SLOTS_PER_SUPERFRAME 16 +#define SLIM_GDE_SLOTS_PER_SUPERFRAME 2 /* Manager's logical address is set to 0xFF per spec */ #define SLIM_LA_MANAGER 0xFF @@ -102,6 +130,7 @@ struct slim_framer { * @msg: Elemental access message to be read/written * @comp: completion if read/write is synchronous, used internally * for tid based transactions. + * @need_tid: flag indicating if a tid is required for this txn */ struct slim_msg_txn { u8 rl; @@ -113,6 +142,7 @@ struct slim_msg_txn { u8 la; struct slim_val_inf *msg; struct completion *comp; + bool need_tid; }; /* Frequently used message transaction structures */ @@ -159,6 +189,88 @@ struct slim_sched { struct mutex m_reconf; }; +enum slim_port_direction { + SLIM_PORT_DIRECTION_INVALID = 0, //FIXME + SLIM_PORT_SOURCE = 1, + SLIM_PORT_SINK = 2, +}; + +enum slim_port_state { + SLIM_PORT_DISCONNECTED = 0, + SLIM_PORT_UNCONFIGURED, /* EP in Port is connected to Channel, No data trasnmission*/ + SLIM_PORT_CONFIGURED, /* after DEFINE_CH/CONTENT/ACTIVE */ +}; + +enum slim_channel_state { + SLIM_CH_INACTIVE = 0, /* After reset or after DEACTIVATE or REMOVE CHANNEL */ + SLIM_CH_ALLOCATED, /* A Channel Number is allocated */ + SLIM_CH_ASSOCIATED, /* Channel and EP are associated with Port CONNECT_SOURCE/SINK*/ + SLIM_CH_DEFINED, /* DEFINE CHANNEL */ + SLIM_CH_ACTIVE, /* NEXT_ACTIVE_CHANNEL */ + SLIM_CH_CONENT_DEFINED, /* DEFINE CONENT */ +}; + +#define SLIM_MAX_PORTS 32 + +struct slim_port_config { + int num; +// int ch_mask; + enum slim_port_direction dir; + int port_mask; /* A SLIMBus Device may have frmo 0 to 31 Ports (inclusive) */ +}; + +struct slim_channel_config { + int num; + int tx_ch_mask; + int rx_ch_mask; +}; + +struct slim_channel { + int id; + int ratem; + int seg_dist; + int data_len; + int proto; + int prrate; + enum slim_channel_state state; +}; + +struct slim_port { + int id; + enum slim_port_direction direction; + enum slim_port_state state; + struct slim_channel ch; +}; + +/* + * enum slim_ch_rate: Most commonly used frequency rate families. + * Use 1HZ for push-pull transport. + * 4KHz and 11.025KHz are most commonly used in audio applications. + * Typically, slimbus runs at frequencies to support channels running at 4KHz + * and/or 11.025KHz isochronously. + */ +enum slim_ch_rate { + SLIM_RATE_1HZ, + SLIM_RATE_4000HZ, + SLIM_RATE_11025HZ, +}; + +struct slim_stream_runtime { + struct slim_device *dev; + unsigned int rate; + unsigned int bps; + enum slim_stream_direction direction; + enum slim_channel_proto prot; + + //??? FIXME + unsigned int ratem; + unsigned int baser; + + int num_ports; + struct slim_port ports[]; +}; + + /** * struct slim_controller - Controls every instance of SLIMbus * (similar to 'master' on SPI) @@ -229,6 +341,12 @@ struct slim_controller { struct slim_eaddr *ea, u8 laddr); int (*get_laddr)(struct slim_controller *ctrl, struct slim_eaddr *ea, u8 *laddr); + int (*alloc_bandwidth)(struct slim_stream_runtime *rt); + int (*enable_stream)(struct slim_stream_runtime *rt); + int (*disable_stream)(struct slim_stream_runtime *rt); + int (*prepare_msg)(struct slim_controller *ctrl, + struct slim_msg_txn *tx, + struct completion *done); int (*wakeup)(struct slim_controller *ctrl); }; @@ -240,6 +358,10 @@ int slim_unregister_controller(struct slim_controller *ctrl); void slim_msg_response(struct slim_controller *ctrl, u8 *reply, u8 tid, u8 l); int slim_do_transfer(struct slim_controller *ctrl, struct slim_msg_txn *txn); int slim_ctrl_clk_pause(struct slim_controller *ctrl, bool wakeup, u8 restart); +int slim_prepare_txn(struct slim_controller *ctrl, struct slim_msg_txn *txn, + struct completion *done, bool need_tid); +int slim_alloc_tid(struct slim_controller *ctrl, struct slim_msg_txn *txn); +int slim_find_prrate(int rate); static inline bool slim_tid_txn(u8 mt, u8 mc) { @@ -258,4 +380,6 @@ static inline bool slim_ec_txn(u8 mt, u8 mc) (mc >= SLIM_MSG_MC_REQUEST_VALUE && mc <= SLIM_MSG_MC_CHANGE_VALUE))); } + +extern char * get_mc_name(int mc); #endif /* _LINUX_SLIMBUS_H */ diff --git a/drivers/slimbus/stream.c b/drivers/slimbus/stream.c new file mode 100644 index 000000000000..5e045fe2d6ed --- /dev/null +++ b/drivers/slimbus/stream.c @@ -0,0 +1,357 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, Linaro Limited +// TODO: +// Add support to natural frequencies like 11.025KHz and 44.1KHz. +// Add support to PUSH/PULL transport protocol +// Bandwidth Management +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/slab.h> +#include <linux/init.h> +#include <linux/idr.h> +#include <linux/of.h> +#include <linux/slimbus.h> +#include "slimbus.h" + +struct slim_stream_runtime *slim_stream_allocate(struct slim_device *dev, + struct slim_stream_config *cfg) +{ + struct slim_stream_runtime *rt; + struct slim_controller *ctrl = dev->ctrl; + int num_ports, i, port_id; + + num_ports = hweight32(cfg->port_mask); + rt = kzalloc(sizeof(*rt) + num_ports * sizeof(*rt->ports), GFP_KERNEL); + if (!rt) + return ERR_PTR(-ENOMEM); + + rt->dev = dev; + rt->num_ports = num_ports; + rt->rate = cfg->rate; + rt->prot = cfg->prot; + rt->bps = cfg->bps; + rt->direction = cfg->direction; + + i = 0; + //FIXME ONLY Natural frequencies of 8KHz to 48KHz are supported!! + rt->ratem = cfg->rate/ctrl->a_framer->superfreq; + + for_each_set_bit(port_id, &cfg->port_mask, SLIM_MAX_PORTS) { + rt->ports[i].state = SLIM_PORT_DISCONNECTED; + rt->ports[i].id = port_id; + rt->ports[i].direction = SLIM_PORT_SINK; + rt->ports[i].ch.id = cfg->chs[i]; + rt->ports[i].ch.state = SLIM_CH_ALLOCATED; + + i++; + } + + return rt; +} +EXPORT_SYMBOL_GPL(slim_stream_allocate); + +static int slim_connect_sink(struct slim_stream_runtime *stream, + struct slim_port *port) +{ + struct slim_device *sdev = stream->dev; + struct slim_val_inf msg = {0, 0, NULL, NULL}; + struct slim_msg_txn txn = {0,}; + u8 wbuf[2]; + + txn.dt = SLIM_MSG_DEST_LOGICALADDR; + txn.la = stream->dev->laddr; + txn.ec = 0; + txn.mc = SLIM_MSG_MC_CONNECT_SINK; + txn.rl = 6; + txn.msg = &msg; + txn.msg->num_bytes = 2; + txn.msg->wbuf = wbuf; + + wbuf[0] = port->id; + wbuf[1] = port->ch.id; + + return slim_do_transfer(sdev->ctrl, &txn); +} + +static int slim_connect_source(struct slim_stream_runtime *stream, + struct slim_port *port) +{ + struct slim_device *sdev = stream->dev; + struct slim_val_inf msg = {0, 0, NULL, NULL}; + struct slim_msg_txn txn = {0,}; + u8 wbuf[2]; + + txn.dt = SLIM_MSG_DEST_LOGICALADDR; + txn.la = stream->dev->laddr; + txn.ec = 0; + txn.mc = SLIM_MSG_MC_CONNECT_SOURCE; + txn.rl = 6; + txn.msg = &msg; + txn.msg->num_bytes = 2; + txn.msg->wbuf = wbuf; + + wbuf[0] = port->id; + wbuf[1] = port->ch.id; + + return slim_do_transfer(sdev->ctrl, &txn); +} + +static int slim_disconnect_port(struct slim_stream_runtime *stream, + struct slim_port *port) +{ + struct slim_device *sdev = stream->dev; + struct slim_val_inf msg = {0, 0, NULL, NULL}; + struct slim_msg_txn txn = {0,}; + u8 wbuf[1]; + + txn.dt = SLIM_MSG_DEST_LOGICALADDR; + txn.la = stream->dev->laddr; + txn.ec = 0; + txn.mc = SLIM_MSG_MC_DISCONNECT_PORT; + txn.rl = 5; + txn.msg = &msg; + txn.msg->num_bytes = 1; + txn.msg->wbuf = wbuf; + wbuf[0] = port->id; + return slim_do_transfer(sdev->ctrl, &txn); +} + +int slim_stream_prepare(struct slim_stream_runtime *stream) +{ + int i; + + for (i = 0; i < stream->num_ports; i++) { + if (stream->direction == SLIM_STREAM_PLAYBACK) + slim_connect_sink(stream, &stream->ports[i]); + else if (stream->direction == SLIM_STREAM_CAPTURE) + slim_connect_source(stream, &stream->ports[i]); + else + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL_GPL(slim_stream_prepare); + +/* + * Presense Rate + * Table 66 from SLIMbus 2.0 Specs + */ +static int prrate_table[] = +{ + 12000, 0x01, + 24000, 0x02, + 48000, 0x03, + 96000, 0x04, + 192000, 0x05, + 384000, 0x06, + 768000, 0x07, + 110250, 0x09, + 220500, 0x0a, + 441000, 0x0b, + 882000, 0x0c, + 176400, 0x0d, + 352800, 0x0e, + 705600, 0x0f, + 4000, 0x10, + 8000, 0x11, + 16000, 0x12, + 32000, 0x13, + 64000, 0x14, + 128000, 0x15, + 256000, 0x16, + 512000, 0x17, +}; + +int slim_find_prrate(int rate) +{ + int i; + for (i = 0; i < ARRAY_SIZE(prrate_table);) { + if (rate == prrate_table[i]) + return prrate_table[i+1]; + i += 2; + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(slim_find_prrate); + +static int slim_define_channel_content(struct slim_stream_runtime *stream, + struct slim_port *port) +{ + struct slim_device *sdev = stream->dev; + struct slim_val_inf msg = {0, 0, NULL, NULL}; + struct slim_msg_txn txn = {0,}; + u8 wbuf[4]; + int prrate; + int fl = 1; /* Frequency Locked for ISO Protocol */ + prrate = slim_find_prrate(stream->rate); + + port->ch.prrate = prrate; + + txn.dt = SLIM_MSG_DEST_LOGICALADDR; + txn.la = stream->dev->laddr; + txn.ec = 0; + txn.mc = SLIM_MSG_MC_NEXT_DEFINE_CONTENT; + txn.rl = 8; + txn.msg = &msg; + txn.msg->num_bytes = 4; + txn.msg->wbuf = wbuf; + wbuf[0] = port->ch.id; + wbuf[1] = prrate | (fl << 7); + wbuf[2] = 0; + // FIXME.. slc->prop.dataf | (slc->prop.auxf << 4); + wbuf[3] = stream->bps/SLIM_SLOT_LEN_BITS; + + return slim_do_transfer(sdev->ctrl, &txn); +} + +struct segdist_code { + /* Channel rate multiplier */ + int ratem; + int segdist_code; + u32 seg_offset_mask; + +}; + +/* Table 20 from SLIMbus Specs Version 2.0 */ +static struct segdist_code segdist_codes[] = { + {1, 0x200, 0xdff}, + {2, 0x100, 0xcff}, + {4, 0x080, 0xc7f}, + {8, 0x040, 0xc3f}, + {16, 0x020, 0xc1f}, + {32, 0x010, 0xc0f}, + {64, 0x008, 0xc07}, + {128, 0x004, 0xc03}, + {256, 0x002, 0xc01}, + {512, 0x001, 0xc00}, + {3, 0xe00, 0x1ff}, + {6, 0xd00, 0x0ff}, + {12, 0xc80, 0x07f}, + {24, 0xc40, 0x03f}, + {48, 0xc20, 0x01f}, + {96, 0xc10, 0x00f}, + {192, 0xc08, 0x007}, + {364, 0xc04, 0x003}, + {768, 0xc02, 0x001}, +}; + +static int slim_get_segdist_code(int ratem) +{ + int i; + for (i = 0; i < ARRAY_SIZE(segdist_codes); i++) { + if (segdist_codes[i].ratem == ratem) + return segdist_codes[i].segdist_code; + } + + return -EINVAL; +} + +static int slim_define_channel(struct slim_stream_runtime *stream, + struct slim_port *port) +{ + struct slim_device *sdev = stream->dev; + struct slim_val_inf msg = {0, 0, NULL, NULL}; + struct slim_msg_txn txn = {0,}; + u8 wbuf[4]; + int sd; + int tp = 0; + + txn.dt = SLIM_MSG_DEST_BROADCAST; + txn.la = stream->dev->laddr; + txn.ec = 0; + txn.mc = SLIM_MSG_MC_NEXT_DEFINE_CHANNEL; + txn.rl = 8; + txn.msg = &msg; + txn.msg->num_bytes = 4; + txn.msg->wbuf = wbuf; + sd = slim_get_segdist_code(stream->ratem); + wbuf[0] = port->ch.id; + + port->ch.seg_dist = sd; + wbuf[1] = sd & 0xFF; + /* Only Isochronous Protocol supported */ + wbuf[2] = tp | ((sd & 0xF00) >> 8); + + /* Only one data line is supported */ + wbuf[3] = stream->bps/SLIM_SLOT_LEN_BITS; + + + return slim_do_transfer(sdev->ctrl, &txn); +} + +static int slim_activate_channel(struct slim_stream_runtime *stream, + struct slim_port *port) +{ + struct slim_device *sdev = stream->dev; + struct slim_val_inf msg = {0, 0, NULL, NULL}; + struct slim_msg_txn txn = {0,}; + u8 wbuf[1]; + + txn.dt = SLIM_MSG_DEST_BROADCAST; + txn.la = stream->dev->laddr; + txn.ec = 0; + txn.mc = SLIM_MSG_MC_NEXT_ACTIVATE_CHANNEL; + txn.rl = 5; + txn.msg = &msg; + txn.msg->num_bytes = 1; + txn.msg->wbuf = wbuf; + wbuf[0] = port->ch.id; + + return slim_do_transfer(sdev->ctrl, &txn); +} + +int slim_stream_enable(struct slim_stream_runtime *stream) +{ + DEFINE_SLIM_BCAST_TXN(txn, SLIM_MSG_MC_BEGIN_RECONFIGURATION, + 3, SLIM_LA_MANAGER, NULL); + struct slim_controller *ctrl = stream->dev->ctrl; + int ret, i; + + if (ctrl->enable_stream) + return ctrl->enable_stream(stream); + + ret = slim_do_transfer(ctrl, &txn); + if (ret) + return ret; + + for (i = 0; i < stream->num_ports; i++) { + struct slim_port *port = &stream->ports[i]; + slim_define_channel(stream, port); + slim_define_channel_content(stream, port); + } + + for (i = 0; i < stream->num_ports; i++) { + struct slim_port *port = &stream->ports[i]; + slim_activate_channel(stream, port); + } + txn.mc = SLIM_MSG_MC_RECONFIGURE_NOW; + txn.rl = 3; + + return slim_do_transfer(ctrl, &txn); +} +EXPORT_SYMBOL_GPL(slim_stream_enable); + +int slim_stream_disable(struct slim_stream_runtime *stream) +{ + return 0; +} +EXPORT_SYMBOL_GPL(slim_stream_disable); + +int slim_stream_unprepare(struct slim_stream_runtime *stream) +{ + int i; + for (i = 0; i < stream->num_ports; i++) + slim_disconnect_port(stream, &stream->ports[i]); + + return 0; +} +EXPORT_SYMBOL_GPL(slim_stream_unprepare); + +int slim_stream_free(struct slim_stream_runtime *stream) +{ + kfree(stream); + return 0; +} +EXPORT_SYMBOL_GPL(slim_stream_free); diff --git a/include/linux/slimbus.h b/include/linux/slimbus.h index c36cf121d2cd..419a9a983bc4 100644 --- a/include/linux/slimbus.h +++ b/include/linux/slimbus.h @@ -14,16 +14,16 @@ extern struct bus_type slimbus_bus; /** * struct slim_eaddr - Enumeration address for a SLIMbus device - * @manf_id: Manufacturer Id for the device - * @prod_code: Product code - * @dev_index: Device index * @instance: Instance value + * @dev_index: Device index + * @prod_code: Product code + * @manf_id: Manufacturer Id for the device */ struct slim_eaddr { - u16 manf_id; - u16 prod_code; - u8 dev_index; u8 instance; + u8 dev_index; + u16 prod_code; + u16 manf_id; } __packed; /** @@ -108,6 +108,53 @@ struct slim_val_inf { struct completion *comp; }; +enum slim_stream_direction { + SLIM_STREAM_PLAYBACK = 0, + SLIM_STREAM_CAPTURE, +}; + +//FIXME ONLY ISO supported +enum slim_channel_proto { + SLIM_HARD_ISO = 0, + SLIM_AUTO_ISO, + SLIM_PUSH, + SLIM_PULL, + SLIM_ASYNC_SMPLX, + SLIM_ASYNC_HALF_DUP, + SLIM_EXT_SMPLX, + SLIM_EXT_HALF_DUP, +}; + +/* + * 1:1 map between port and channel + * + * only ISO protocol is supported. + * + */ +struct slim_stream_config { + unsigned int rate; + unsigned int bps; + + /* MAX 256 channels */ + unsigned int ch_count; + unsigned int *chs; + /* Max 32 ports per device */ + unsigned long port_mask; + + enum slim_stream_direction direction; + enum slim_channel_proto prot; +}; + +struct slim_stream_runtime; + +struct slim_stream_runtime *slim_stream_allocate(struct slim_device *dev, + struct slim_stream_config *c); +int slim_stream_prepare(struct slim_stream_runtime *stream); +int slim_stream_enable(struct slim_stream_runtime *stream); +int slim_stream_disable(struct slim_stream_runtime *stream); +int slim_stream_unprepare(struct slim_stream_runtime *stream); +int slim_stream_free(struct slim_stream_runtime *stream); + /* * use a macro to avoid include chaining to get THIS_MODULE */ @@ -138,6 +185,8 @@ static inline void slim_set_devicedata(struct slim_device *dev, void *data) dev_set_drvdata(&dev->dev, data); } +struct slim_device *of_slim_get_device(struct slim_controller *ctrl, + struct device_node *np); struct slim_device *slim_get_device(struct slim_controller *ctrl, struct slim_eaddr *e_addr); int slim_get_logical_addr(struct slim_device *sbdev); |