diff options
| author | Robert Chiras <robert.chiras@nxp.com> | 2018-11-28 15:09:56 +0200 |
|---|---|---|
| committer | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2019-01-25 16:14:20 +0000 |
| commit | b203d7ce2e00e3da573e2b75d7a6e418d4b4e2ef (patch) | |
| tree | 3d7ee23acd1e2e4a82ab450ca29a65e30516f563 | |
| parent | bde95eed383f9791334a01c81af67977cec70103 (diff) | |
Revert "MA-12957: arm64: dts: imx8qm/qxp mek: Correct interrupts for adv7535"
This commit is breaking suspend/resume, so reverting it until a fix is
provided.
This reverts commit 4a004884a4f16d698941a39fd0ec5f29bedb10ed.
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi | 4 | ||||
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi index c90507106771..ccb946070ca2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi @@ -593,7 +593,7 @@ fsl,pins = < SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc600004c SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc600004c - SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 0x00000020 + SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 0x00000020 >; }; @@ -601,7 +601,7 @@ fsl,pins = < SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c - SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 0x00000020 + SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 0x00000020 >; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi index a3ec242c4df3..772bd7105338 100755 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi @@ -456,7 +456,7 @@ fsl,pins = < SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 - SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 0x00000020 + SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 0x00000020 >; }; @@ -470,7 +470,7 @@ fsl,pins = < SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 - SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 0x00000020 + SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 0x00000020 >; }; |