diff options
| author | Robert Chiras <robert.chiras@nxp.com> | 2018-11-26 13:17:14 +0200 |
|---|---|---|
| committer | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2019-01-25 16:14:17 +0000 |
| commit | 7097749d12b137970bdb05ec03a0b5e34b309489 (patch) | |
| tree | 347ec0d6b488025940d2c5f8a9f16c84127e3d91 | |
| parent | 26a1baa46df857d83690398bc8ef6d9042e187d5 (diff) | |
MA-12957: arm64: dts: imx8qm/qxp mek: Correct interrupts for adv7535
This patch fixes the interrupts used by ADV7535. Initial patch
configured the GPIO0 IO00 as IO pin for the DSI_INT, used by ADV7535,
but the correct one is IO01, since IO00 is used by PWM.
Fixes: c2f1eceb5629 ("arm64: dts: imx8qm/qxp mek: Configure interrupts
for adv7535")
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi | 4 | ||||
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi index d5f1472f39fd..a28078336c56 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi @@ -591,7 +591,7 @@ fsl,pins = < SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc600004c SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc600004c - SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 0x00000020 + SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 0x00000020 >; }; @@ -599,7 +599,7 @@ fsl,pins = < SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c - SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 0x00000020 + SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 0x00000020 >; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi index bcd79ae5b411..d89109a2fe0d 100755 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi @@ -456,7 +456,7 @@ fsl,pins = < SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 - SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 0x00000020 + SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 0x00000020 >; }; @@ -470,7 +470,7 @@ fsl,pins = < SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 - SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 0x00000020 + SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 0x00000020 >; }; |