diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2018-11-27 16:25:16 +0800 |
|---|---|---|
| committer | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2019-01-25 16:14:19 +0000 |
| commit | 0cddc7422bf682050ff5ee7d8f62c82e25fdf327 (patch) | |
| tree | 15fd24f53d59f57131a1e402d747a0e7cc7c4194 | |
| parent | 7b6b2734fbe49ee4a9f06d368567859749d49895 (diff) | |
MLK-20472 arm64: dts: correct the pad configurations of pcie
Correct the pad confirations of the pcie perst and epdev_on
on 8qm/qxp platforms.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit 28d5b68c1fa7568a2444915b71fab12e8a2d4350)
5 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi index d0bedaa631ee..e28a0e73c9ed 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi @@ -527,7 +527,7 @@ fsl,pins = < SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x04000021 SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 - SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x04000021 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 >; }; @@ -535,7 +535,7 @@ fsl,pins = < SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x04000021 SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 - SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x04000021 + SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 >; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts index 0a17c36155b3..b5b8b3b5ea95 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts @@ -777,9 +777,9 @@ fsl,pins = < SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x04000021 SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 - SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x04000021 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 - SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x04000021 + SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 >; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts index 7e79aa839462..4fe6a555b7a4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts @@ -931,9 +931,9 @@ fsl,pins = < SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x04000021 SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 - SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x04000021 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 - SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x04000021 + SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 >; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi index d89109a2fe0d..f0843359ecce 100755 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi @@ -598,7 +598,7 @@ pinctrl_pcieb: pcieagrp{ fsl,pins = < - SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x04000021 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000021 SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 >; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi index 52c41793464c..363f7e880fc3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi @@ -456,7 +456,7 @@ pinctrl_pcieb: pciebgrp{ fsl,pins = < - SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x04000021 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000021 SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 >; |