diff options
| author | Bintian Wang <bintian.wang@huawei.com> | 2015-01-07 22:38:25 +0800 |
|---|---|---|
| committer | Fei Wang <w.f@huawei.com> | 2015-02-06 12:57:36 +0800 |
| commit | 6558d1078776ede805f6301c043be67d42df523c (patch) | |
| tree | 1034cb34771323f8f8d4d0b80ac3966ead2c718f /arch/arm64 | |
| parent | 19d62bb2409a0a969ed07127ff8dd1e894ecf3e6 (diff) | |
dts: hi6220: Add device nodes for UART1/2
Add UART1/2 device nodes to Hisilicon hi6220 SoC dts file.
Signed-off-by: Bintian Wang <bintian.wang@huawei.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/hi6220-hikey.dts | 51 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/hi6220.dtsi | 51 |
2 files changed, 101 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/hi6220-hikey.dts b/arch/arm64/boot/dts/hi6220-hikey.dts index 8876bb6bd541..30a311362454 100644 --- a/arch/arm64/boot/dts/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hi6220-hikey.dts @@ -10,6 +10,7 @@ /memreserve/ 0x00000000 0x07400000; /memreserve/ 0x0740f000 0x1000; +#include "hikey-pinctrl.dtsi" #include "hi6220.dtsi" / { @@ -22,6 +23,8 @@ aliases { serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; }; chosen { @@ -33,4 +36,52 @@ device_type = "memory"; reg = <0x0 0x00000000 0x0 0x40000000>; }; + + smb { + uart0: uart@f8015000 { /* console */ + status = "ok"; + }; + + uart1: uart@f7111000 { + pinctrl-names = "default", "idle"; + pinctrl-0 = <&UART1_CTS_N_pmx_func + &UART1_CTS_N_cfg_func + &UART1_RTS_N_pmx_func + &UART1_RTS_N_cfg_func + &UART1_RXD_pmx_func + &UART1_RXD_cfg_func + &UART1_TXD_pmx_func + &UART1_TXD_cfg_func>; + pinctrl-1 = <&UART1_CTS_N_pmx_idle + &UART1_CTS_N_cfg_idle + &UART1_RTS_N_pmx_idle + &UART1_RTS_N_cfg_idle + &UART1_RXD_pmx_idle + &UART1_RXD_cfg_idle + &UART1_TXD_pmx_idle + &UART1_TXD_cfg_idle>; + status = "ok"; + }; + + uart2: uart@f7112000 { + pinctrl-names = "default", "idle"; + pinctrl-0 = <&UART2_CTS_N_pmx_func + &UART2_CTS_N_cfg_func + &UART2_RTS_N_pmx_func + &UART2_RTS_N_cfg_func + &UART2_RXD_pmx_func + &UART2_RXD_cfg_func + &UART2_TXD_pmx_func + &UART2_TXD_cfg_func>; + pinctrl-1 = <&UART2_CTS_N_pmx_idle + &UART2_CTS_N_cfg_idle + &UART2_RTS_N_pmx_idle + &UART2_RTS_N_cfg_idle + &UART2_RXD_pmx_idle + &UART2_RXD_cfg_idle + &UART2_TXD_pmx_idle + &UART2_TXD_cfg_idle>; + status = "ok"; + }; + }; }; diff --git a/arch/arm64/boot/dts/hi6220.dtsi b/arch/arm64/boot/dts/hi6220.dtsi index a3052f1f7763..576264d3c14b 100644 --- a/arch/arm64/boot/dts/hi6220.dtsi +++ b/arch/arm64/boot/dts/hi6220.dtsi @@ -214,7 +214,56 @@ interrupts = <0 36 4>; clocks = <&clock_ao HI6220_UART0_PCLK>; clock-names = "apb_pclk"; - status = "ok"; + status = "disabled"; + }; + + uart1: uart@f7111000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xf7111000 0x0 0x1000>; + interrupts = <0 37 4>; + reset-controller-reg = <0x330 0x334 0x338 5>; + clock-freq-high = <1>; + clocks = <&clock_sys HI6220_UART1_PCLK>; + clock-names = "apb_pclk"; + clk-enable-flag = <0>; + fifo-deep-size = <64>; + status = "disabled"; + }; + + uart2: uart@f7112000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xf7112000 0x0 0x1000>; + interrupts = <0 38 4>; + reset-controller-reg = <0x330 0x334 0x338 6>; + clocks = <&clock_sys HI6220_UART2_PCLK>; + clock-names = "apb_pclk"; + clk-enable-flag = <0>; + fifo-deep-size = <64>; + status = "disabled"; + }; + + uart3: uart@f7113000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xf7113000 0x0 0x1000>; + interrupts = <0 39 4>; + reset-controller-reg = <0x330 0x334 0x338 7>; + clocks = <&clock_sys HI6220_UART3_PCLK>; + clock-names = "apb_pclk"; + clk-enable-flag = <0>; + fifo-deep-size = <16>; + status = "disabled"; + }; + + uart4: uart@f7114000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xf7114000 0x0 0x1000>; + interrupts = <0 40 4>; + reset-controller-reg = <0x330 0x334 0x338 8>; + clocks = <&clock_sys HI6220_UART4_PCLK>; + clock-names = "apb_pclk"; + clk-enable-flag = <0>; + fifo-deep-size = <16>; + status = "disabled"; }; dma0: dma@F7370000 { |