diff options
| author | xuejiancheng <xuejiancheng@huawei.com> | 2014-05-27 15:25:11 +0800 |
|---|---|---|
| committer | Zhangfei Gao <zhangfei.gao@linaro.org> | 2014-10-30 13:30:55 +0800 |
| commit | 5d21236d666361929256a890cf7d9c535b394d20 (patch) | |
| tree | 7f1adf30347b7508bccdece3340fae241898000c | |
| parent | a870a4aff466f795f02f9c109cb06f5ba8f4db38 (diff) | |
arm:dts: hix5hd2 add ahci sata-phy and syscon node
hix5hd2 add ahci,sata-phy and syscon node
Signed-off-by: xuejiancheng <xuejiancheng@huawei.com>
| -rw-r--r-- | arch/arm/boot/dts/hix5hd2-dkb.dts | 17 | ||||
| -rw-r--r-- | arch/arm/boot/dts/hix5hd2.dtsi | 12 |
2 files changed, 28 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/hix5hd2-dkb.dts b/arch/arm/boot/dts/hix5hd2-dkb.dts index e02688c1d56c..af133f385355 100644 --- a/arch/arm/boot/dts/hix5hd2-dkb.dts +++ b/arch/arm/boot/dts/hix5hd2-dkb.dts @@ -75,6 +75,21 @@ phy1: ethernet-phy@1 { reg = <1>; }; - }; + }; + + ahci:sata@f9900000 { + phys = <&sata_phy>; + phy-names = "sata-phy"; + }; + + sata_phy:phy@f9900000 { + compatible = "hisilicon,hix5hd2-sata-phy"; + reg = <0xf9900000 0x10000>; + hisilicon,syscon = <&peri_ctrl>; + hisilicon,power-reg = <0x8 10>; + hisilicon,reg-init = <0x148 0 32 0x345cb8>,<0x14c 0 32 0x20545>; + #phy-cells = <0>; + }; + }; }; diff --git a/arch/arm/boot/dts/hix5hd2.dtsi b/arch/arm/boot/dts/hix5hd2.dtsi index 4b3c880077bf..0d66633464dd 100644 --- a/arch/arm/boot/dts/hix5hd2.dtsi +++ b/arch/arm/boot/dts/hix5hd2.dtsi @@ -188,6 +188,13 @@ clocks = <&clock HIX5HD2_USB_CLK>; }; + ahci:sata@f9900000 { + compatible = "hisilicon,hix5hd2-ahci"; + reg = <0xf9900000 0x10000>; + interrupts = <0 70 4>; + clocks = <&clock HIX5HD2_SATA_CLK>; + }; + sctrl@f8000000 { compatible = "hisilicon,sctrl"; reg = <0xf8000000 0x1000>; @@ -195,6 +202,11 @@ reboot_reg = <0x4>; }; + peri_ctrl:syscon@f8a20000 { + compatible = "syscon"; + reg = <0xf8a20000 0x1000>; + }; + clkbase@f8a22000 { compatible = "hisilicon,clkbase"; #address-cells = <1>; |