diff options
author | Sarah Walker <Sarah.Walker@arm.com> | 2016-01-13 16:24:22 +0000 |
---|---|---|
committer | Ryan Harkin <ryan.harkin@linaro.org> | 2016-03-10 07:58:05 +0000 |
commit | 14ebf51be6ead99b3861d779bdcf3cee18ab81d6 (patch) | |
tree | ec08b24cd2881121f9d3b684cb3aa3ee6534e0b2 | |
parent | 7bc2949ccefe0eba6a009ffe91a2117a8f1f4da6 (diff) |
arm64: dts: add device tree for GPU+VP+DP Juno platform
This commit adds a new DTS for the GPU+VP+DP
Juno platform. In order to reduce duplication
between this and the basic Juno platform, the
common areas have been split into
'juno-common.dtsi'.
Change-Id: Ice7bc9ee649332f3031181d6728d91043b6f8e3d
-rw-r--r-- | arch/arm64/boot/dts/Makefile | 3 | ||||
-rw-r--r-- | arch/arm64/boot/dts/juno-common.dtsi | 704 | ||||
-rw-r--r-- | arch/arm64/boot/dts/juno.dts | 695 | ||||
-rw-r--r-- | arch/arm64/boot/dts/juno_mali_fpga_T860_VP550_DP550_SMMU550.dts | 70 |
4 files changed, 777 insertions, 695 deletions
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 661015fd774..06db106890d 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -1,6 +1,7 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb \ fvp-base-gicv2-psci.dtb -dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb \ + juno_mali_fpga_T860_VP550_DP550_SMMU550.dtb dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb targets += dtbs diff --git a/arch/arm64/boot/dts/juno-common.dtsi b/arch/arm64/boot/dts/juno-common.dtsi new file mode 100644 index 00000000000..2da6ec56c89 --- /dev/null +++ b/arch/arm64/boot/dts/juno-common.dtsi @@ -0,0 +1,704 @@ +/* + * ARM Ltd. Juno Plaform + * + * Fast Models FVP v2 support + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + model = "Juno"; + compatible = "arm,juno", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &soc_uart0; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster1: cluster1 { + #cooling-cells = <2>; /* min followed by max */ + + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster0: cluster0 { + #cooling-cells = <2>; /* min followed by max */ + + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + entry-method-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + entry-method-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + CPU0:cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + clocks = <&scpi_dvfs 1>; + clock-names = "vlittle"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU1:cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + clocks = <&scpi_dvfs 1>; + clock-names = "vlittle"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU2:cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; + clocks = <&scpi_dvfs 1>; + clock-names = "vlittle"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU3:cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; + clocks = <&scpi_dvfs 1>; + clock-names = "vlittle"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU4:cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + clocks = <&scpi_dvfs 0>; + clock-names = "vbig"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU5:cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + clocks = <&scpi_dvfs 0>; + clock-names = "vbig"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x0 0x7f000000>, + <0x00000008 0x80000000 0x1 0x80000000>; + }; + + /* memory@14000000 { + device_type = "memory"; + reg = <0x00000000 0x14000000 0x0 0x02000000>; + }; */ + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x2c010000 0 0x1000>, + <0x0 0x2c02f000 0 0x2000>, + <0x0 0x2c04f000 0 0x2000>, + <0x0 0x2c06f000 0 0x2000>; + interrupts = <GIC_PPI 9 0xf04>; + }; + + msi0: msi@2c1c0000 { + compatible = "arm,gic-msi"; + reg = <0x0 0x2c1c0000 0 0x10000 + 0x0 0x2c1d0000 0 0x10000 + 0x0 0x2c1e0000 0 0x10000 + 0x0 0x2c1f0000 0 0x10000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 0xff01>, + <GIC_PPI 14 0xff01>, + <GIC_PPI 11 0xff01>, + <GIC_PPI 10 0xff01>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <1>; + interrupts = <0 60 4>; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 18 4>, + <GIC_SPI 22 4>, + <GIC_SPI 26 4>, + <GIC_SPI 30 4>, + <GIC_SPI 02 4>, + <GIC_SPI 06 4>; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0xC4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xC4000003>; + migrate = <0xC4000005>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + pci0: pci@30000000 { + compatible = "arm,pcie-xr3"; + device_type = "pci"; + reg = <0 0x7ff30000 0 0x1000 + 0 0x7ff20000 0 0x10000 + 0 0x40000000 0 0x10000000>; + bus-range = <0 255>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x00 0x5ff00000 0x0 0x00100000 + 0x02000000 0x0 0x00000000 0x40 0x00000000 0x0 0x80000000 + 0x42000000 0x0 0x80000000 0x40 0x80000000 0x0 0x80000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic 0 136 4 + 0 0 0 2 &gic 0 137 4 + 0 0 0 3 &gic 0 138 4 + 0 0 0 4 &gic 0 139 4>; + }; + + + mailbox: mhu@2b1f0000 { + compatible = "arm,mhu"; + reg = <0x0 0x2b1f0000 0x0 0x10000>, /* MHU registers */ + <0x0 0x2e000000 0x0 0x10000>; /* Payload area */ + interrupts = <0 36 4>, /* low priority interrupt */ + <0 35 4>; /* high priority interrupt */ + #mbox-cells = <1>; + mbox-names = "cpu_to_scp_low", "cpu_to_scp_high"; + mboxes = <&mailbox 0 &mailbox 1>; + }; + + clocks { + compatible = "arm,scpi-clks"; + + scpi_dvfs: scpi_clocks@0 { + compatible = "arm,scpi-clk-indexed"; + #clock-cells = <1>; + clock-indices = <0>, <1>, <2>; + clock-output-names = "vbig", "vlittle", "vgpu"; + }; + + scpi_clk: scpi_clocks@3 { + compatible = "arm,scpi-clk-range"; + #clock-cells = <1>; + clock-indices = <3>, <4>; + frequency-range = <23750000 165000000>; + clock-output-names = "pxlclk0", "pxlclk1"; + }; + + }; + + hwmon@1c010000 { + compatible = "arm,v2m-juno-meters"; + reg = <0x0 0x1c010000 0x0 0x1000>; + }; + + cpufreq { + compatible = "arm,scpi-cpufreq"; + }; + + scpi_sensor0: scpi-sensor@0 { + compatible = "arm,scpi-thermal"; + #thermal-sensor-cells = <1>; + }; + + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2500>; + + thermal-sensors = <&scpi_sensor0 3>; + + trips { + threshold: trip-point@0 { + temperature = <55000>; + hysteresis = <1000>; + type = "passive"; + }; + target: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cluster0 0 5>; + }; + map1 { + trip = <&target>; + cooling-device = <&cluster1 0 5>; + }; + map2 { + trip = <&target>; + cooling-device = <&gpu 0 4>; + }; + }; + }; + }; + + soc_uartclk: refclk72738khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <7273800>; + clock-output-names = "juno:uartclk"; + }; + + soc_refclk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "juno:clk24mhz"; + }; + + mb_eth25mhz: clk25mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "ethclk25mhz"; + }; + + soc_usb48mhz: clk48mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "clk48mhz"; + }; + + soc_smc50mhz: clk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "smc_clk"; + }; + + soc_refclk100mhz: refclk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "apb_pclk"; + }; + + soc_faxiclk: refclk533mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <533000000>; + clock-output-names = "faxi_clk"; + }; + + soc_fixed_3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + memory-controller@7ffd0000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0 0x7ffd0000 0 0x1000>; + interrupts = <0 86 4>, + <0 87 4>; + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + chip5-memwidth = <16>; + }; + + dma0: dma@0x7ff00000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x7ff00000 0 0x1000>; + interrupts = <0 95 4>, + <0 88 4>, + <0 89 4>, + <0 90 4>, + <0 91 4>, + <0 108 4>, + <0 109 4>, + <0 110 4>, + <0 111 4>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&soc_faxiclk>; + clock-names = "apb_pclk"; + }; + + soc_uart0: uart@7ff80000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x7ff80000 0x0 0x1000>; + interrupts = <0 83 4>; + clocks = <&soc_uartclk>, <&soc_refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + dmas = <&dma0 1 + &dma0 2>; + dma-names = "rx", "tx"; + }; + + /* this UART is reserved for secure software. + soc_uart1: uart@7ff70000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x7ff70000 0x0 0x1000>; + interrupts = <0 84 4>; + clocks = <&soc_uartclk>, <&soc_refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; */ + + ulpi_phy: phy@0 { + compatible = "phy-ulpi-generic"; + reg = <0x0 0x94 0x0 0x4>; + phy-id = <0>; + }; + + ehci@7ffc0000 { + compatible = "snps,ehci-h20ahb"; + /* compatible = "arm,h20ahb-ehci"; */ + reg = <0x0 0x7ffc0000 0x0 0x10000>; + interrupts = <0 117 4>; + clocks = <&soc_usb48mhz>; + clock-names = "otg"; + phys = <&ulpi_phy>; + }; + + ohci@0x7ffb0000 { + compatible = "generic-ohci"; + reg = <0x0 0x7ffb0000 0x0 0x10000>; + interrupts = <0 116 4>; + clocks = <&soc_usb48mhz>; + clock-names = "otg"; + }; + + i2c@0x7ffa0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x0 0x7ffa0000 0x0 0x1000>; + interrupts = <0 104 4>; + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <500>; + clocks = <&soc_smc50mhz>; + + dvi0: dvi-transmitter@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + }; + + dvi1: dvi-transmitter@71 { + compatible = "nxp,tda998x"; + reg = <0x71>; + }; + }; + + i2c@0x6f190000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,versatile-i2c"; + reg = <0x0 0x6f190000 0x0 0x1000>; + + dvi2: dvi-transmitter@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + video-ports = <0x234501>; + }; + + dvi3: dvi-transmitter@71 { + compatible = "nxp,tda998x"; + reg = <0x71>; + video-ports = <0x234501>; + }; + }; + + /* mmci@1c050000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x0 0x1c050000 0x0 0x1000>; + interrupts = <0 73 4>, + <0 74 4>; + max-frequency = <12000000>; + vmmc-supply = <&soc_fixed_3v3>; + clocks = <&soc_refclk24mhz>, <&soc_refclk100mhz>; + clock-names = "mclk", "apb_pclk"; + }; */ + + hdlcd@7ff60000 { + compatible = "arm,hdlcd"; + reg = <0 0x7ff60000 0 0x1000>; + interrupts = <0 85 4>; + clocks = <&scpi_clk 0>; + clock-names = "pxlclk"; + i2c-slave = <&dvi0>; + + /* display-timings { + native-mode = <&timing0>; + timing0: timing@0 { + /* 1024 x 768 framebufer, standard VGA timings * / + clock-frequency = <65000>; + hactive = <1024>; + vactive = <768>; + hfront-porch = <24>; + hback-porch = <160>; + hsync-len = <136>; + vfront-porch = <3>; + vback-porch = <29>; + vsync-len = <6>; + }; + }; */ + }; + + /* hdlcd@7ff50000 { + compatible = "arm,hdlcd"; + reg = <0 0x7ff50000 0 0x1000>; + interrupts = <0 93 4>; + clocks = <&scpi_clk 1>; + clock-names = "pxlclk"; + i2c-slave = <&dvi1>; + + display-timings { + native-mode = <&timing1>; + timing1: timing@1 { + /* 1024 x 768 framebufer, standard VGA timings * / + clock-frequency = <65000>; + hactive = <1024>; + vactive = <768>; + hfront-porch = <24>; + hback-porch = <160>; + hsync-len = <136>; + vfront-porch = <3>; + vback-porch = <29>; + vsync-len = <6>; + }; + }; + }; */ + + smb { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 15>; + interrupt-map = <0 0 0 &gic 0 68 4>, + <0 0 1 &gic 0 69 4>, + <0 0 2 &gic 0 70 4>, + <0 0 3 &gic 0 160 4>, + <0 0 4 &gic 0 161 4>, + <0 0 5 &gic 0 162 4>, + <0 0 6 &gic 0 163 4>, + <0 0 7 &gic 0 164 4>, + <0 0 8 &gic 0 165 4>, + <0 0 9 &gic 0 166 4>, + <0 0 10 &gic 0 167 4>, + <0 0 11 &gic 0 168 4>, + <0 0 12 &gic 0 169 4>; + + motherboard { + model = "V2M-Juno"; + arm,hbi = <0x252>; + arm,vexpress,site = <0>; + arm,v2m-memory-map = "rs1"; + compatible = "arm,vexpress,v2p-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + usb@5,00000000 { + compatible = "nxp,usb-isp1763"; + reg = <5 0x00000000 0x20000>; + bus-width = <16>; + interrupts = <4>; + }; + + ethernet@2,00000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <2 0x00000000 0x10000>; + interrupts = <3>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + clocks = <&mb_eth25mhz>; + vdd33a-supply = <&soc_fixed_3v3>; /* change this */ + vddvario-supply = <&soc_fixed_3v3>; /* and this */ + }; + + iofpga@3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + v2m_sysreg: sysreg@010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + }; + + kmi@060000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <8>; + clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@070000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <8>; + clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + wdt@0f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x10000>; + interrupts = <7>; + clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x10000>; + interrupts = <9>; + clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; + clock-names = "timclken1", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x10000>; + interrupts = <9>; + clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; + clock-names = "timclken1", "apb_pclk"; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x10000>; + interrupts = <0>; + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + }; + }; + }; + }; + + fpgaosc0: fpgaosc@0 { + /* Internal FPGA 77 MHz clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <77000000>; + clock-output-names = "fpga:osc0"; + }; + + fpgaosc1: fpgaosc@1 { + /* Internal FPGA 67 MHz clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <67000000>; + clock-output-names = "fpga:osc1"; + }; + + fpgaosc2: fpgaosc@2 { + /* Internal FPGA 23.75 MHz clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <23750000>; + clock-output-names = "fpga:osc2"; + }; + + dcc_lt { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,site = <2>; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + db2oscclk2: osc@2 { + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <2000000 230000000>; + #clock-cells = <0>; + clock-output-names = "db2:osc2"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/juno.dts b/arch/arm64/boot/dts/juno.dts index 38490bbd1e8..a7119dc72f0 100644 --- a/arch/arm64/boot/dts/juno.dts +++ b/arch/arm64/boot/dts/juno.dts @@ -4,548 +4,14 @@ * Fast Models FVP v2 support */ -/dts-v1/; - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/thermal/thermal.h> +#include "juno-common.dtsi" / { - model = "Juno"; - compatible = "arm,juno", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - aliases { malidp0 = &dp0; malidp1 = &dp1; - serial0 = &soc_uart0; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster1: cluster1 { - #cooling-cells = <2>; /* min followed by max */ - - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - core2 { - cpu = <&CPU2>; - }; - core3 { - cpu = <&CPU3>; - }; - }; - - cluster0: cluster0 { - #cooling-cells = <2>; /* min followed by max */ - - core0 { - cpu = <&CPU4>; - }; - core1 { - cpu = <&CPU5>; - }; - }; - }; - - idle-states { - entry-method = "arm,psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - entry-method-param = <0x0010000>; - entry-latency-us = <40>; - exit-latency-us = <100>; - min-residency-us = <150>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - entry-method-param = <0x1010000>; - entry-latency-us = <500>; - exit-latency-us = <1000>; - min-residency-us = <2500>; - }; - }; - - CPU0:cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x0 0x100>; - enable-method = "psci"; - clocks = <&scpi_dvfs 1>; - clock-names = "vlittle"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - CPU1:cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x0 0x101>; - enable-method = "psci"; - clocks = <&scpi_dvfs 1>; - clock-names = "vlittle"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - CPU2:cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x0 0x102>; - enable-method = "psci"; - clocks = <&scpi_dvfs 1>; - clock-names = "vlittle"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - CPU3:cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x0 0x103>; - enable-method = "psci"; - clocks = <&scpi_dvfs 1>; - clock-names = "vlittle"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - CPU4:cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57","arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - clocks = <&scpi_dvfs 0>; - clock-names = "vbig"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - CPU5:cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57","arm,armv8"; - reg = <0x0 0x1>; - enable-method = "psci"; - clocks = <&scpi_dvfs 0>; - clock-names = "vbig"; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0x0 0x7f000000>, - <0x00000008 0x80000000 0x1 0x80000000>; - }; - - /* memory@14000000 { - device_type = "memory"; - reg = <0x00000000 0x14000000 0x0 0x02000000>; - }; */ - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0x2c010000 0 0x1000>, - <0x0 0x2c02f000 0 0x2000>, - <0x0 0x2c04f000 0 0x2000>, - <0x0 0x2c06f000 0 0x2000>; - interrupts = <GIC_PPI 9 0xf04>; - }; - - msi0: msi@2c1c0000 { - compatible = "arm,gic-msi"; - reg = <0x0 0x2c1c0000 0 0x10000 - 0x0 0x2c1d0000 0 0x10000 - 0x0 0x2c1e0000 0 0x10000 - 0x0 0x2c1f0000 0 0x10000>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 0xff01>, - <GIC_PPI 14 0xff01>, - <GIC_PPI 11 0xff01>, - <GIC_PPI 10 0xff01>; - }; - - timer@2a810000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x2a810000 0x0 0x10000>; - clock-frequency = <100000000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - frame@2a830000 { - frame-number = <1>; - interrupts = <0 60 4>; - reg = <0x0 0x2a830000 0x0 0x10000>; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <GIC_SPI 18 4>, - <GIC_SPI 22 4>, - <GIC_SPI 26 4>, - <GIC_SPI 30 4>, - <GIC_SPI 02 4>, - <GIC_SPI 06 4>; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0xC4000001>; - cpu_off = <0x84000002>; - cpu_on = <0xC4000003>; - migrate = <0xC4000005>; - sys_poweroff = <0x84000008>; - sys_reset = <0x84000009>; - }; - - pci0: pci@30000000 { - compatible = "arm,pcie-xr3"; - device_type = "pci"; - reg = <0 0x7ff30000 0 0x1000 - 0 0x7ff20000 0 0x10000 - 0 0x40000000 0 0x10000000>; - bus-range = <0 255>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x00 0x5ff00000 0x0 0x00100000 - 0x02000000 0x0 0x00000000 0x40 0x00000000 0x0 0x80000000 - 0x42000000 0x0 0x80000000 0x40 0x80000000 0x0 0x80000000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &gic 0 136 4 - 0 0 0 2 &gic 0 137 4 - 0 0 0 3 &gic 0 138 4 - 0 0 0 4 &gic 0 139 4>; - }; - - - mailbox: mhu@2b1f0000 { - compatible = "arm,mhu"; - reg = <0x0 0x2b1f0000 0x0 0x10000>, /* MHU registers */ - <0x0 0x2e000000 0x0 0x10000>; /* Payload area */ - interrupts = <0 36 4>, /* low priority interrupt */ - <0 35 4>; /* high priority interrupt */ - #mbox-cells = <1>; - mbox-names = "cpu_to_scp_low", "cpu_to_scp_high"; - mboxes = <&mailbox 0 &mailbox 1>; - }; - - clocks { - compatible = "arm,scpi-clks"; - - scpi_dvfs: scpi_clocks@0 { - compatible = "arm,scpi-clk-indexed"; - #clock-cells = <1>; - clock-indices = <0>, <1>, <2>; - clock-output-names = "vbig", "vlittle", "vgpu"; - }; - - scpi_clk: scpi_clocks@3 { - compatible = "arm,scpi-clk-range"; - #clock-cells = <1>; - clock-indices = <3>, <4>; - frequency-range = <23750000 165000000>; - clock-output-names = "pxlclk0", "pxlclk1"; - }; - - }; - - hwmon@1c010000 { - compatible = "arm,v2m-juno-meters"; - reg = <0x0 0x1c010000 0x0 0x1000>; - }; - - cpufreq { - compatible = "arm,scpi-cpufreq"; - }; - - scpi_sensor0: scpi-sensor@0 { - compatible = "arm,scpi-thermal"; - #thermal-sensor-cells = <1>; - }; - - thermal-zones { - soc_thermal { - polling-delay = <1000>; - polling-delay-passive = <100>; - sustainable-power = <2500>; - - thermal-sensors = <&scpi_sensor0 3>; - - trips { - threshold: trip-point@0 { - temperature = <55000>; - hysteresis = <1000>; - type = "passive"; - }; - target: trip-point@1 { - temperature = <80000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&cluster0 0 5>; - }; - map1 { - trip = <&target>; - cooling-device = <&cluster1 0 5>; - }; - map2 { - trip = <&target>; - cooling-device = <&gpu 0 4>; - }; - }; - }; - }; - - soc_uartclk: refclk72738khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <7273800>; - clock-output-names = "juno:uartclk"; - }; - - soc_refclk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "juno:clk24mhz"; }; - mb_eth25mhz: clk25mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "ethclk25mhz"; - }; - - soc_usb48mhz: clk48mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - clock-output-names = "clk48mhz"; - }; - - soc_smc50mhz: clk50mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "smc_clk"; - }; - - soc_refclk100mhz: refclk100mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "apb_pclk"; - }; - - soc_faxiclk: refclk533mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <533000000>; - clock-output-names = "faxi_clk"; - }; - - soc_fixed_3v3: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - memory-controller@7ffd0000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0 0x7ffd0000 0 0x1000>; - interrupts = <0 86 4>, - <0 87 4>; - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - chip5-memwidth = <16>; - }; - - dma0: dma@0x7ff00000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0x7ff00000 0 0x1000>; - interrupts = <0 95 4>, - <0 88 4>, - <0 89 4>, - <0 90 4>, - <0 91 4>, - <0 108 4>, - <0 109 4>, - <0 110 4>, - <0 111 4>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - clocks = <&soc_faxiclk>; - clock-names = "apb_pclk"; - }; - - soc_uart0: uart@7ff80000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0x7ff80000 0x0 0x1000>; - interrupts = <0 83 4>; - clocks = <&soc_uartclk>, <&soc_refclk100mhz>; - clock-names = "uartclk", "apb_pclk"; - dmas = <&dma0 1 - &dma0 2>; - dma-names = "rx", "tx"; - }; - - /* this UART is reserved for secure software. - soc_uart1: uart@7ff70000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0x7ff70000 0x0 0x1000>; - interrupts = <0 84 4>; - clocks = <&soc_uartclk>, <&soc_refclk100mhz>; - clock-names = "uartclk", "apb_pclk"; - }; */ - - ulpi_phy: phy@0 { - compatible = "phy-ulpi-generic"; - reg = <0x0 0x94 0x0 0x4>; - phy-id = <0>; - }; - - ehci@7ffc0000 { - compatible = "snps,ehci-h20ahb"; - /* compatible = "arm,h20ahb-ehci"; */ - reg = <0x0 0x7ffc0000 0x0 0x10000>; - interrupts = <0 117 4>; - clocks = <&soc_usb48mhz>; - clock-names = "otg"; - phys = <&ulpi_phy>; - }; - - ohci@0x7ffb0000 { - compatible = "generic-ohci"; - reg = <0x0 0x7ffb0000 0x0 0x10000>; - interrupts = <0 116 4>; - clocks = <&soc_usb48mhz>; - clock-names = "otg"; - }; - - i2c@0x7ffa0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x0 0x7ffa0000 0x0 0x1000>; - interrupts = <0 104 4>; - clock-frequency = <100000>; - i2c-sda-hold-time-ns = <500>; - clocks = <&soc_smc50mhz>; - - dvi0: dvi-transmitter@70 { - compatible = "nxp,tda998x"; - reg = <0x70>; - }; - - dvi1: dvi-transmitter@71 { - compatible = "nxp,tda998x"; - reg = <0x71>; - }; - }; - - i2c@0x6f190000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,versatile-i2c"; - reg = <0x0 0x6f190000 0x0 0x1000>; - - dvi2: dvi-transmitter@70 { - compatible = "nxp,tda998x"; - reg = <0x70>; - video-ports = <0x234501>; - }; - - dvi3: dvi-transmitter@71 { - compatible = "nxp,tda998x"; - reg = <0x71>; - video-ports = <0x234501>; - }; - }; - - /* mmci@1c050000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x0 0x1c050000 0x0 0x1000>; - interrupts = <0 73 4>, - <0 74 4>; - max-frequency = <12000000>; - vmmc-supply = <&soc_fixed_3v3>; - clocks = <&soc_refclk24mhz>, <&soc_refclk100mhz>; - clock-names = "mclk", "apb_pclk"; - }; */ - - hdlcd@7ff60000 { - compatible = "arm,hdlcd"; - reg = <0 0x7ff60000 0 0x1000>; - interrupts = <0 85 4>; - clocks = <&scpi_clk 0>; - clock-names = "pxlclk"; - i2c-slave = <&dvi0>; - - /* display-timings { - native-mode = <&timing0>; - timing0: timing@0 { - /* 1024 x 768 framebufer, standard VGA timings * / - clock-frequency = <65000>; - hactive = <1024>; - vactive = <768>; - hfront-porch = <24>; - hback-porch = <160>; - hsync-len = <136>; - vfront-porch = <3>; - vback-porch = <29>; - vsync-len = <6>; - }; - }; */ - }; - - /* hdlcd@7ff50000 { - compatible = "arm,hdlcd"; - reg = <0 0x7ff50000 0 0x1000>; - interrupts = <0 93 4>; - clocks = <&scpi_clk 1>; - clock-names = "pxlclk"; - i2c-slave = <&dvi1>; - - display-timings { - native-mode = <&timing1>; - timing1: timing@1 { - /* 1024 x 768 framebufer, standard VGA timings * / - clock-frequency = <65000>; - hactive = <1024>; - vactive = <768>; - hfront-porch = <24>; - hback-porch = <160>; - hsync-len = <136>; - vfront-porch = <3>; - vback-porch = <29>; - vsync-len = <6>; - }; - }; - }; */ - gpu: gpu@0x2d000000 { compatible = "arm,malit6xx", "arm,mali"; #cooling-cells = <2>; /* min followed by max */ @@ -556,165 +22,6 @@ clock-names = "clk_mali"; }; - - smb { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 15>; - interrupt-map = <0 0 0 &gic 0 68 4>, - <0 0 1 &gic 0 69 4>, - <0 0 2 &gic 0 70 4>, - <0 0 3 &gic 0 160 4>, - <0 0 4 &gic 0 161 4>, - <0 0 5 &gic 0 162 4>, - <0 0 6 &gic 0 163 4>, - <0 0 7 &gic 0 164 4>, - <0 0 8 &gic 0 165 4>, - <0 0 9 &gic 0 166 4>, - <0 0 10 &gic 0 167 4>, - <0 0 11 &gic 0 168 4>, - <0 0 12 &gic 0 169 4>; - - motherboard { - model = "V2M-Juno"; - arm,hbi = <0x252>; - arm,vexpress,site = <0>; - arm,v2m-memory-map = "rs1"; - compatible = "arm,vexpress,v2p-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - ranges; - - usb@5,00000000 { - compatible = "nxp,usb-isp1763"; - reg = <5 0x00000000 0x20000>; - bus-width = <16>; - interrupts = <4>; - }; - - ethernet@2,00000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <2 0x00000000 0x10000>; - interrupts = <3>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - clocks = <&mb_eth25mhz>; - vdd33a-supply = <&soc_fixed_3v3>; /* change this */ - vddvario-supply = <&soc_fixed_3v3>; /* and this */ - }; - - iofpga@3,00000000 { - compatible = "arm,amba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - v2m_sysreg: sysreg@010000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - }; - - kmi@060000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x060000 0x1000>; - interrupts = <8>; - clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@070000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x070000 0x1000>; - interrupts = <8>; - clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - wdt@0f0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f0000 0x10000>; - interrupts = <7>; - clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; - clock-names = "wdogclk", "apb_pclk"; - }; - - v2m_timer01: timer@110000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x110000 0x10000>; - interrupts = <9>; - clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; - clock-names = "timclken1", "apb_pclk"; - }; - - v2m_timer23: timer@120000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x120000 0x10000>; - interrupts = <9>; - clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; - clock-names = "timclken1", "apb_pclk"; - }; - - rtc@170000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x170000 0x10000>; - interrupts = <0>; - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - }; - }; - }; - }; - - fpgaosc0: fpgaosc@0 { - /* Internal FPGA 77 MHz clock */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <77000000>; - clock-output-names = "fpga:osc0"; - }; - - fpgaosc1: fpgaosc@1 { - /* Internal FPGA 67 MHz clock */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <67000000>; - clock-output-names = "fpga:osc1"; - }; - - fpgaosc2: fpgaosc@2 { - /* Internal FPGA 23.75 MHz clock */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <23750000>; - clock-output-names = "fpga:osc2"; - }; - - dcc_lt { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,site = <2>; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - db2oscclk2: osc@2 { - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <2000000 230000000>; - #clock-cells = <0>; - clock-output-names = "db2:osc2"; - }; - }; - dp0: display@6f200000 { compatible = "arm,mali-dp550"; reg = <0 0x6f200000 0 0x20000>; diff --git a/arch/arm64/boot/dts/juno_mali_fpga_T860_VP550_DP550_SMMU550.dts b/arch/arm64/boot/dts/juno_mali_fpga_T860_VP550_DP550_SMMU550.dts new file mode 100644 index 00000000000..59b3c4bafb4 --- /dev/null +++ b/arch/arm64/boot/dts/juno_mali_fpga_T860_VP550_DP550_SMMU550.dts @@ -0,0 +1,70 @@ +/* + * ARM Ltd. Juno Plaform + * + * Fast Models FVP v2 support + */ + +#include "juno-common.dtsi" + +/ { + aliases { + malidp0 = &dp0; + }; + + gpu: gpu@0x6f010000 { + compatible = "arm,malit6xx", "arm,mali"; + reg = <0x0 0x6f010000 0x0 0x4000>; + interrupts = <0 168 4>, <0 168 4>, <0 168 4>; + interrupt-names = "JOB", "MMU", "GPU"; + clocks = <&scpi_dvfs 2>; + clock-names = "clk_mali"; + }; + + dp0: display@6f200000 { + compatible = "arm,mali-dp550"; + reg = <0 0x6f200000 0 0x40000>; + interrupts = <0 168 4>, <0 168 4>; + interrupt-names = "DE", "SE"; + clocks = <&db2oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>; + clock-names = "pxclk", "mclk", "aclk", "pclk"; + de-axi-burst-length = <32>; + de-axi-outstanding-transactions = <15>; + se-axi-burst-length = <32>; + se-axi-outstanding-transactions = <15>; + se-axi-awqos = <0>; + se-axi-awcache = <0>; + #stream-id-cells = <5>; + port { + dp0_out: endpoint { + remote-endpoint = <&tx0_in>; + }; + }; + }; + + test-transmitters { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + tx0: video_tx@0 { + compatible = "generic,slave_enc_video_tx"; + reg = <0>; + i2c-slave = <&dvi2>; + type = "HDMI"; + type-idx = <0>; + port { + tx0_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; + }; + + smmu@6f300000 { + compatible = "arm,mmu-500"; + reg = <0 0x6f300000 0 0x10000>; + #global-interrupts = <1>; + interrupts = <0 168 4>, <0 168 4>, <0 168 4>; + mmu-masters = <&dp0 0x008 0x009 0x00a 0x00b 0x00c>; + }; +}; |