diff options
| author | Ryan Harkin <ryan.harkin@linaro.org> | 2016-01-29 17:26:08 +0000 |
|---|---|---|
| committer | Ryan Harkin <ryan.harkin@linaro.org> | 2017-01-05 10:08:57 +0000 |
| commit | dae8db02d9bdcb0c0b7a9924f735249c8fa10210 (patch) | |
| tree | 30f168f5a6b5cba4f6ae37e7b3da84514e096dba | |
| parent | 4b9a3cc5675669bfd790a8812b600b5c2f615af1 (diff) | |
HACK: Platforms/ARM: TC2: set gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride TRUEarmlt-20170206-001armlt-20170116-001armlt-20170110-001armlt-17.0117.01
Mainline Tianocore EDK2 fails to boot on TC2. I tested pure upstream
code at this commit:
f447734 2016-01-26 MdeModulePkg:Make the logic in ConfigRouting.c clear and safe [Dandan Bi]
The following trace is shown on the serial console:
------------------------------------------------------------------------
Loading driver at 0x000BF805000 EntryPoint=0x000BF805251 FaultTolerantWriteDxe.efi
Data Abort Exception PC at 0xBF8BDFF8 CPSR 0xA0000113 NzCveAift_svc
/working/platforms/uefi/edk2/Build/ArmVExpress-CTA15-A7/DEBUG_GCC49/ARM/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe/DEBUG/VariableRuntimeDxe.dll
loaded at 0xBF8B4000 (PE/COFF offset) 0x9FF8 (ELF or Mach-O offset)
0x8FF8
0xE1901F9F LDREX r1, [r0]
R0 0xBF8E0A34 R1 0xBF8C4F90 R2 0x00000002 R3 0xBF8E0A34
R4 0x00000044 R5 0x00000400 R6 0x00000000 R7 0xB000021C
R8 0x80000100 R9 0xB8000000 R10 0xBFFEC000 R11 0x00000000
R12 0x00000000 SP 0xBFFFFB08 LR 0xBF8BDF1B PC 0xBF8BDFF8
DFSR 0x00001008 DFAR 0xBF8E0A34 IFSR 0x00001236 IFAR 0xED414047
Precise External Abort: read from 0xBF8E0A34
Instruction Access Flag fault on Page at 0xED414047
ASSERT [ArmCpuDxe]
/working/platforms/uefi/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/DefaultExceptionHandler.c(260):
((BOOLEAN)(0==1))
------------------------------------------------------------------------
'git bisect' shows that the commit below causes the problem:
------------------------------------------------------------------------
commit 0c9a522f28772049ae37c85b8ae589a98d2d3b81
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date: Thu Nov 12 11:40:57 2015 +0000
ArmPkg/ArmLib: mark all cached mappings as (inner) shareable
Mark all cached memory mappings as shareable (or inner shareable on
AArch64) so that our view of memory is kept coherent by the hardware.
This is relevant for things like coherent DMA and virtualization (where
a guest may migrate to another core) but in general, since UEFI on ARM
is mostly used in a context where the secure firmware and possibly a
secure OS are already up and running, it is best to refrain from using
any non-shareable mappings.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18778 6f19259b-4bc3-4df7-8a09-765794883524
------------------------------------------------------------------------
Only the revert of the change to TT_DESCRIPTOR_SECTION_WRITE_BACK is
needed to get TC2 working again.
However, the topic was discussed on the mailing list:
https://www.mail-archive.com/edk2-devel@lists.01.org/msg03974.html
The correct solution for platforms that wish to revert this behaviour
is to set the following PCD to TRUE:
gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride
However, for TC2 should not need to do this. Work continues to
ascertain why TC2 breaks with shareable mappings. Current thinking is
that CCI-400 needs configuring before shareable mappings will work.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
| -rw-r--r-- | Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc index 69048a3..ae91a78 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc @@ -74,6 +74,7 @@ ################################################################################
[PcdsFeatureFlag.common]
+ gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|TRUE
gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
|