1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
|
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&soc {
gpu: qcom,adreno-3xx@01c00000 {
compatible = "qcom,adreno-3xx";
#stream-id-cells = <16>;
reg = <0x01c00000 0x20000>;
reg-names = "kgsl_3d0_reg_memory";
interrupts = <0 33 0>;
interrupt-names = "kgsl_3d0_irq";
clock-names =
"core_clk",
"iface_clk",
"mem_clk",
"mem_iface_clk",
"alt_mem_iface_clk",
"gfx3d_clk_src";
clocks =
<&gcc GCC_OXILI_GFX3D_CLK>,
<&gcc GCC_OXILI_AHB_CLK>,
<&gcc GCC_OXILI_GMEM_CLK>,
<&gcc GCC_BIMC_GFX_CLK>,
<&gcc GCC_BIMC_GPU_CLK>,
<&gcc GFX3D_CLK_SRC>;
power-domains = <&gcc OXILI_GDSC>;
qcom,chipid = <0x03000600>;
qcom,gpu-pwrlevels {
compatible = "qcom,gpu-pwrlevels";
qcom,gpu-pwrlevel@0 {
qcom,gpu-freq = <400000000>;
};
qcom,gpu-pwrlevel@1 {
qcom,gpu-freq = <19200000>;
};
};
};
mdss_mdp: qcom,mdss_mdp@1a00000 {
compatible = "qcom,mdss_mdp";
reg = <0x1a00000 0x90000>,
<0x1ac8000 0x3000>;
reg-names = "mdp_phys", "vbif_phys";
interrupts = <0 72 0>;
interrupt-controller;
#interrupt-cells = <1>;
power-domains = <&gcc MDSS_GDSC>;
connectors = <&mdss_dsi0>;
gpus = <&gpu>;
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc MDP_CLK_SRC>,
<&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_VSYNC_CLK>;
clock-names = "iface_clk", "bus_clk", "core_clk_src",
"core_clk", "lut_clk", "vsync_clk";
};
mdss_dsi0: qcom,mdss_dsi@1a98000 {
compatible = "qcom,mdss-dsi-ctrl";
label = "MDSS DSI CTRL->0";
qcom,dsi-host-index = <0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1a98000 0x25c>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss_mdp>;
interrupts = <4 0>;
vdda-supply = <&pm8916_l2>;
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l6>;
clocks = <&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_BYTE0_CLK>,
<&gcc GCC_MDSS_PCLK0_CLK>,
<&gcc GCC_MDSS_ESC0_CLK>,
<&gcc BYTE0_CLK_SRC>,
<&gcc PCLK0_CLK_SRC>;
clock-names = "mdp_core_clk", "iface_clk", "bus_clk",
"core_mmss_clk", "byte_clk", "pixel_clk",
"core_clk", "byte_clk_src", "pixel_clk_src";
qcom,dsi-phy = <&mdss_dsi_phy0>;
};
mdss_dsi_phy0: qcom,mdss_dsi_phy@1a98300 {
compatible = "qcom,dsi-phy-28nm-lp";
qcom,dsi-phy-index = <0>;
power-domains = <&gcc MDSS_GDSC>;
reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
reg = <0x1a98300 0xd4>,
<0x1a98500 0x280>,
<0x1a98780 0x30>;
clocks = <&gcc GCC_MDSS_AHB_CLK>;
clock-names = "iface_clk";
vddio-supply = <&pm8916_l6>;
};
};
|
