diff options
Diffstat (limited to 'drivers/char/drm/radeon_cp.c')
| -rw-r--r-- | drivers/char/drm/radeon_cp.c | 79 |
1 files changed, 44 insertions, 35 deletions
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c index 6e13f4bec91..38eda336a65 100644 --- a/drivers/char/drm/radeon_cp.c +++ b/drivers/char/drm/radeon_cp.c @@ -109,9 +109,9 @@ static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr) { u32 ret; - RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f); - ret = RADEON_READ(RADEON_IGPGART_DATA); - RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f); + RADEON_WRITE(RS400_NB_MC_INDEX, addr & 0x7f); + ret = RADEON_READ(RS400_NB_MC_DATA); + RADEON_WRITE(RS400_NB_MC_INDEX, 0x7f); return ret; } @@ -613,14 +613,18 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) (long)dev_priv->gart_info.bus_addr, dev_priv->gart_size); - RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000); - RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1); - RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800); - RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR, + RADEON_WRITE_IGPGART(RS400_MC_MISC_CNTL, RS400_GART_INDEX_REG_EN); + RADEON_WRITE_IGPGART(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN | + RS400_VA_SIZE_32MB)); + RADEON_WRITE_IGPGART(RS400_GART_FEATURE_ID, (RS400_HANG_EN | + RS400_TLB_ENABLE | + RS400_GTW_LAC_EN | + RS400_1LEVEL_GART)); + RADEON_WRITE_IGPGART(RS400_GART_BASE, dev_priv->gart_info.bus_addr); - temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39); - RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp); + temp = RADEON_READ_IGPGART(dev_priv, RS400_AGP_MODE_CNTL); + RADEON_WRITE_IGPGART(RS400_AGP_MODE_CNTL, temp); RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start); dev_priv->gart_size = 32*1024*1024; @@ -629,13 +633,13 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) dev_priv->gart_size) & 0xffff0000) | (dev_priv->gart_vm_start >> 16))); - temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE); - RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp); + temp = RADEON_READ_IGPGART(dev_priv, RS400_AGP_ADDRESS_SPACE_SIZE); + RADEON_WRITE_IGPGART(RS400_AGP_ADDRESS_SPACE_SIZE, temp); - RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH); - RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1); - RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH); - RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0); + RADEON_READ_IGPGART(dev_priv, RS400_GART_CACHE_CNTRL); + RADEON_WRITE_IGPGART(RS400_GART_CACHE_CNTRL, RS400_GART_CACHE_INVALIDATE); + RADEON_READ_IGPGART(dev_priv, RS400_GART_CACHE_CNTRL); + RADEON_WRITE_IGPGART(RS400_GART_CACHE_CNTRL, 0); } } @@ -650,21 +654,26 @@ static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on) (long)dev_priv->gart_info.bus_addr, dev_priv->gart_size); - temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL); - RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000); + temp = RS690_READ_MCIND(dev_priv, RS400_MC_MISC_CNTL); + RS690_WRITE_MCIND(RS400_MC_MISC_CNTL, (RS400_GART_INDEX_REG_EN | + RS690_BLOCK_GFX_D3_EN)); - RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, - RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB); + RS690_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN | + RS400_VA_SIZE_32MB)); - temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID); - RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800); + temp = RS690_READ_MCIND(dev_priv, RS400_GART_FEATURE_ID); + RS690_WRITE_MCIND(RS400_GART_FEATURE_ID, (RS400_HANG_EN | + RS400_TLB_ENABLE | + RS400_GTW_LAC_EN | + RS400_1LEVEL_GART)); temp = dev_priv->gart_info.bus_addr & 0xfffff000; temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; - RS690_WRITE_MCIND(RS690_MC_GART_BASE, temp); + RS690_WRITE_MCIND(RS400_GART_BASE, temp); - temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL); - RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000); + temp = RS690_READ_MCIND(dev_priv, RS400_AGP_MODE_CNTL); + RS690_WRITE_MCIND(RS400_AGP_MODE_CNTL, ((1 << RS400_REQ_TYPE_SNOOP_SHIFT) | + RS400_REQ_TYPE_SNOOP_DIS)); RS690_WRITE_MCIND(RS690_MC_AGP_BASE, (unsigned int)dev_priv->gart_vm_start); @@ -677,32 +686,32 @@ static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on) RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp); - temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE); - RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, - RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB); + temp = RS690_READ_MCIND(dev_priv, RS400_AGP_ADDRESS_SPACE_SIZE); + RS690_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, (RS400_GART_EN | + RS400_VA_SIZE_32MB)); do { - temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL); + temp = RS690_READ_MCIND(dev_priv, RS400_GART_CACHE_CNTRL); if ((temp & RS690_MC_GART_CLEAR_STATUS) == RS690_MC_GART_CLEAR_DONE) break; DRM_UDELAY(1); } while (1); - RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL, - RS690_MC_GART_CC_CLEAR); + RS690_WRITE_MCIND(RS400_GART_CACHE_CNTRL, + RS400_GART_CACHE_INVALIDATE); + do { - temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL); + temp = RS690_READ_MCIND(dev_priv, RS400_GART_CACHE_CNTRL); if ((temp & RS690_MC_GART_CLEAR_STATUS) == - RS690_MC_GART_CLEAR_DONE) + RS690_MC_GART_CLEAR_DONE) break; DRM_UDELAY(1); } while (1); - RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL, - RS690_MC_GART_CC_NO_CHANGE); + RS690_WRITE_MCIND(RS400_GART_CACHE_CNTRL, 0); } else { - RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS); + RS690_WRITE_MCIND(RS400_AGP_ADDRESS_SPACE_SIZE, 0); } } |