diff options
| author | David Woodhouse <David.Woodhouse@intel.com> | 2012-11-21 10:38:13 +0000 |
|---|---|---|
| committer | David Woodhouse <David.Woodhouse@intel.com> | 2012-11-21 10:38:13 +0000 |
| commit | 851462444d421c223965b12b836bef63da61b57f (patch) | |
| tree | 495baa14e638817941496c36e1443aed7dae0ea0 /arch/mips/include/asm/cpu.h | |
| parent | 5a6ea4af0907f995dc06df21a9c9ef764c7cd3bc (diff) | |
| parent | 6924d99fcdf1a688538a3cdebd1f135c22eec191 (diff) | |
Merge branch 'for-3.7' of git://git.infradead.org/users/dedekind/l2-mtd
Conflicts:
drivers/mtd/nand/nand_base.c
Diffstat (limited to 'arch/mips/include/asm/cpu.h')
| -rw-r--r-- | arch/mips/include/asm/cpu.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 554e2d29965..52c4e914f95 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -320,7 +320,8 @@ enum cpu_type_enum { #define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ #define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ -#define MIPS_CPU_RIXI 0x00400000 /* CPU has TLB Read/eXec Inhibit */ +#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */ +#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */ /* * CPU ASE encodings @@ -331,6 +332,7 @@ enum cpu_type_enum { #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ +#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */ #endif /* _ASM_CPU_H */ |